JPH0677241B2 - Processor - Google Patents

Description

The present invention relates to an arithmetic processing unit forming a part of an information processing apparatus, and more particularly to a cache in an arithmetic processing unit including a cache memory and a plurality of LSI chips.・ With memory
The present invention relates to a technology for data transfer with an LSI chip.

[Conventional technology]

In recent years, the integration of electronic devices has made remarkable progress, and high-performance arithmetic processing devices have also been realized by several LSI chips.

By the way, in such a high-performance arithmetic processing device, a cache memory is adopted for the purpose of further increasing the processing speed. However, when there are a plurality of LSI chips, the read destination and the write source of the cache memory are Since it will be spread over multiple LSI chips, and the number of pins of the cache memory will become enormous if each data path is provided, the data path is generally made into a bus and commonly used by each LSI chip. I try to stay within the pin count limit.

[Problems to be Solved by the Invention] As described above, the conventional arithmetic processing device is
The number of pins of the cache memory has been reduced by making the data path for accessing the memory a bus. However, when the number of LSI chips connected to the bus increases, the line length of the bus increases, and the delay time of signals on the bus increases due to an increase in capacitance, which makes it impossible to access the cache memory at high speed.

Since it is a bus system, the data widths of all the LSI chips must be the same, and for LSI chips with different data widths, it is necessary to provide a data alignment circuit before the input / output terminals.

There were drawbacks such as.

In particular, in an arithmetic processing unit in which access to the cache memory is pipelined, the increase in the read time of the cache memory is a direct factor that prevents the shortening of the machine cycle. However, the countermeasure against was an important issue. In addition, since the increase of hardware also brings about, it was an important issue to reduce it.

The present invention has been proposed in view of the above points, and an object of the present invention is to provide an arithmetic processing device capable of performing high-speed cache memory access and reducing hardware. Especially.

[Means for Solving the Problems]

In order to achieve the above-mentioned object, the present invention comprises a cache memory and a plurality of LSI chips having non-uniform data widths, and the cache memory and two or more LSI chips.
In an arithmetic processing unit that transfers data to and from a chip, a cross
The cache memory and two or more LSI chips are connected via a chip having a bar switch function and a function of aligning data and converting a data width.

[Action]

In the arithmetic processing unit of the present invention, the cache memory is provided via the chip having the cross bar switch function.
Data is transferred to and from the LSI chip, and if necessary, data width conversion is performed so as to match the data width of the transfer destination LSI chip.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus including an arithmetic processing unit of the present invention. In FIG. 1, reference numeral 90 denotes an arithmetic processing unit which is the object of the present invention.
Reference numeral 90 is connected to a main storage device 91, an input / output control device 92, and a system control device 93 via a system bus 94. Although not shown in FIG. 1, in the multiprocessor configuration, several other arithmetic processing units are connected to the system bus 94.
When a main memory capacity is further increased, a plurality of main memory devices are connected to the system bus 94.

Further, the arithmetic processing unit 90 includes each LSI chip constituting the instruction control circuit 10, the address translation control circuit 20, the bus control circuit 30, the arithmetic control circuit 40, the high speed arithmetic circuit 50, and the control memory circuit 60, and a plurality of random numbers. Control memory 85 consisting of access memory (RAM), cache memories 83, 84, address array (AA) 81, copy address array (CAA) 82, and multiple LSI chips It is composed of a crossbar switch 70 and the like.

Next, the read operation operation for the cache memories 83, 84 and the main memory 91 will be described. First, an instruction or operand read instruction and a read address are transferred from the instruction control circuit 10 to the address conversion control circuit 20 via a connection line 102. When the read address is a virtual address, the virtual address is translated in the address translation control circuit 20 into a real address. The address translation control circuit 20 outputs the read real address on the connection lines 201, 202, 203, 204, stores the correspondence relationship between the cache memories 83, 84 and the main storage device 91, that is, the cache memory 83, 84 registration information and determines the presence or absence of registration. Based on the signal returned from the address array 81 via the connection 202 ', it is determined whether or not there is a cache hit (registered), and if it is a cache hit, the read data from the cache memory 83 or the cache memory 84 is valid. Then, the data is returned to the read-out LSI chip via the cross bar switch 70. Generally, the return destination is the instruction control circuit 10 when reading an instruction.
The operation control circuit 40 is used for reading operands, but the address translation control circuit 20 is used for special operations.
It may also be the high-speed arithmetic circuit 50. On the other hand, if there is no cache hit (called cache miss or NFB), the bus control circuit 30 sets the system bus.
A block transfer request is sent to the main storage device 91 via 94. Then, the data returned from the main storage device 91 is
After passing through the bus control circuit 30, the data is written in the cache memory 83 or the cache memory 84 by the connection 307, the cross bar switch 70, the connection 837 or the connection 847. The first return data from the main storage device 91 is returned from the cross bar switch 70 to the return destination. The read operation is executed as described above.

Next, the write operation operation for the cache memories 83, 84 and the main memory 91 will be described. First, the write instruction and the write address are created in the instruction control circuit 10 when the instruction control circuit 10 decodes an instruction requiring the write operation or when the micro program executes the write operation, and the connection 102
Is sent to the address translation control circuit 20 via. If the write address is a virtual address, it is converted to a real address by the address conversion control circuit 20, and then stored in a register that holds the write address in the address conversion control circuit 20, and the write data is stored in the high-speed arithmetic circuit 50 or the like. At the time of preparation, writing to the cache memory 83 or the cache memory 84 and a write instruction to the main memory 91,
The write address and write data are sent to the bus control circuit 30. However, writing to the cache memory 83 or the cache memory 84 is performed only when the corresponding address is registered in the cache memory 83 or the cache memory 84. In the bus control circuit 30, the main storage device 91 is connected via the system bus 94.
Write to. The write data is prepared in the arithmetic control circuit 40 mainly under the control of the micro program, sent to the register holding the write data in the high-speed arithmetic circuit 50 through the connection 405, and then synchronized with the write address. Sent to the crossbar switch 70 via the connection 507, and the bus control circuit 30 and cache
It is transferred to the memory 83 or the cache memory 84.
The write operation is executed as described above.

The data read operation and the data write operation for the cache memories 83, 84 and the main memory 91 are executed as described above, but the data lines to which the data are transferred all constitute each circuit as shown in the figure. The LSI chips are arranged so as to be connected to each other in a one-to-one manner, and other than the connection selected by the cross bar switch 70 is not affected, and the line of the access path is minimized. Since each LSI chip can be mounted on the package, the delay time due to the data line on the package can be significantly reduced. That is, when the conventional device is applied to the embodiment shown in FIG.
Conventionally, since the connection 207, 107, 407, 507, 307, 837, 847 had a bus configuration in which they were connected in parallel, the total line length became long, the capacitance increased and the delay time at the time of data transfer increased, but the present invention According to the above, since only the capacitance of the connection selected by the crossbar switch 70 is relevant and the shortest access path can be obtained, the delay time due to the capacitance is significantly reduced. It can be done.

Next, FIG. 2 shows the crossbar switch in FIG.
FIG. 30 is a configuration diagram showing an example of an internal configuration of 70. In FIG. 2, reference numerals 847, 837, 307, 207, 507, 407, 107 denote cache memory 84, cache memory 83, bus control circuit 30, address translation control circuit 20, respectively, as shown in FIG.
The wiring is connected to the high-speed arithmetic circuit 50, arithmetic control circuit 40, and instruction control circuit 10. It should be noted that although illustrated in a simplified manner in the figure, the connection lines 847, 837, 307, 207, 507, 107 have a data width of, for example, 8 bytes (64 bits). However, the data width of only the connection 407 is different from the others, and is, for example, 4 bytes. Then connection 847,837,307,207,50
Selectors 710 to 716 and input / output drivers are provided corresponding to 7,407 and 107, respectively, and selectors 710 to 71 are provided as connection lines 205 which are control lines of the crossbar switch 70.
The select signals 205-S0 to 205-S6 of 6 and the output enable signals 205-E0 to 205-E4 of the driver are given, and the address translation control circuit 20 controls the individual selectors 710 to 716 independently. Has become. For example, cache
When data is read from the memory 83 to the instruction control circuit 10, the selector 716 connects the connection 107 and the connection 837.

As another feature of the present invention, the cross bar switch 70 has a function of converting the data width, and LSI chips having non-uniform data widths can be coupled to each other. For example, when data is read to the arithmetic control circuit 40 (only the connection 407 has a data width different from others as described above, for example, 4 bytes),
At the time of cache access, the selector 715 selects the input data of the connection 837 or the connection 847 according to the read address, and further selects either the upper 4 bytes or the lower 4 bytes of the 8 bytes according to the read address. As the select signal 205-S5 is given,
Operation control circuit with byte data as 4 byte data
Can be returned to 40. When reading data to another LSI chip, for example, the instruction control circuit 10, the data width of the connection line 107 is 8 bytes, which is the same as the cache memories 83, 84, etc., so that selection in 4-byte units is not necessary.

Next, FIG. 3 shows the address conversion control circuit 20 in FIG.
3 shows a part of the internal configuration of the. In FIG. 3, a request code is a code including information for instructing a read operation or a write operation given from the instruction control circuit 10, and a request address is a read / write address given by the instruction control circuit 10 (instruction control If the read / write address given from the circuit 10 is a virtual address, it is after being converted to a real address.

The operation will be described below. First, connection 20-101 and connection 2
When the request code and the request address are given to 0-201, the request code is set in the request code register 20-10, and the request address is set in the real address register 20-20. In the normal state, the request address is set in the real address register 20-20 when the request is received, and at the same time,
AA address register 20-30 and DA address register
Part of the requested address is also set in 20-40 or DA address register 20-41. During a read or write operation, an address is given from the AA address register 20-30, DA address register 20-40, 20-41 to the connection lines 202-204, and the address array 81 and the cache memory 83 or the cache memory 84 are supplied. And are read and the address array 81 is checked for a cache hit. In the case of a read operation, if a cache hit, the data read from the cache memory 83 or the cache memory 84 is returned to the read destination via the crossbar switch 70. Whether the read data is returned from the cache memory 83 or the cache memory 84 is determined according to a predetermined 1-bit value in the request address, and the value of this bit is "0".
When, the cache memory 83 (bank # 0) is selected, and when it is "1", the cache memory 84 (bank # 1) is selected. On the other hand, if there is no cache hit (cache miss), the real address register 20-20
The address of the block transfer to the main memory device 91 is sent from the bus control circuit 30 to the bus control circuit 30 via the connection 201 through the selector 20-23, and when the block transfer data read by the bus control circuit 30 is returned for the first time, the data is transferred. Is returned to the read destination via the cross bar switch 70 and simultaneously registered in the cache memory 83 or the cache memory 84. When the block size is 32 bytes and the data transfer width is 8 bytes, the 8-byte transfer is executed four times for the block transfer. Also, cache memory 8
If the banks of 3,84 are divided at the 5th bit from the lower address, that is, at the 16-byte boundary, the block transfer data is cache memory 83 and cache memory 84.
It will be written twice to 16 bytes each.

On the other hand, if the instruction of the write operation is set in the request code register 20-10, the address array 81
Is executed and the cache memory 83 or the cache memory 84 is read, the request address (write address) is set in the real address register 20-20 to the real address register 20-22, and the cache memory The read data from 83 or cache memory 84 is set in data registers 20-50. In addition, information on whether or not a cache hit is input to the decoder 20-11,
Set in request code register 20-12. In the case of the write operation as described above, processing is performed from the first stage of the request code register 20-10 and the real address register 20-20 to the second stage of the request code register 20-12 and the real address register 20-22. , And the subsequent stage can be accepted by vacating the first stage. That is, since it is necessary to wait for write data in the write operation, such processing is possible.

Now, the request code and the request address of the write operation set in the request code register 20-12 and the real address register 20-22 of the second stage are the high speed operation circuit.
Wait for write data to be prepared in the write data register in 50, and perform the write operation when the write data is prepared. Although not a direct content of the present invention, in this embodiment, in the case of a cache hit, even if a partial write in which all the data (for example, 8 bytes) within the data width is not rewritten at the time of writing, Write all data to rewrite all data, especially main memory
The processing speed for writing to 91 can be improved. That is, in a state where the reference of the address array 81 and the reading of the cache memory 83 or the cache memory 84 are executed, the read data of the cache memory 83 or the cache memory 84 is connected to the data register 20- When the write data is prepared, the high-speed arithmetic circuit 50
From the data register 20-50 of the address translation control circuit 20 to the pre-write data transferred via the selector 20-51 and the connection 207 from the crossbar switch 70. Then, the data is exchanged in byte units, and new write data is created. That is, a write mask (8 bits when the data width is 8 bytes) is provided for each byte, and only the byte whose mask is "1" can be replaced with the pre-write data. That is, the write data of the connection 507 is selected in the byte whose write mask is "1", and the pre-write data of the connection 207 is selected in the byte whose write mask is "0". This write mask together with the write data is connected to the crossbar switch 7 via connection 507.
It is sent to 0, and is received by the write mask receiving unit 720 and then used for controlling the selector in the same manner as the control signal by the connection 205. By this operation, at the time of cache hit, it is possible to write all to the bus control circuit 30 and the main memory 91 even for write operations that are not all write. That is, full writing becomes possible. In the case of a cache hit, the contents of the data register 20-50 are pre-write data, so the above processing is possible, but in the case of a cache miss, the contents are undefined (only parity is guaranteed. ). Therefore, full writing cannot be performed. In the case of such a cache miss, since full writing is impossible, if 2-byte writing is performed, it is sent as it is to the bus control circuit 30 as 2-byte partial writing, and writing to the cache memories 83 and 84 is not executed. In general, the main memory 91 has an error correction code (ECC) in units of 8 bytes and corrects a read 1-bit error. Therefore, for example, writing other than 8-byte full writing such as 2-byte partial writing is performed. At the time of execution, after reading the corresponding 8-byte boundary data,
It is necessary to replace only 2 bytes of the write data and recreate the error correction code in units of 8 bytes and write it together with the data, which may result in a longer processing time than all writes. In that case In order to remedy this delay in processing time, the cache memory 83, 84 in the arithmetic processing unit 90 previously executes the above processing, and the main memory 91 is written as a full write operation. It is possible to shorten the processing time.

On the other hand, although not a direct content of the present invention, in FIG. 3, the request code register and the real address register are two stages, and the cache memories 83, 84 divided into two banks. Simultaneously write to
It can be read. Below, the second stage request code register 20-12, the real address register 2
The operation will be described for the case where the write operation is set to 0-22 and the read operation is set to the request code register 20-10 and the real address register 20-20 of the first stage. In this case, the operation differs depending on the bank of the cache memory for writing and reading. The bank selection is performed according to a predetermined 1-bit value in the request address as described above.

(1) In the case of the same bank In this case, the write operation of the second stage is prioritized and the DA address register 20-40 or DA address
In the register 20-41, part of the write address (contents of the real address register 20-22) is selected by the selectors 20-23, 20-42, 20.
It is set via -43, and secures the write address to the cache memory 83 or the cache memory 84,
Writing is done. Further, the read operation of the first stage is performed by waiting for the completion of the write operation.

(2) In the case of another bank In this case, for example, writing is bank # 0 (cache memory 83) and reading is bank # 1 (cache memory 8).
In the case of 4), part of the write address is set in the DA address register 20-40, and part of the read address is set in the AA address register 20-30 and DA address register 20-41. Therefore, in the second stage, the address of the cache memory 83 is secured by the DA address register 20-40, the write data is created by the connections 507 and 207, and the connection 8
At the same time that the data is written to the cache memory 83 by 37, the write data is sent to the bus control circuit 30 through the connection 307 to write to the main memory 91. In parallel with this, in the first stage AA address registers 20-30 and DA
Address array 81 by address register 20-41
The address of the cache memory 84 is secured, and the data of the cache memory 84 is read by the connection 847. At this time, if the read destination is the instruction control circuit 10 or the operation control circuit 40, the read data can be returned.
However, high-speed arithmetic circuit 50 or address translation control circuit 20
Cannot be read because they are used by the second stage write operations.

〔The invention's effect〕

As described above, in the arithmetic processing unit of the present invention, the cache is directly cached by the chip having the crossbar switch function without using the bus method for the data path for reading and writing of the cache memory.・ Memory and LSI
Since the connection with the chip is made, the total line length forming the data path for data transfer can be minimized, and high-speed cache memory access can be realized. There is. Also,
Since the data width can be converted as needed by the chip with the cross bar switch function, even if LSI chips with different data widths are mixed, it is possible to respond as is by changing the control signal. Since no special data alignment circuit is required, there is an effect that the hardware can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing apparatus including an arithmetic processing unit of the present invention, FIG. 2 is an internal block diagram of a crossbar switch in FIG. 1, and FIG. 3 is an address conversion control circuit in FIG. It is a figure which shows a part of internal structure of. In the figure, 90 ... arithmetic processing unit, 91 ... main memory unit,
92 ... I / O controller, 93 ... System controller, 94 ...
... System bus, 10 ... Command control circuit, 20 ... Address translation control circuit, 30 ... Bus control circuit, 40 ... Operation control circuit, 50 ... High-speed operation circuit, 60 ... Control memory circuit, 70 ...
… Crossbar switch, 81 …… Address array,
82 ... Copy address array, 83, 84 ... Cache memory, 85 ... Control memory.

Claims (1)

[Claims] 1. An arithmetic processing unit comprising a cache memory and a plurality of LSI chips having non-uniform data widths, wherein data is transferred between the cache memory and two or more of the LSI chips. A cross bar that can connect any input / output terminals
An arithmetic processing unit characterized in that the cache memory and two or more LSI chips are connected via a chip having a switch function and a function of aligning data and converting a data width.