JPH067655B2 - Polarity judgment circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a polarity determination circuit used in a receiver of a digital transmission network including a transmitter, a receiver, and a transmission line between the transmitter and the receiver. Regarding

[Prior Art] The digital transmission network is typically ISDN (Integrated Services Digital Network), and the transmission path is typically a two-wire metallic cable. The transmitter transmits the time division multiplexed digital signal to the transmission line. The time division multiplexed digital signal may be a multilevel coded signal.

In the time division multiplexed digital signal, each multiframe is
.. and N.sup.th (N is a first integer equal to or greater than 3) frames are included. The first frame of each multi-frame includes a multi-frame sync signal that represents a first predetermined sync word and a transmit data signal that follows the multi-frame sync signal. The first predetermined sync word comprises at least one symbol.

Each of the second to Nth frames of each multiframe is
It includes a frame sync signal representing a second predetermined sync word and a transmit data signal following the frame sync signal. In ISDN, the second predetermined sync word is generally defined by inverting the first predetermined sync word.

The receiving unit receives the time division multiplexed digital signal from the transmission line as a received digital signal. The received digital signal has a true polarity equal to the polarity of the time-division multiplexed digital signal when the transmission line composed of the two-wire metallic cable is correctly connected, that is, properly connected, between the transmitter and the receiver. have. When the transmission line is incorrectly connected, i.e., vice versa, in polarity between the transmitter and the receiver, the received digital signal has an inverted polarity with respect to the true polarity.

[Problems to be Solved by the Invention] In order to correctly decode the transmission data signal in the receiving unit, regardless of whether the transmission line is correctly or incorrectly connected in polarity between the transmitting unit and the receiving unit, A polarity determination circuit is needed to determine if the received digital signal for the unit has a true or inverted polarity.

Therefore, an object of the present invention is to provide a polarity determination circuit which is used in a receiver of a digital transmission network and determines whether a received digital signal has a true polarity or an inverted polarity.

Another object of the present invention is to provide a polarity determination circuit that can determine whether a received digital signal has a true polarity or an inverted polarity by using a frame synchronization signal.

Yet another object of the present invention is to provide a polarity determination circuit having a simple structure.

[Means for Solving the Problems] According to the present invention, there is provided a polarity determination circuit used in a receiver of a digital transmission network including a transmitter, a receiver, and a transmission line between the transmitter and the receiver. , The transmitting unit transmits a time division multiplexed digital signal including consecutive multiframes in which each multiframe includes the first, second, ..., And Nth (N is a first integer of 3 or more) frames. And a first frame of each multi-frame includes a multi-frame sync signal representing a first predetermined sync word and a transmit data signal following the multi-frame sync signal.
Each of the second to Nth frames of each multiframe is
A second predetermined synchronization word, the frame synchronization signal representing a second predetermined synchronization word and a transmission data signal following the frame synchronization signal, wherein the second predetermined synchronization word is the first predetermined synchronization word. The receiver receives the time division multiplexed digital signal from the transmission line as a reception digital signal, and the reception digital signal is such that the transmission line is correctly connected in polarity between the transmission unit and the reception unit. Has a true polarity equal to that of the time division multiplexed digital signal, and the received digital signal has a true polarity when the transmission line is incorrectly connected in polarity between the transmitter and the receiver. In contrast, the polarity determination circuit determines whether the received digital signal has a true polarity or an inverted polarity, and the polarity determination circuit According to the first and second determination result signals, the polarity determination circuit determines that the received digital signal has a true polarity and the received digital signal has an inverted polarity, respectively. The first and second determination result signals indicate that the received digital signal has a true polarity and the received digital signal has an inverted polarity, respectively. In the polarity determination circuit, a first digital signal is received, a first predetermined synchronization word is detected, and a first detection pulse is output each time the first predetermined synchronization word is detected. Sync word detecting means; receiving a received digital signal, detecting a second predetermined sync word, and outputting a second detection pulse each time the second predetermined sync word is detected. 2
And an upper threshold value which is connected to the first and second synchronization word detection means and which is higher than the initial value by a preselected value M (M is a second integer of 2 or more). And a lower threshold value that is lower than the initial value by the preselected value M, and counts down and up in response to the first and second detection pulses, respectively. And a counting means for respectively outputting the determination result signal of 1) when the count is increased to the upper threshold value and when the count is decreased to the lower threshold value.

The counting means raises and lowers the count in response to the first and second detection pulses, respectively, and outputs the first and second determination result signals when the count decreases to a lower threshold value and The counts may be output when the counts increase to the upper threshold.

Further, in the above-described polarity determination circuit according to the present invention, each of the frame synchronization signals of at least two frames of the second to Nth frames of each multiframe is a first predetermined signal represented by the multiframe synchronization signal. It is also applicable if it represents a second predetermined synchronization word determined by inverting the synchronization word.

[Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.

The polarity determination circuit 10 according to the first embodiment of the present invention shown in FIG. 1 is used in the first communication unit 11 of the digital transmission network shown in FIG.

Referring to FIG. 2, it is assumed that first communication unit 11 is currently operating as a receiving unit. The digital transmission network is typically ISDN and includes the second communication unit 12 and the first communication unit 12.
And a transmission line 13 between the second communication units 11 and 12.
It is assumed that the second communication unit 12 is currently operating as a transmission unit, but the second communication unit 12 also includes a similar polarity determination circuit that operates when the second communication unit 12 acts as a reception unit. Contains. The transmission line 12 is typically a two-wire metallic cable. The second communication unit 12 transmits the time division multiplexed digital signal to the transmission line 13.

Referring to FIG. 3, the time division multiplexed digital signal is SIG
And is shown on the top line. The time division multiplexed digital signal includes consecutive multiframes of a common multiframe period. Each multi-frame includes a first frame, a second frame, ..., And an Nth frame (N is a first integer of 3 or more) having a common frame period. The first frame of each multiframe includes a multiframe synchronization signal and a transmission data signal that follows the multiframe synchronization signal. The multi-frame sync signal and the transmission data signal are labeled F1 and DATA, respectively. The multiframe sync signal represents a first predetermined sync word consisting of at least one symbol.

Each of the second to Nth frames of each multiframe is
It includes a frame synchronization signal labeled F and a transmission data signal labeled DATA following the frame synchronization signal F. The frame sync signal represents a second predetermined sync word. Here, it is assumed that the second predetermined synchronization word is determined by inverting the first predetermined synchronization word.

Returning to FIG. 1, the first communication unit 11 receives the time division multiplexed digital signal from the transmission line 13 as a received digital signal. This received digital signal is transmitted through the transmission line 13 of the two-wire metallic cable to the first and second communication units 11 and 12.
(Fig. 2) In polarity, correctly, that is, regularly,
When connected, it has a true polarity equal to that of the time division multiplexed digital signal. When the transmission line 13 is connected between the first and second communication units 11 and 12 (Fig. 2) in the wrong polarity, that is, conversely, when the transmission line 13 is connected to the true polarity, the received digital signal is Has a reversed polarity.

The polarity determination circuit 10 is for determining whether the received digital signal has a true polarity or an inverted polarity. The polarity determination circuit 10 thereby outputs the first and second determination result signals 16 and 17 to the polarity determination circuit 10 that the received digital signal has a true polarity and the received digital signal is inverted. It is output when it is determined that it has polarity. First and second
Judgment result signals 16 and 17 indicate that the received digital signal has a true polarity and the received digital signal has an inverted polarity, respectively.

The polarity determination circuit 10 includes first and second synchronization word detecting means 21 and 22. First synchronization word detecting means 21
Receives the received digital signal and receives the clock signal CLOCK
Detecting a first predetermined sync word in synchronization with
Each time the first predetermined synchronization word is detected, the first detection pulse F1P is output. The second synchronization word detecting means 22 receives the received digital signal and receives the clock signal CL.
The second predetermined synchronization word is detected in synchronism with OCK, and the second detection pulse FP is output every time the second predetermined synchronization word is detected. The first and second detection pulses F1P and FP are the second and third detection pulses of FIG. 3, respectively.
, And the clock signal CLOCK is shown in the bottom line of FIG.

Continuing to refer to FIG. 1, the counting circuit 23 is
And an up / down counter 24 having countdown and countup terminals DOWN and UP connected to the second sync word detection means 21 and the second sync word detection means 22, respectively. Up-down counter 24
Has an initial value of 0 and an enable terminal ENABLE, for example. When the enable terminal ENABLE receives the control signal 25 having the logic "0" level, the up / down counter 24 responds to the count with the clock signal CLO in response to the first and second detection pulses F1P and FP.
In synchronization with CK, down and up respectively, and outputs the count as a count value. Enable terminal E
While NABLE receives the control signal 25 at the logic "1" level, the up / down counter 24 stops such counting operation and holds the count as it is.

The up / down counter 24 further has an output terminal Q and positive and negative polarity terminals QHp and QHn. The up / down counter 24 outputs the absolute value of the count value to the output terminal Q. The up / down counter 24 outputs a logic "1" level signal to the positive and negative polarity terminals QHp and QHn, respectively, when the count value has a positive and negative polarity.

The combination of the coincidence gate 26 and the AND gate 27 is, as will become clear as the description proceeds, up / down counter 2
Determine the upper threshold for 4. The upper threshold value is higher than the initial value by a preselected value M (M is a second integer of 2 or more). The combination of match gate 26 and AND gate 28 determines the lower threshold for up / down counter 24, as will become apparent as the description proceeds. The lower threshold is lower than the initial value by the preselected value M.

The match gate 26 is connected to the output terminal Q, receives the absolute value of the count value and the preselected value M, and outputs a logic "1" level signal when the absolute value becomes equal to the preselected value M. Output. When this absolute value is not equal to the preselected value M, a logic "0" level signal is output.

The AND gate 27 includes the coincidence gate 26 and the positive terminal Q.
Only when the AND gate 27 is connected to Hp and receives the logic "1" level signal from the coincidence gate 26 and the positive polarity terminal QHp, the logic "1" level signal is output as the first determination result signal 1
Output as 6. AND gate 28 is match gate 2
6 and the negative terminal QHn, and AND gate 2
The logic "1" level signal is output as the second determination result signal 17 only when 8 receives the logic "1" level signal from the coincidence gate 26 and the negative polarity terminal QHn.

As described above, the count circuit 23 is connected to the first and second synchronization word detection circuits 21 and 22, has the initial value and the upper and lower threshold values, and has the first and second detection pulses F.
In response to 1P and FP, the count is down and up respectively, and the first and second decision result signals 16 and 17
Are output when the count has increased to the upper threshold and when the count has decreased to the lower threshold.
When the second integer M is equal to 8, the counting circuit 23 outputs the fourth
It operates as shown. In this case, the initial value and the upper and lower thresholds are 0, +8, and -8, respectively.

In FIG. 1, the count-up and count-down UP and DOWN of the up / down counter 24 may be connected to the first and second sync word detection circuits 21 and 22, respectively. In this case, the count circuit 23 increases and decreases the count in response to the first and second detection pulses F1P and FP, respectively, and lowers the first and second determination result signals 16 and 17 by the count. When the count is decreased to the upper threshold and when the count is increased to the upper threshold, the respective outputs are performed.

Continuing to refer to FIG. 1, the count stop circuit 29
Includes an OR gate 30 and a flip-flop 31.
When the OR gate 30 receives one of the first and second determination result signals 16 and 17 from the count circuit 23, the OR gate 30 supplies the one of the first and second determination result signals 16 and 17 to the flip-flop 31 and the flip-flop 31. The control signal 25 of logic "1" level is output to the loop 31. As a result, the counting circuit 23 outputs the one of the first and second determination result signals 16 and 17 continuously and continuously thereafter.

In this way, the count stop circuit 29 is used by the count circuit 23.
Connected to the first and second determination result signals 16 and 17
In response to one of the first determination result signal 16 and the second determination result signal 16 and 1
7 of the first and second decision result signals 16 and 1
Even after receiving the above-mentioned one of 7, the output is continued.

The first communication unit 11 further includes a synchronization confirmation detection circuit 32 connected to the first and second synchronization word detection circuits 21 and 22. The synchronization confirmation detection circuit 32 responds to the first and second detection pulses F1P and FP, and outputs the clock signal CLOC.
In response to K, the synchronization confirmation is detected, and the synchronization confirmation signal SYNC
Is output.

When receiving the first determination result signal 16 from the count circuit 23, the decoder 33 decodes the received digital signal into a decoded signal in synchronization with the clock signal CLOCK. When receiving the second determination result signal 16 from the count circuit 23, the decoder 33 inverts the received digital signal as an inverted signal and decodes the inverted signal in synchronization with the clock signal CLOCK. Decode to.

Referring again to FIG. 3, the polarity determination circuit 1 shown in FIG.
0 is determined by inverting each of the at least two frame sync signals F of the second to Nth frames of each multi-frame by inverting the first predetermined sync word represented by the multi-frame sync signal F1. The second
It is also applicable to the case in which a predetermined synchronization word of 1 is represented.

Referring to FIG. 5, the polarity determination circuit 40 according to the second embodiment of the present invention includes similar parts indicated by the same reference numerals. This polarity determination circuit 40 is also used in the first communication unit 11 that receives different time division multiplexed digital signals from the transmission line 13 as received digital signals.

Returning to FIG. 2, the different time division multiplexed digital signal will be described. For this different time division multiplexed digital signal, the first integer N is 6 or more. In the different time division multiplexed digital signals, each of at least two frame synchronization signals F of the second to Nth frames of each multiframe has a first predetermined synchronization represented by the multiframe synchronization signal F1. FIG. 6B illustrates a second predetermined sync word determined by inverting the word. Second to Nth of each multi-frame
At least one frame synchronization signal F of the second to Nth frames other than the at least two of the first frame of the third frame is different from both of the first and first predetermined synchronization words. Represents a word. Each of the frame synchronization signals F of the at least two remaining ones of the second to Nth frames of each multi-frame has a third
4 represents a fourth predetermined synchronization word determined by inverting the predetermined synchronization word of FIG.

Returning to FIG. 5, the polarity determination circuit 40 is similar to the polarity circuit 10 of FIG.
1 and 22 are included. The polarity determination circuit 40 further includes
It includes third and fourth sync word detection circuits 43 and 44. The third synchronization word detection circuit 43 receives the received digital signal, detects a third predetermined synchronization word,
A third detection pulse is output each time the third predetermined synchronization word is detected. Similarly, the fourth synchronization word detection circuit 44 receives the received digital signal, detects the fourth predetermined synchronization word, and performs the fourth detection every time the fourth predetermined synchronization word is detected. Output pulse.

The first counting circuit 45 is connected to the first and second synchronization word detecting circuits 21 and 22, and has a first initial value, a first upper threshold value, and a first lower threshold value. There is. First
The upper threshold of M is a value M selected in advance from the first initial value.
(M is a second integer greater than or equal to 2). The first lower threshold is lower than the first initial value by the preselected value M. The first count circuit 45 responds to the first and second detection pulses to down and up the first count, respectively, and outputs the first and second output signals to the first count to the first count. When the first count is decreased to the upper threshold value and when the first count is decreased to the first lower threshold value. Each of the first and second output signals has a logic "1" level.

The first count stop circuit 46 includes the first count circuit 4
5 and is responsive to one of the first and second output signals to stop the first counting circuit 45 and instruct the first counting circuit 45 to output the one of the first and second output signals. After receiving the one of the first and second output signals,
Output continuously.

The second counting circuit 47 is connected to the third and fourth synchronization word detecting circuits 43 and 44, and has a second initial value, a second upper threshold value, and a second lower threshold value. There is. Second
Is above the second initial value by the preselected value M. The second lower threshold is lower than the preselected value M than the second initial value. The second count circuit 47 responds to the third and fourth detection pulses to down and up the second count, respectively, and to the third and fourth count pulses.
Is output when the second count is increased to a second upper threshold value and when the second count is decreased to a second lower threshold value. Each of the third and fourth output signals has a logic "1" level.

The second count stop circuit 48 includes the second count circuit 4
7 and is responsive to one of the third and fourth output signals to stop the second counting circuit 47 and instruct the second counting circuit 47 to output one of the third and fourth output signals. One after receiving the one of the third and the fourth output signals,
Output continuously.

Each of the first and second counting circuits 45 and 47 has the same structure as the counting circuit 23 shown in FIG. Each of the first and second count stop circuits 46 and 48 is the same in structure as the count stop circuit 29 shown in FIG.

The first AND gate 49 generates the first determination result signal 16 of logic "1" level while receiving the first and third output signals. Similarly, the second AND gate 50 is
While receiving the second and fourth output signals, the second determination result signal 17 of logic "1" level is generated.

Thus, the first and second AND gates 49 and 50
Is a combination of the first and second counting circuits 45 and 47.
Connected to the first and second determination result signals 16 and 17
While receiving the first and third output signals, and the second
And the fourth output signal, the circuit operates as a determination result signal generating circuit which is generated respectively.

In the illustrated first communication unit 11, the synchronization confirmation detection circuit 32 includes the first to fourth synchronization word detection circuits 21 and 2.
2, 43, and 44. In response to the first to fourth detection pulses of the synchronization confirmation detection circuit 32, the synchronization confirmation is detected and the synchronization confirmation signal SYNC is output.

When receiving the first determination result signal 16 from the count circuit 23, the decoder 33 decodes the received digital signal into a decoded signal in synchronization with the clock signal CLOCK. When receiving the second determination result signal 16 from the count circuit 23, the decoder 33 inverts the received digital signal as an inverted signal and decodes the inverted signal in synchronization with the clock signal CLOCK. Decode to.

Although the present invention has been described above with reference to some preferred embodiments, those skilled in the art can easily implement the present invention in various other ways. For example, the first shown in FIG.
A different counting circuit may be used instead of the counting circuit 45 of FIG. The different counting circuits respectively up and down the counts in response to the first and second detection pulses and output the first and second output signals when the counts decrease to a first lower threshold value. And, when the first count has increased to the first upper threshold value, they are output. In addition, another different counting circuit may be used instead of the second counting circuit 47 shown in FIG. The other different counting circuit is responsive to the third and fourth detection pulses to up and down the count, respectively, and reduce the third and fourth output signals to a first lower threshold value. And when the first count has increased to the first upper threshold value. In FIG. 5, in the polarity determination circuit 40, a pair of synchronization words having different polarities is K (K is an integer of 3 or more) in the time division multiplexed digital signal.
When included in pairs, K pairs of sync word detection circuits and K count circuits may be included.

[Effects of the Invention] As described above, according to the present invention, a polarity detection circuit which is used in a receiver of a digital transmission network and determines whether a received digital signal has a true polarity or an inverted polarity is obtained. be able to. Further, according to the present invention, it is possible to obtain the polarity detection circuit which can determine whether the received digital signal has the true polarity or the inverted polarity by using the frame synchronization signal and the multi-frame synchronization signal. Moreover, the polarity detection circuit of the present invention has a simple structure.

[Brief description of drawings]

1 is a block diagram of a first communication unit having a polarity determination circuit according to a first embodiment of the present invention, FIG. 2 is a block diagram of a digital transmission network including the first communication unit of FIG. 1, and FIG. FIG. 3 is a time chart for explaining the operation of the polarity determination circuit of FIG. 1, FIG. 4 is a diagram for explaining the operation of the counting circuit of the polarity determination circuit of FIG. 1, and FIG. 5 is of the present invention. It is a block diagram of the 1st communication part containing the polarity determination circuit by a 2nd Example. Reference numeral 10 is a polarity determination circuit, 12 is first and second communication units, 13 is a transmission line, 21 and 22 are first and second synchronization word detection circuits, 23 is a count circuit, 24 is an up / down counter, and 25. Is a control signal, 26 is a match date, 2
7 and 28 are AND gates, 29 is a count stop circuit,
30 is an OR gate, 31 is a flip-flop, 32 is a synchronization confirmation detection circuit, 33 is a decoder, 40 is a polarity determination circuit, 43 and 44 are third and fourth synchronization word detection circuits, and 45 and 47 are first and second. Counting circuit, 46
Reference numerals 48 and 48 are first and second count stop circuits, and 49 and 50 are AND gates.

Claims (10)

[Claims] 1. A polarity determination circuit used in a receiver of a digital transmission network, which includes a transmitter, a receiver, and a transmission path between the transmitter and the receiver, wherein the transmitter determines that each multiframe is 1, second, ..., and Nth (N is a first integer of 3 or more)
A time-division multiplexed digital signal including continuous multi-frames including a plurality of frames, and a first frame of each multi-frame includes a multi-frame synchronization signal that represents a first predetermined synchronization word. And a transmission data signal following the multi-frame synchronization signal, wherein each of the second to Nth frames of each multi-frame has a second
Of the predetermined synchronization words and a transmission data signal following the frame synchronization signal, wherein the second predetermined synchronization word is an inversion of the first predetermined synchronization word. The receiver receives the time division multiplexed digital signal from the transmission line as a reception digital signal, and the reception digital signal is such that the transmission line is correctly connected in polarity between the transmission unit and the reception unit. Time has a true polarity equal to that of the time-division multiplexed digital signal, and the received digital signal is relative to the true polarity when the transmission line is incorrectly connected in polarity between the transmitter and the receiver. It has an inverted polarity, the polarity determination circuit determines whether the received digital signal has a true polarity or an inverted polarity, and the polarity determination circuit Thus, the polarity determination circuit determines that the received digital signal has a true polarity and that the received digital signal has an inverted polarity, respectively. The first and second determination result signals indicate that the received digital signal has a true polarity and the received digital signal has an inverted polarity, respectively. In the polarity determining circuit, a first digital signal is received, a first predetermined synchronization word is detected, and a first detection pulse is output each time the first predetermined synchronization word is detected. Second synchronization word detecting means for receiving the received digital signal, detecting a second predetermined synchronization word, and outputting a second detection pulse each time the second predetermined synchronization word is detected. Of the synchronization word detecting means and the first and second synchronization word detecting means, and an upper threshold value which is higher than the initial value by a preselected value M (M is a second integer of 2 or more). And a lower threshold value that is lower than the initial value by the preselected value M, and counts down and up in response to the first and second detection pulses, respectively. A polarity determination circuit, comprising: a counting unit that outputs the determination result signal of 2 when the count is increased to an upper threshold value and when the count is decreased to a lower threshold value. 2. A counting means, which is connected to the counting means, stops the counting means in response to one of the first and second determination result signals, and supplies the counting means with the one of the first and second determination result signals. A count stop means for continuously outputting even after receiving one of the first and second determination result signals,
The polarity determination circuit according to claim 1, further comprising: 3. A polarity determination circuit used in a receiver of a digital transmission network including a transmitter, a receiver, and a transmission path between the transmitter and the receiver, wherein the transmitter determines that each multiframe is 1, second, ..., and Nth (N is a first integer of 3 or more)
A time-division multiplexed digital signal including continuous multi-frames including a plurality of frames, and a first frame of each multi-frame includes a multi-frame synchronization signal that represents a first predetermined synchronization word. And a transmission data signal following the multi-frame synchronization signal, wherein each of the second to Nth frames of each multi-frame has a second
Of the predetermined synchronization words and a transmission data signal following the frame synchronization signal, wherein the second predetermined synchronization word is an inversion of the first predetermined synchronization word. The receiver receives the time division multiplexed digital signal from the transmission line as a reception digital signal, and the reception digital signal is such that the transmission line is correctly connected in polarity between the transmission unit and the reception unit. Time has a true polarity equal to that of the time-division multiplexed digital signal, and the received digital signal is relative to the true polarity when the transmission line is incorrectly connected in polarity between the transmitter and the receiver. It has an inverted polarity, the polarity determination circuit determines whether the received digital signal has a true polarity or an inverted polarity, and the polarity determination circuit Thus, the polarity determination circuit determines that the received digital signal has a true polarity and that the received digital signal has an inverted polarity, respectively. The first and second determination result signals are that the received digital signal has a true polarity and the received digital signal has an inverted polarity, respectively. In the polarity determination circuit shown, it receives a received digital signal, detects a first predetermined synchronization word, and outputs a first detection pulse each time the first predetermined synchronization word is detected. The first synchronization word detecting means and the received digital signal, the second predetermined synchronization word is detected, and the second detection pulse is output each time the second predetermined synchronization word is detected. Connected to the second synchronization word detecting means and the first and second synchronization word detecting means, and having only an initial value and a value M (M is a second integer of 2 or more) preselected from the initial value. A high upper threshold and a lower threshold lower than the initial value by the preselected value M, in response to first and second detection pulses, counting up and down respectively, A polarity determination circuit, comprising: counting means for respectively outputting the second determination result signal when the count is reduced to a lower threshold value and when the count is increased to an upper threshold value. 4. The counting means is connected to the counting means, and in response to one of the first and second determination result signals, the counting means is stopped and the counting means is provided with the one of the first and second determination result signals. 4. The polarity determination circuit according to claim 3, further comprising count stopping means for continuously outputting one after receiving one of the first and second determination result signals. 5. A polarity determination circuit used in a receiver of a digital transmission network including a transmitter, a receiver, and a transmission line between the transmitter and the receiver, wherein the transmitter determines that each multiframe is 1, second, ..., and Nth (N is a first integer of 3 or more)
A time-division multiplexed digital signal including continuous multi-frames including a plurality of frames, and a first frame of each multi-frame includes a multi-frame synchronization signal that represents a first predetermined synchronization word. A transmission data signal following the multi-frame synchronization signal, each of the second to Nth frames of each multi-frame including a frame synchronization signal and a transmission data signal following the frame synchronization signal, Each of the at least two frame synchronization signals of the second to Nth frames of each multi-frame has a second predetermined synchronization word, which is determined by inverting the first predetermined synchronization word. The receiver receives the time-division multiplexed digital signal from the transmission line as a reception digital signal, and the reception digital signal is transmitted by the transmission line. When proper connection in parts and polarity between the receiving section, has a true polarity equal to the polarity of the division-multiplexed digital signal when the reception digital signal,
When the transmission line is incorrectly connected between the transmission unit and the reception unit in polarity, it has an inverted polarity with respect to the true polarity, and the polarity determination circuit determines that the received digital signal is the true polarity or the inverted polarity. The polarity determination circuit determines whether the received digital signal has a true polarity, and the polarity determination circuit determines the polarity of the first and second determination result signals. It is output when it is determined that the received digital signal has an inverted polarity, and the first and second determination result signals each have a received digital signal having a true polarity. And a polarity determining circuit which indicates that the received digital signal has an inverted polarity, receives the received digital signal, detects a first predetermined synchronization word, and First synchronization word detecting means for outputting a first detection pulse each time a predetermined synchronization word is detected, and a received digital signal to detect a second predetermined synchronization word, and a second synchronization word is detected. Second synchronization word detecting means for outputting a second detection pulse each time a predetermined synchronization word is detected, and first and second synchronization word detecting means are connected, and an initial value and an initial value Also has an upper threshold that is higher by a preselected value M (M is a second integer greater than or equal to 2) and a lower threshold that is lower than the initial value by the preselected value M. In response to the detection pulse of, the count is down and up respectively, the first and second determination result signals, when the count increases to an upper threshold and when the count decreases to a lower threshold, Counting means to output respectively , Polarity determining circuit, characterized in that it comprises. 6. The counting means is connected to the counting means, and in response to one of the first and second determination result signals, the counting means is stopped and the counting means is provided with the one of the first and second determination result signals. A count stop means for continuously outputting even after receiving one of the first and second determination result signals,
The polarity determination circuit according to claim 5, further comprising: 7. A polarity determination circuit used in a receiver of a digital transmission network including a transmitter, a receiver, and a transmission path between the transmitter and the receiver, wherein the transmitter has a multi-frame 1, second, ..., and Nth (N is a first integer of 3 or more)
A time-division multiplexed digital signal including continuous multi-frames including a plurality of frames, and a first frame of each multi-frame includes a multi-frame synchronization signal that represents a first predetermined synchronization word. A transmission data signal following the multi-frame synchronization signal, each of the second to Nth frames of each multi-frame including a frame synchronization signal and a transmission data signal following the frame synchronization signal, Each of the at least two frame synchronization signals of the second to Nth frames of each multi-frame has a second predetermined synchronization word, which is determined by inverting the first predetermined synchronization word. The receiver receives the time-division multiplexed digital signal from the transmission line as a reception digital signal, and the reception digital signal is transmitted by the transmission line. When proper connection in parts and polarity between the receiving section, has a true polarity equal to the polarity of the division-multiplexed digital signal when the reception digital signal,
When the transmission line is incorrectly connected between the transmission unit and the reception unit in polarity, it has an inverted polarity with respect to the true polarity, and the polarity determination circuit determines that the received digital signal is the true polarity or the inverted polarity. The polarity determination circuit determines whether the received digital signal has a true polarity, and the polarity determination circuit determines the first and second determination result signals, respectively. It is output when it is determined that the received digital signal has an inverted polarity, and the first and second determination result signals each have a received digital signal having a true polarity. And a polarity determining circuit that indicates that the received digital signal has an inverted polarity, receives the received digital signal, detects a first predetermined synchronization word, and A first synchronization word detecting means for outputting a first detection pulse each time a predetermined synchronization word is detected, and a received digital signal to detect a second predetermined synchronization word, and a second synchronization word is detected. It is connected to a second synchronization word detecting means for outputting a second detection pulse each time a predetermined synchronization word is detected, and first and second synchronization word detecting means, and an initial value and an initial value First and second detections having an upper threshold that is higher by a preselected value M (M is a second integer greater than or equal to 2) and a lower threshold that is lower by the preselected value M than the initial value. In response to the pulse, the count is respectively increased and decreased, and the first and second determination result signals are output when the count is decreased to the lower threshold and when the count is increased to the upper threshold, respectively. Counting means to , Polarity determining circuit, characterized in that it comprises. 8. The counting means is connected to the counting means, and in response to one of the first and second determination result signals, the counting means is stopped, and the counting means is provided with the one of the first and second determination result signals. A count stop means for continuously outputting even after receiving one of the first and second determination result signals,
The polarity determination circuit according to claim 7, further comprising: 9. A polarity determination circuit used in a receiver of a digital transmission network including a transmitter, a receiver, and a transmission path between the transmitter and the receiver, wherein the transmitter determines that each multiframe is 1, second, ..., and Nth (N is a first integer of 3 or more)
A time-division multiplexed digital signal including continuous multi-frames including a plurality of frames, and a first frame of each multi-frame includes a multi-frame synchronization signal that represents a first predetermined synchronization word. A transmission data signal following the multi-frame synchronization signal, each of the second to Nth frames of each multi-frame including a frame synchronization signal and a transmission data signal following the frame synchronization signal, Each of the at least two frame synchronization signals of the second to Nth frames of each multi-frame has a second predetermined synchronization word, which is determined by inverting the first predetermined synchronization word. At least one of the second to Nth frames except the at least two of the second to Nth frames of each multiframe. Frame synchronization signal represents a third predetermined synchronization word that is different from both the first and second predetermined synchronization words, and includes at least two of the second to Nth frames of each multiframe. Each of the two remaining frame sync signals represents a fourth predetermined sync word, determined by inverting a third predetermined sync word,
The receiver receives the time division multiplexed digital signal from the transmission line as a reception digital signal, and the reception digital signal is the time division multiplexed digital signal when the transmission line is correctly connected in polarity between the transmitter and the receiver. It has a true polarity equal to the polarity, and the received digital signal has a polarity that is the inverse of the true polarity when the transmission line is incorrectly connected in polarity between the transmitter and the receiver, The polarity determination circuit determines whether the received digital signal has a true polarity or an inverted polarity, and the polarity determination circuit thereby determines the polarity determination of the first and second determination result signals, respectively. When the circuit determines that the received digital signal has a true polarity and the received digital signal has an inverted polarity, the circuit outputs the signal. The second determination result signal indicates that the received digital signal has a true polarity and the received digital signal has an inverted polarity. A first synchronization word detecting means for receiving a first predetermined synchronization word and outputting a first detection pulse each time the first predetermined synchronization word is detected; A second sync word detecting means for receiving a second predetermined sync word and outputting a second detection pulse each time the second predetermined sync word is detected; Third synchronization word detecting means for receiving a third predetermined synchronization word, outputting a third detection pulse each time the third predetermined synchronization word is detected, and a receiving digital signal. Receiving a signal, detecting a fourth predetermined synchronization word, and outputting a fourth detection pulse each time the fourth predetermined synchronization word is detected; And a second synchronization word detecting means, and a first initial value and a value M selected in advance from the first initial value.
A first upper threshold that is higher by (M is a second integer greater than or equal to 2) and a first lower threshold that is lower by the preselected value M than the first initial value; Responsive to the second detection pulse, the first count is respectively down and up and the first and second output signals are increased when the first count is increased to a first upper threshold and when the first count is increased. Is connected to the first counting means and the first counting means for respectively outputting when the count of is reduced to the first lower threshold value.
In response to one of the first and second output signals, the first counting means is stopped and the first and second output signals are supplied to the first counting means. Output continuously even after receiving one of the output signals of
Count stopping means and third and fourth synchronization word detecting means, and a second initial value, and a second upper threshold value higher than the second initial value by the preselected value M. , A second lower threshold lower than the second initial value by the preselected value M,
In response to the third and fourth detection pulses, down and up the second count respectively, and increasing the third and fourth output signals when the second count has increased to a second upper threshold and When the second count is reduced to the second lower threshold value, the second count means outputs the second count means, and the second count means is connected to the third count means and the fourth count means.
In response to one of the output signals from the second counting means, the second counting means receives the one of the third and fourth output signals from the third and fourth output signals. A second output that is continuously output even after receiving one of the output signals of
Connected to the count stopping means and the first and second counting means, while receiving the first and second determination result signals and the second and third output signals, and And a determination result signal generating means for generating each while receiving the fourth output signal. 10. A polarity determination circuit used in a receiver of a digital transmission network, which includes a transmitter, a receiver, and a transmission line between the transmitter and the receiver, wherein the transmitter has a multi-frame The first, second, ..., And N-th (N is a first integer equal to or greater than 3) frames of time-division multiplexed digital signals including consecutive multi-frames are transmitted to the transmission path, One frame includes a multi-frame sync signal representing a first predetermined sync word and a transmit data signal following the multi-frame sync signal,
Each of the second to Nth frames of each multiframe is
Each of the at least two frame synchronization signals of the second to Nth frames of each multiframe includes a frame synchronization signal and a transmission data signal subsequent to the frame synchronization signal, and a first predetermined synchronization word. Of the second to Nth frames, excluding said at least two of the second to Nth frames of each multiframe, which are determined by inverting The at least one frame sync signal represents a third predetermined sync word that is different from both the first and second predetermined sync words, and includes a second to Nth frame of each multiframe. Each of the frame sync signals of the at least two remaining ones is determined by inverting a third predetermined sync word and a fourth pre-determined sync word. The receiver receives the time division multiplexed digital signal from the transmission line as a reception digital signal, and the reception digital signal is such that the transmission line is correctly connected in polarity between the transmission unit and the reception unit. Has a true polarity equal to that of the time division multiplexed digital signal, and the received digital signal has a true polarity when the transmission line is incorrectly connected in polarity between the transmitter and the receiver. In contrast, the polarity determination circuit determines whether the received digital signal has a true polarity or an inverted polarity, and the polarity determination circuit thereby determines whether the received digital signal has the first polarity or the second polarity. Judgment result signal
The polarity determining circuit outputs the received digital signal when it determines that the received digital signal has a true polarity and the received digital signal has an inverted polarity, respectively. The second determination result signals are received by the polarity determination circuit indicating that the received digital signal has a true polarity and the received digital signal has an inverted polarity, respectively. A first synchronization word detecting means for detecting a first predetermined synchronization word and outputting a first detection pulse each time the first predetermined synchronization word is detected; Second synchronization word detecting means for detecting a second predetermined synchronization word and outputting a second detection pulse each time the second predetermined synchronization word is detected, Third sync word detecting means for receiving a digital signal, detecting a third predetermined sync word, and outputting a third detection pulse each time the third predetermined sync word is detected; Fourth sync word detecting means for receiving a digital signal, detecting a fourth predetermined sync word, and outputting a fourth detection pulse each time the fourth predetermined sync word is detected; It is connected to the first and second synchronization word detecting means, and has a first initial value and a value M (M
Is a second upper integer greater than or equal to 2) and a first upper threshold that is lower than the first initial value by the preselected value M.
A lower threshold value, and up and down the first count in response to the first and second detection pulses, respectively.
The first count is the first and the second output signal is the first count.
A first count means for outputting respectively when the first count means decreases to a lower threshold value and the first count increases to a first upper threshold value, and the first and the first count means are connected. Two
In response to one of the first and second output signals, the first counting means is stopped and the first and second output signals are supplied to the first counting means. Output continuously even after receiving one of the output signals of
Count stopping means and third and fourth synchronization word detecting means, and a second initial value, and the preselected value M rather than the second initial value.
Has a second upper threshold and a second lower threshold that is less than the second initial value by the preselected value M, and is responsive to the third and fourth detection pulses. 2 counts up and down, respectively, and third and fourth output signals increase when the second count decreases to a second lower threshold and when the second count increases to a second upper threshold. And a second counting means for outputting each of the third counting means and the third counting means, which are connected to the second counting means.
In response to one of the output signals, the second counting means is stopped and the one of the third and fourth output signals is supplied to the second counting means. A second output that is continuously output even after receiving one of the output signals of
Counting stop means of the first and second counting means,
And the second determination result signal to the first and third
And a determination result signal generating means for respectively generating the second and fourth output signals.