JPH0675931A - Computer system - Google Patents

Abstract

PURPOSE: To provide a method for switching a network connection by allowing a high speed input and output for a multi-PME computer system to break in the network connection. CONSTITUTION: This system connection (gripper) is used in a system in which data are inputted and outputted in the network of mutually connected nodes, and the nodes are mutually connected in the form of mesh, ring, or returning tourus. As a result, no edge to the network is present, and a gripper mechanism logically breaks a ring along a dimension at a right angle to the ring so that the edge to the network can be established. Thus, the network can be dynamically toggled between the network without any edge and the network with the edge.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to densely parallel processors and architectures, and more particularly to moving data in and out of an array of processing elements.

[0002]

2. Description of the Related Art First, terms used in this specification will be described.

ALU ALU is the arithmetic logic circuit part of the processor.

Array An array refers to an array of elements in one or more dimensions. An array can include an ordered set of data items (array elements), but in languages such as FORTRAN, those data items are identified by a single name. In other languages, the name of an ordered set of data items refers to an ordered set of data elements that all have the same attributes. In program arrays, dimensions are generally specified by number or dimension attributes. In some languages, array declarators specify the size of each dimension of the array, and in some languages the array is an array of elements in a table. In a hardware sense, an array is a collection of structures (functional elements) that are the same in a massively parallel architecture as a whole. An array element in data parallel computer processing is an element to which an operation can be assigned and which can execute a required operation independently and in parallel in a parallel state. In general, an array can be thought of as a grid of processing elements. By assigning partition data to each section of the array, the partition data can be moved in a regular grid pattern. However, it is possible to index the data or assign the data to any location in the array.

Array Director The array director is a unit programmed as an array control program. The array director serves as a master control program for a group of functional elements arrayed as an array.

Array Processor Array processors mainly include multiple instruction multiple data scheme (MIMD) and single instruction multiple data scheme (SIM).
There are two types, D). In a MIMD array processor, each processing element in the array uses its own data to execute its own unique instruction stream. SIM
In a D array processor, each processing element in the array is
Limited to the same instruction via a common instruction stream. However, the data associated with each processing element is unique. There are other features of the preferred array processor of this invention. In this specification, this is referred to as APAP, and AP
The abbreviation AP is used.

Asynchronous Asynchronous means that there is no regular time relationship. That is, the relationship between the executions of each function is unpredictable, and there is no regular or predictable time relationship between the executions of each function. In a control situation, the control program addresses the location to which control is passed when data is waiting for the idle element being addressed. This keeps the operations in order, even though they do not match the time of any event.

BOPS / GOPS BOPS or GOPS is an abbreviation for the same meaning of 1 billion operations per second. See GOPS.

Circuit Switching / Store-and-Switch These terms refer to two mechanisms for moving data packets through a network of nodes. Store-and-forward is a mechanism by which a data packet is received at each intermediate node, stored in its memory, and then forwarded towards its destination. Circuit switching directs an intermediate node to logically connect its input port to an output port so that data packets do not go into the intermediate node's memory but go directly through the node to its destination. It is a mechanism that enables it.

Cluster A cluster is a control unit (cluster control device),
Hardware connected to it (terminals, functional units,
Or a virtual component) and a station (or functional unit). As used herein, a cluster is a processor memory element (PM), also referred to as a node array.
E) of the array. Normally, a cluster has 512 PM
It has an E element.

The entire PME node array of the present invention consists of a set of clusters each supported by one Cluster Controller (CC).

Cluster control device A cluster control device is a device that controls the input / output operations of a plurality of devices or functional units connected to it.
The cluster controller is typically under the control of a program stored in, and executing on, the unit, as in the IBM 3601 financial institution communication controller.
It is fully controllable in hardware, as in the 3272 controller.

Cluster Synchronizer A cluster synchronizer manages the operation of all or a portion of a cluster to maintain the synchronized operation of the elements so that each functional unit can maintain a specific time relationship with the execution of the program. It is a functional unit.

Control Device A control device is a device that directs the transmission of data and commands over the links of an interconnection network. The operation of the control device is controlled by a program executed by a processor to which the control device is connected or a program executed in the control device.

CMOS CMOS is an abbreviation for complementary metal oxide semiconductor technology. It is widely used in the manufacture of dynamic random access memory (DRAM). NMOS
Is another technique used in the manufacture of dynamic random access memories. In the present invention, the complementary metal oxide semiconductor is used.
The technology used to manufacture the processor (APAP) does not limit the scope of semiconductor technology used.

Dotting refers to joining three or more lead wires by physical connection. Most backpanel buses use this connection method. This term
Related to the OR DOTS of the past, it is used here to identify multiple data sources that can be coupled onto the bus by a very simple protocol.

The concept of I / O zippers in the present invention can be used to implement the concept that an input port entering a node can be driven by an output port exiting a node or by data coming from the system bus.
Conversely, the data output from one node can be used as an input to another node and system bus. It should be noted that the data output to the system bus and another node are not executed at the same time but in another cycle.

Dotting is used in the discussion of H-DOT, by which the two-port PE or PME or picket can be used for arrays of various configurations. Several topologies have been discussed, including 2D and 3D meshes, base 2N cubes, sparse base 4N cubes, sparse base 8N cubes.

DRAM DRAM is an abbreviation for dynamic random access memory, which is a common storage device used by a computer as a main storage device. However, the term DRAM is also applicable to use as a cache or memory that is not main memory.

Floating-Point Floating-point numbers are represented in two parts: a fixed-point part, or fractional part, and an exponent part to a radix or base on the promise. The exponent indicates the actual position of the decimal point. In typical floating point notation, the real number 0.0001234 is represented as 0.1234-3. Here, 0.1234 is a decimal part and -3 is an exponent. In this example, the floating point radix or base is 10, representing an implicit fixed integer base greater than one. The exponent represented explicitly in the floating-point representation, or represented in the exponent in the floating-point representation, is raised to the power of this base and then multiplied by the fractional part to obtain the represented real number. Numeric literals can be represented either in floating point notation or in real numbers.

FLOPS This term refers to the number of floating point instructions per second. Floating point operations include ADD (addition), SUB (subtraction),
It involves MPY (multiplication), DIV (division) and often many other operations. The parameter of floating point instructions per second is often calculated using add or multiply instructions and can generally be considered a 50/50 mix. The calculation includes generation of an exponent part and a decimal part, and normalization of a necessary decimal part. The present invention can handle 32-bit or 48-bit floating point formats (though it may be longer, but such formats were not counted in the mix). Multiple instructions are required when performing floating point operations with fixed point instructions (regular or RISC). Some people use a 10: 1 ratio when calculating performance, and a ratio of 6: 1.
Some studies have shown that 25 is more appropriate. Different architectures have different ratios.

Functional Unit A functional unit is a hardware, software, or both entity that can achieve a certain purpose.

G bytes G bytes refer to 1 billion bytes. 1 Gbyte / sec
That's 1 billion bytes per second.

GIGAFLOPS 10 ⁹ floating point instructions per second

GOPS and PETAOPS GOPS or BOPS have the same meaning of 1 billion operations per second. PETAOPS means 1 trillion operations per second, which is the potential of current machines. In the APAP machine of the present invention, these terms are BIP / G which means 1 billion instructions per second.
It is almost the same as IP. While some machines can perform multiple operations (ie, both add and multiply) with a single instruction, the present invention does not. Also, it may take many instructions to perform one operation. For example, the present invention uses multiple instructions to perform 64-bit operations. However, when counting the calculation, the logarithmic calculation was not performed. GO to describe performance
Preference was given to using PS, but it was not used consistently. MIP / MOP, BIP / BOP as units above it, and MegaFLOPS / Giga
FLOPS / TeraFLOPS / PetaFLOPS
Is used.

ISA ISA means a Set Architecture (architecture setting) instruction.

Link A link is a physical or logical element. A physical link is a physical connection for connecting elements or units, while a link in computer programming is an instruction or address that exchanges control and parameters between different parts of a program. In multiple systems, a link is a connection between two systems specified by a program code that identifies the link identified by its real or virtual address. Thus, a link typically includes the physical medium, any protocol, and associated equipment and programming. That is, the link is both logical and physical.

MFLOPS MFLOPS means 10 ⁶ floating point instructions per second.

MIMD MIMD is a multiple data arrangement where each processor in the array has its own instruction stream and thus multiple instruction streams, one for each processing element.
Used to refer to the processor array architecture that executes a stream.

Module A module is a discrete and identifiable program unit, or a functional unit of hardware designed for use with other components. An aggregate of PEs included in a single electronic chip is also called a module.

Node In general, a node is a junction of links. In a general-purpose array of PEs, one PE can be a node.
A node can also include a collection of PEs called modules. In the present invention, a node is formed from an array of PMEs, and this set of PMEs is called a node.
The node is preferably 8 PMEs.

Node array A collection of modules composed of PMEs is sometimes called a node array. It is an array of nodes made up of modules. Node arrays are typically
Although there are more than a few PMEs, the term encompasses a plurality.

PDE PDE is a partial differential equation.

PDE relaxation solution process PDE relaxation solution process is PDE (partial differential equation)
Is a method of solving. Solving PDEs uses most of the computational power of supercomputers in the known field, and thus it exemplifies the mitigation process. PD
There are many ways to solve the E equation, and several numerical solutions include the relaxation process. For example, when solving a PDE with the finite element method, most of the time is spent computing the relaxation. Consider the example of the field of heat transfer. Given the hot gas inside the chimney and the cold wind outside, what is the temperature gradient inside the chimney bricks? Considering bricks as small segments and writing an equation that describes how heat flows between the segments as a function of temperature difference, the heat transfer PDE is transformed into a finite element problem. Now, assuming that all elements, except the inner and outer elements, are at room temperature and the boundary segments are the temperature of the hot gas and cold wind, a problem is created to initiate the relaxation.
The computer program then models the time by updating the temperature variable within each segment based on the amount of heat flowing into or out of the segment. In order to relax a set of temperature variables in the chimney to represent the actual temperature distribution that occurs in the physical chimney, it must take many cycles to process all the segments in the model. If the goal is to model gas cooling in a chimney, the elements must be extended to the gas equation, then the inner boundary conditions are linked with another finite element model, and this process continues. Note that the heat flow depends on the temperature difference between adjacent segments. Therefore, the temperature variable is distributed using the communication path between PEs. It is this near-neighbor communication pattern or characteristic that makes the PDE relationship well applicable to parallel computing.

Picket This is an element within the array of elements that make up the array processor. This element is a data flow (ALU
REGS), memory, controls, and the parts of the communication matrix associated with this element. This unit refers to 1 / n of an array processor that consists of parallel processor elements and memory elements and their control and part of the array intercommunication mechanism. Pickets are a form of processor memory element (PME). The PME chip design processor logic of the present invention may implement the picket logic described in the related application or have the logic for a processor array formed as a node.
The term picket is similar to the commonly used array term PE for processing elements, and is preferably a combination of processing elements and local memory for processing bit parallel bytes of information in a clock cycle. Consists of,
It is an element of the processing array. The preferred embodiment consists of a byte wide data flow processor, 32 bytes or more of memory, a primitive control mechanism, and a mechanism for communicating with other pickets.

The term "picket" comes from Tom Sawyer and his white fence. However, it will also be understood that, functionally, it is similar to the army's picket line.

Picket Chip A picket chip contains multiple pickets on a single silicon chip.

Picket Processor System (or Subsystem) A picket processor consists of an array of pickets, a communications network, an input / output system, a microprocessor, a canned routine processor, and a microcontroller executing the array. It is a total system including a SIMD control device.

Picket Architecture The picket architecture is a preferred embodiment of the SIMD architecture and has the capability to address a number of diverse problems including: -Set associative processing-Parallel numerical central processing-Image-like physical array processing

Picket Array A picket array is an ordered array of pickets arranged in a geometric order.

PME or Processor Memory Element PME stands for Processor Memory Element. The term PME is used herein to refer to a single processor, memory, and I / O capable system element or unit forming one of the parallel array processors of the present invention. PME is a term that encompasses pickets. A PME is a processor, memory associated with it,
1 / n of the processor array that consists of the control interface and part of the array communication network facility. This element can comprise a PME with regular array connectivity, such as in a picket processor, or a PME as part of a sub-array, such as in the multiple PME node described above.

Routing The routing is the allocation of a physical route for delivering a message to a destination. A source and a destination are required for route allocation. These elements or addresses are
Has a temporary relationship or affinity. Message routing is often based on keys obtained by looking up a table of assignments. Within a network, a destination is any station or network addressable unit that is addressed as the destination of information to be transmitted by a routing address that identifies a link. The destination field identifies the destination with the message header destination code.

A processor array architecture in which all processors in a SIMD array are instructed to execute multiple data streams arranged one per processing element from a single instruction stream.

SIMDMIMD or SIMD / MI
MD SIMDMIMD or SIMD / MIMD is a term that refers to a machine that has the dual function of being able to switch from MIMD to SIMD for a period of time to process complex instructions, and thus has two modes. Placing a Connection Machine Model CM-2 from Thinking Machines, Inc as the front end or back end of a MIMD machine allows the programmer to configure multiple modes, also known as dual mode. I was able to run different parts of the problem that were running. These machines have been around since ILLIAC and use a bus to interconnect a master CPU with other processors. The master control processor has the ability to interrupt the processing of other CPUs. Other CPUs can execute independent program code. During the interrupt, something needs to be done for the checkpoint function (close and save the current state of the controlled processor).

SIMIMD SIMIMD is a processor array architecture in which all processors in the array are commanded by a single instruction stream to execute multiple data streams arranged one per processing element. Is.
Within this configuration, the data dependent operations within each picket that mimic instruction execution are controlled by the SIMD instruction stream.

This uses the SIMD instruction stream to order multiple instruction streams (one per picket) and multiple data streams (one per picket).
A single instruction stream machine capable of executing SIMIMD can be performed by the PME system.

SISD SISD is an abbreviation for single instruction single data.

Swapping Swapping refers to the interchange of the data content of one storage area with the data content of another storage area.

Synchronous operation Synchronous operation in MIMD machines is a mode of operation in which each action is associated with some event (usually a clock). This event can be a specified event that occurs regularly in the program sequence.
Actions are dispatched to a number of processing elements, each of which performs its function independently. Control is not returned to the controller until the operation is complete.

If the request is for an array of functional units, a request is made by the controller to an element in the array, which element must complete operation before control is returned to the controller.

TERAFLOPS TERAFLOPS means 10 ¹² floating point instructions per second.

VLSI VLSI is an abbreviation for very large scale integration (applied to integrated circuits).

Zipper A zipper is a newly provided function for establishing a link from a device outside the normal interconnection of an array configuration.

Circuit-switched scheme A PME in the array in which an intermediate PME logically connects an input port to an output port so that the message passes through the intermediate PME towards its final destination without additional manipulation by the intermediate PME. Method of data transfer between.

Input transfer complete interrupt Request for program context switch made when an I / O message word with a transfer complete tag is received.

Break-in A mechanism for I / O ports to cause processor-transparent context switching and self-manage data transfers using processor data streams and control paths.

Run-time software Software that runs on the processing elements, including operating systems, executive programs, application programs, service programs, etc.

Memory refresh A function required by dynamic RAM technology in which memory usage is interrupted during rewriting of the current information.

Zipper Dynamic break of a group of network rings. When "zipped", data can travel around the ring without entering or leaving the network.
When "unzipped", the ring is broken to form an edge to the network through which data traveling in and out of the network.

[0060]

As the background of the present invention,
Fast I / O in meshes, tori and other dimensional networks is enhanced by faster I / O. Conventional systems do not have the functionality of the invention with respect to networks. We think it important to provide the ability to break the ring to form an edge into the network through which data around the ring can enter and leave the network.

[0061]

High speed input / output for multiple PME computer systems provides a method of breaking in and switching network connections. This system connection is called a zipper.

The I / O zipper concept of the present invention can be used to implement the concept that a port entering a node can be driven with a port leaving a node or data coming from the system bus. Conversely, the data emitted from one node is made available for I / O to another node and the system bus. The data output to the system bus and the data output to another node do not occur simultaneously but in different cycles. Zippers are used in systems that move data in and out of a network of interconnected nodes and interconnect the nodes as a mesh, ring or folded torus, so there is no edge to the network and the zipper mechanism makes the ring orthogonal to the ring. It breaks logically along the dimension to establish an edge to the network. Coupling logically toggles networks between networks without edges and networks with edges. When the edge is active,
Data enters and leaves the network through the edges, and this coupling allows for the distribution of data that enters the network or the collection of data that exits the network so that the data rate through the edge is persistent data for systems outside the network. It will match the rate and peak data rate.

Zippers allow a dynamic break of a group of network rings. When "zipped", data can travel around the ring without entering or leaving the network. When "unzipped", the ring is broken to form an edge to the network through which data traveling in and out of the network.

The above and other improvements are described in the detailed description below. For a better understanding of the present invention and its advantages and features, refer to the description and to the drawings below.

The following detailed description illustrates, by way of example, preferred embodiments of the invention and its advantages and features, with reference to the drawings.

[0066]

DETAILED DESCRIPTION OF THE INVENTION Previous U.S. Patent Application No. 6111594 envisions incorporating memory and control logic within a single chip, replicating the combination within the chip, and building a processor system from a single chip replica. It has been described. By this means, by developing and manufacturing only one type of single chip, a system can be obtained that provides massively parallel processing capability while increasing performance capability by reducing chip boundary crossings and line lengths.

The original patent uses a one-dimensional input / output structure to
It describes adding multiple SIMD processing memory elements (PMEs) to the structure in a chip. The present invention and related applications cited extend the concept to more than one dimension and include a complete I / O system with data transfer and program interrupts. The following description is 8 per chip
For a four-dimensional input / output structure with a single SIMD / MIMD PME, see US Pat.
It can also be extended to higher dimensions or to more PMEs per dimension, as described in No. 4.

The present invention and its related applications extend these concepts from interprocessor communication to external input / output mechanisms.
It also describes the interfaces and elements needed to control the processing array. In summary, there are the following three types of input / output. (A) Between processors, (b) Between processor and the outside, (c) Broadcast communication / control. In a massively parallel processing system, all these types of I / O bandwidth must be balanced with the computational power of the processor. Within the array, these requirements are met by replicating a 16-bit instruction set architecture computer (hereinafter PME) with the addition of very fast interrupt state swap capability. The characteristics of PMEs are unique when compared to the processing elements of other massively parallel machines. It can completely distribute processing, routing, storage and I / O. This feature does not exist in any other design.

A block diagram of the "Advanced Parallel Array Processor (APAP)" disclosed in detail in the related application is shown in FIG. APAP is an adjunct to the host processor 1. Data and commands are issued by programs running on the host processor. These data and commands are received and converted by the application director (API) 3 of the array director. Next, data and commands are passed from the API to the cluster 6 via the cluster synchronizer 4 and the cluster controller 5. These clusters provide APAP memory and perform parallel processing. The function provided by the cluster synchronizer 4 and the cluster controller 5 is to route data and commands to the appropriate clusters and to balance the load among the clusters. For details on the control device, refer to "Advanced Parallel Pro
US Patent Application entitled "cessor Array Director".

A cluster consists of several PMEs interconnected as a modified hypercube. Within the hypercube, each cell can address any cell whose address differs by one bit position as a neighbor cell. Every cell in the ring has an address ±
Two cells that differ by one can be addressed as neighboring cells. The modified hypercube used for APAP combines both approaches to build a hypercube from a ring. The intersection of the rings is defined as a node. In the preferred embodiment of the invention, there are two nodes.
It includes n PMEs 20 and a broadcast / control interface (BCI) unit 21. The PME is organized as a 2xn array within the node. Where n is the number of dimensions or rings that characterize the array, subject to the limitations of the physical chip package. In the preferred embodiment, n = 4. As chip technology improves, the larger "n", the higher the possible dimensions in the array.

The construction of arrays from PMEs is shown in FIGS. Eight PMEs are interconnected to form node 151. A group of eight nodes are interconnected as an X-dimensional ring (16PME), and a group of eight nodes that overturn it are interconnected as a Y-dimensional ring 152. This results in a single two-dimensional cluster containing an 8x8 array of nodes (512 PMEs). The clusters are combined in a maximum of 8x8 array to form a four-dimensional array element 153. Each group of 8 nodes across this array element are combined in the W and Z dimensions. Single node interconnection paths in all four dimensions are shown at 154.
Note that the array need not be normal or orthogonal. A particular application or configuration can redefine the number of nodes in any or all dimensions.

Each PME can only exist within one node ring 26 (FIG. 2). Ring W, X, Y, Z
Call. The PMEs 20 in one chip are paired (ie + W, -W) and one PME moves data clockwise along the node ring to the outside and the other PME
E travels counterclockwise along the node rings 23, 26 externally, thus one PME is dedicated to each node's external port. Name the two PMEs in each ring named after their external I / O ports (+ W, -W,
+ X, -X, + Y, -Y, + Z, -Z). There are also two rings 22 in the node, 4 + n and 4-n PMs
Interconnect E. These inner rings provide a path for messages to travel between outer rings. AP
Since the APs can be considered as four-dimensional orthogonal arrays 151-154, the inner ring allows the message to move through the array in all dimensions. Thus, by addressing a PME in its own node ring or a neighboring PME in that node, an addressing structure is obtained in which any PME can step the message towards its purpose.

In FIG. 5, each PME has four input ports and four output ports (left 85, 92, right 86, 95, vertical 9).
3, 94, external 80, 81). Three of the input ports and three of the output ports are
It is a full-duplex, 2-point connection to the ME. The fourth port is a full duplex point-to-point connection to the off-chip PME. In the preferred embodiment, due to pin and power constraints on the physical package, the actual I / O interfaces are 4-bit wide paths 97, 98, 99, which are the inter-PME data words 96 shown in FIG. Used to multiplex 100 4 nibbles.

In the preferred embodiment, this PME I / O design provides three I / O modes of operation.

Normal mode Used for data transfer between two adjacent PMEs. Data transfer is initiated by PME software. Data destined for a PME farther than an adjacent PME is received by the adjacent PME and forwarded as if it originated from that adjacent PME. Normal mode is "PME Store and Forward / Circuit S
It is disclosed in detail in a related US patent application entitled "witched Modes".

Circuit switching mode Data and control is PM
Allow passage through E. This mode enables high speed communication between PMEs that are not directly adjacent to each other.
The circuit switched mode is disclosed in detail in the above related patent application.

Zipper mode Used by the array controller to load data into or read data from the nodes in the cluster. Zipper mode is
The normal mode and circuit switched mode features are used to transfer data at high speed to and from an array of PMEs on a cluster card.

Each ring in array W, X, Y, Z is continuous and has no edges to the array. Conceptually, a zipper is a logical break in the ring at the interface between two nodes to form a temporary edge.
When the zipper is inactive, the array has no edges. When the zipper is activated, all interfaces between the two node trains are broken and the resulting "edges" are used to transfer data between the array and the array controller. For example, referring to FIG. 6, if the zipper connection is placed on the -X interface along the X = 0 node row, then X = 8 (PME × 15) 250 node rows and X = 0 (PME × 0). The interface between the 253 node rows is no longer between the two points, but a third (host) interface 251 is added. Normally, the data passes between PME × 0 253 and PME × 15 250 as if there was no host interface there. However, under control of the PME run-time software, data is passed between the arrays 250, 253 and the host interface 251 via the temporary edges of the array when the zipper is activated. A zipper along a single cluster row breaks the ring with 8 nodes. Based on today's technology, the preferred embodiment can pass about 57 megabytes per second to and from a single cluster via a single zipper. It is expected that this data rate will increase significantly if future technology such as optical connection develops.

FIG. 7 illustrates how this concept can be extended to place zippers on the two "edges" 255, 256 of a cluster. This approach increases the I / O bandwidth to approximately 114 megabytes per second when different data is passed within each zipper, and approximately 57 megabytes per second of orthogonal data movement when the same data is passed within each zipper. To support. Orthogonal data movement supports fast transposition and matrix multiplication operations within the array. In theory there could be a zipper on each node-to-node interface, but in practice each PME with a zipper interface would avoid having its memory fill up and not be able to accept any more data. First, it must be possible to transfer array I / O data to another PME. The number of zippers is for each PME
Technology to determine how much memory can be used by
Limited by the speed at which zipper data can be moved between the PME on the zipper and another PME in the array.

FIG. 1 shows an array of n clusters. In the preferred embodiment, each cluster supports two orthogonal zippers. The maximum array I / O rate for this array is 2n x 57 megabytes per second. The maximum orthogonal array I / O rate for this array is n × 157 megabytes per second.

In the preferred embodiment of the zipper, there are two modes of operation: zipper input and zipper output. The zipper input operation is from the array controller to the selected PME on the cluster.
Transfer data to a group of. The zipper input operation is initiated by the array controller run-time software.
The array controller run-time software must first call PMESI.
MD mode broadcast communication command ("SIMD / MIMD Processing
A PME is placed along the zipper interface in either zipper normal (ZN) mode or zipper line switched (ZC) mode using a related US patent application entitled "Memory Element". The software gives the SIMDPME software in ZN mode a count of words to receive, in which the PME can receive data from the X interface 80 (FIG. 5), but first the input buffer in memory for that interface. The two locations in memory are the start address of each input data buffer 232 and the buffer 23.
Reserved for storing the number of words stored in 3. In addition, PME control register 2 (FIG. 9) enables input interface 173 and input interrupt 172. The SIMD PME broadcast software loads to reserved memory locations to define the output data block and to load the PME control register 2 to allow the transfer of input data. In ZN mode, the PME is idle and waits for I / O interrupts or toggles to ZC mode.

FIG. 10 shows the zipper input operation when the PME has one possible configuration. This figure shows an example of transferring 8 words to three different PMEs. Data interface (zipper) sends data to PME260
To the PME from this PME via this array.

In the preferred embodiment of the present invention, the array controller first PE A260, PEB261, PE D.
263 is set to ZN mode and PE C262 is set to ZC mode. In the zipper input operation, setting the "Z" bit 163 and "CS" bit 170 of the PME control register 1 puts the PME in ZC mode. "Z" bit 16
By setting 3 and resetting the "CS" bit 170,
PE goes into ZN mode. Initial reception counts 3, 4, and 1 are assigned to PEs A, B, and D, respectively. P
EA receives the three data words using the normal receive sequence. When the word count reaches 0,
The hardware of PE A is "C" of PME control register 1.
Reset the S "bit 170 and ZC PE A264
Enter the mode. The same sequence is executed for PE B269 and PE D271. At the time of the last word transfer (to PED) 271, the array controller may insert a transfer complete (TC) tag bit 224.
When the TC bit is set, PE AD detects that bit and generates an I / O interrupt request 171. TC
PE A-D if bit 224 is not set
Remains in ZC mode 272-275 at the end of the transfer.

Request 240 on the zipper interface
Is detected, the receiving PME sends an acknowledgment 241 and loads the data into the input register 87. The receive sequence then begins, fetching the count 233 and decrementing it, fetching the input buffer address 232 and incrementing it, and storing the data word in PME memory 41. The receive sequence is similar to the transmit sequence. This sequence breaks into the idle PME and the memory 41
And cycle stealing access to ALU 42 to update the I / O address and count fields and load the input data word into memory 41. Either the count reaches 0 and the mode switches to ZC, or a TC tag is received and the corresponding input interrupt register bit 171 is set, interrupt code 1
This sequence continues until 90 begins to indicate "transfer complete".

The PME is:
Generate an acknowledgment in response to the request. The input registers 87, 100 are empty. The request is not suppressed 174. The interrupt 182 is not pending on the request input. -The request input is not switched. The request has the highest priority of all current requests.

The input registers 87 and 100 receive the acknowledgment 2
It is busy after 26 is generated until the receive sequence stores the data word in memory. Acknowledgments are suppressed when the input register becomes busy. When busy, the input register is prevented from being overwritten before the receive sequence is executed (since the receive sequence may be delayed due to memory refresh).

When the TC tag bit 224 is sent by the sending zipper, the input interrupt latch 171 for that interface is set. No further acknowledgments 226 are generated on that interface until the PME runtime software resets the interrupt latch. For example, if TC tag bit 224 is set during a data transfer from X interface 82:
Further requests from X are suppressed until the L interrupt is taken and the L interrupt latch is reset.

I / O interrupt 17 for the external interface if TC tag bit 224 is set, the data word is transferred, and the receiving PME is in ZN mode.
A 1 is generated and the interrupt code 190 is set to reflect TC. Furthermore, if the buffer count reaches 0 before the TC tag is sent from the sending zipper, the PME will toggle to ZC mode.

When in the ZN receive mode, the PME can only execute the memory refresh sequence and the receive sequence for zipper input. This is necessary because zipper data transfers can occur at maximum PME clock rates. There is no time for the execution of PME instructions or receive sequences for non-zipper inputs. PE during ZN mode
The hardware suppresses all input requests except zipper input requests. The ZC mode PME is related to the above-mentioned related patent application "PME Store and Forward / Circuit Switched Modes"
The full range of operation for PMEs in circuit switched mode can be performed as described in. It also includes the ability to use the splitter submode for zipper data.

The zipper output operation transfers data from the selected PME group in the cluster to the array controller. The zipper output operation is initiated by the array controller run-time software, which first
The MD mode broadcast command is used to place the PME around the zipper interface in either zipper normal (ZN) mode or zipper line switched (ZC) mode. The array controller then switches to PN SIMD in ZN mode.
Give the software the number of words to send.

Conceptually, data is transferred from the main memory of the originating PME to the main memory of the host computer. In the preferred embodiment, for each interface, two storage locations are reserved in memory for storing the starting address of output data block 230 and the number of words stored in block 231. Further, the PME control register 1 (see FIG. 8) controls the destination and mode of data output. Broadcast SIMD
The PME software defines the transfer mode,
The ME control register 1 is loaded. Broadcast SIM
Either the D PME software or the PME run-time software loads the data to be transferred to the host into the specified memory location. Then broadcast SIMD PM
The E software loads the address and count into the specified memory location. The software then loads the PME control register 1 and finally executes the OUT instruction to start the data transmission sequence.

The zipper output operation in one possible PME configuration is shown in FIG. In this figure, 8 words are different 3
An example of transferring to one PME is shown. The data interface (zipper) transfers data from the PME 280 and moves from PME to PME through the array.

In this example, the array controller is the first PE
A280, PE B281, PED283 are set to ZN mode, and PE C282 is set to ZC mode.
In the zipper output operation, setting "Z" bit 163 and "CS" bit 170 of PME control register 1 causes PME
Goes into ZC mode. "Z" bit 163 is set,
Resetting the CS "bit 170 puts the PME in ZN mode. PE A, PE B, and PE D are assigned counts of 3, 4, and 1, respectively.
A sends its three data words using the normal send sequence. When the word count reaches 0, PME
The hardware in A is "CS" of PME control register 1
Reset Bit 170 and PME A284 to ZC
Enter the mode. PME B289 and PME D2
The same sequence occurs within 95. PM of PMED
If the E control register "TC" 164 is set,
PMED on last word transfer (from PMED)
Inserts the transfer complete (TC) tag bit 224. T
If the C tag is set, PME AD will detect that bit and generate an I / O interrupt request 171. If the TC tag is not set, PM
EA-D remain in ZC mode at the end of the transfer.

Each time a data word is sent in the send sequence, the count 231 is decremented, the start address 230 is incremented, and one data word is read from memory 41. The data word is transmit register 4
PME 97,161 loaded and selected on 7,96
Sent to the interface. Transmission sequence is idle P
Breaking into ME to cycle steal access to memory 41 and ALU 42 causes the I / O address and count fields to be updated and the transmit registers 47, 96 to be loaded. For zipper transfers, CX bit 165 of PME control register 1 is set, resulting in the PME processor being idle until the transmission sequence is complete. This sequence continues until the count reaches zero.

The data transfer interface is 4 bits wide 97. Therefore, each 16-bit data word 220 is sent as four 4-bit intercepts (nibbles). A tag nibble 221 and a parity nibble 222 are also sent with the data. Transfer format is 2
23.

The transmission sequence is shown in FIG. On the interface, the sending PME issues a request 225 to the receiving zipper interface. Upon receipt of the acknowledgment 226, the sending PME may initiate the data transfer and the next transmission sequence may occur. The next transmission sequence does not occur until an acknowledgment is received.

TC bit 164 of PME control register 1
Is set, TC bit 224 will be set in the tag field of the last transferred data word. This bit informs the receiving zipper that the data transfer is complete.

When in the ZN transmission mode, the PME can only execute the transmission sequence and the memory refresh sequence. This is necessary because zipper data transfers can occur at maximum PME clock rates. There is no time for the execution of PME instructions or receive sequences for non-zipper inputs. During ZN transmission mode, PME hardware suppresses all input requests. ZC mode PME
Related patent application mentioned above "PME Store and Forward / Circuit S
The full range of operation for circuit switched PMEs can be performed as described in "witched Modes", including the ability to use splitter submodes for zipper data.

The zipper interface connects the array controller to the nodes on the cluster, as shown at the top and bottom of FIG. A typical interface consists of a two nibble (4 bit) unidirectional point-to-point interface, which results in a unidirectional full duplex transfer between two PMEs. Related patent application "PME Store and Forward / Circu
One P as described in it Switched Modes "
It is preferable to use the process described above to transfer 6 nibbles from the ME to the other PME. Basically, using data path 202, request line 203, acknowledge line 204,
Information is transferred from the PME on the left 200. At the same time, data path 210, request line 211, and acknowledgment line 212 can be used to transfer information from the PME on the right side 201. Data path 2 to put data into the array when the zipper is installed on the interface
14, request line 215, acknowledge line 216 are added, and data path 217, request line 218, acknowledge line 216 are added to exit the array. The array controller runtime software causes the runtime software of PME 200 to disable 202, 203, 204 when it wants to perform a zipper send sequence to PME 201. At the same time, the array controller run-time software
When you want to execute the zipper reception sequence to PME200, the runtime software of PME201
Disable 11,212. Note that the placement of zipper logic is quite arbitrary. It can easily be placed on the + X and -X interfaces of the same node, and can also be placed on any or all of the W, Y, Z node interfaces.

Although a preferred embodiment of this invention has been described, a worker of ordinary skill in this art would recognize that various modifications and improvements, both now and in the future, are within the scope of the following claims. The claims should be construed to maintain the proper protection for the invention first disclosed.

[Brief description of drawings]

FIG. 1 illustrates a typical enhanced parallel array processor (APA).
FIG. 3B is a functional block diagram illustrating P) and specifically showing the main elements of APAP and the APAP interface to a host processor or other data source / destination.

FIG. 2 is a schematic diagram illustrating an embodiment of a processor memory element (PME) node, and in particular showing the interconnection of the various elements that make up the node.

FIG. 3 is a schematic diagram showing a modified binary hypercube.

FIG. 4 is a schematic diagram showing a modified binary hypercube.

FIG. 5 is a schematic diagram showing a circuit switching path.

FIG. 6 is a schematic diagram showing a zipper connection on a single PME-PME interface.

FIG. 7 is a schematic diagram showing a zipper connection over two orthogonal connections to a cluster.

FIG. 8 is a schematic diagram showing reserved storage locations for interrupt and I / O processing. Here, the actual memory position is obtained by adding an offset to the starting storage address of the level range.
For example, the right input data buffer count is 00C
It is in O + 003D or ^ X ^ 00FD.

FIG. 9 is a schematic diagram showing PME control registers and interconnect networks supporting interrupt implementations.

FIG. 10 is a schematic diagram showing a zipper reception sequence.

FIG. 11 is a data flow diagram illustrating an example of a processor memory element. The main sections of this data stream are main storage, general purpose registers, ALUs and registers, and parts of the interconnect mesh.

FIG. 12 is a schematic diagram showing tags, parity, and data words transferred between PME inputs and outputs.

FIG. 13 is a schematic diagram showing a zipper transmission sequence.

FIG. 14 is a schematic diagram showing a PE input / output data flow.

FIG. 15 is a schematic diagram showing ordering of output interfaces between PME inputs and outputs.

FIG. 16 is a diagram showing a transfer sequence.

FIG. 17 is a schematic diagram showing a physical zipper interface.

[Explanation of symbols]

1 Host Processor 2 Host Memory 3 Application Program Interface (API) 4 Cluster Synchronizer 5 Cluster Controller 6 Cluster 20 Processor Memory Element (PME) 21 Broadcast / Control Interface (BCI) Unit 22 Ring 23 Node -Ring 26-node ring 151-node 152 Y-dimensional ring 153 4-dimensional array element 154 Interconnection path

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Clive Alan Collins, Monroe Drive, Pawkeepsie, NY 12601, USA 9 (72) Inventor Michael Charles Dup, USA 13760, Ivon Avenue, Endwell, NY 1130 (72) Inventor James Warren Diefendelfer Front Street, Owego, NY 13827, USA 396 (72) Inventor Donald George Grice, United States 12401, Kingston, NY Sawkill-Ravy Road 2179 ( 72) Inventor Billy Jack Knowles 12401, Kingston, NY Harley Avenue 72 (72) Inventor Donald Michael Resmeister United States 13850, Vestal, NY 108 Collins Hill Road 108 A (72) Inventor Richard Edward Near USA 13732, Appalachin, NY Forest Hill Road 109 (72) Inventor Elie Eugene Letter 34 Box 29 Be, H. Sea Earl, Warren Center, PA 18851, USA (72) Inventor David Bruce Rolf United States 12491, U.S.A. West Harry, Pine Tree Road 24 (72) Inventor Vincent John Smallal Skyline Terrace, Endwell, New York 13760, USA 812

Claims (11)

[Claims] 1. A means for interconnecting nodes as a ring of a folded torus without edges to the network, and logically breaking the ring along a dimension orthogonal to the ring so that the edge to the network is established. To dynamically toggle the network between edgeless and edged networks, to move data in and out of the network through the edge when it is active, and to traverse the edge Means to distribute data into or out of the network so that the data rate to be matched matches both the sustained and peak data rates of systems external to the network. A device for moving data in and out of a network of connected nodes . 2. When a logical break of the ring is performed n times, n
Claim 10 characterized by the fact that the resulting peak and sustained data rates through n edges approach n times the data rate through a single edge. The apparatus according to Item 1. 3. A ring connects nodes in an m-dimensional orthogonal form, n logical breaks in the orthogonal direction of the ring are performed in a plurality of orthogonal dimensions, and the same data is obtained by the multidimensional orthogonal break of the ring. A quadratic pass of the same data that is moved in and out of the network, resulting in a simplification and acceleration of processing for functions such as transposition and matrix multiplication in the network.
The device according to. 4. A processor memory element having a plurality of processor memory elements having a communication path to another processor memory element and a node identification, the nodes between the processor memory elements along the communication path providing a processing array. A computer system interconnected as an n-dimensional network with parallel communication paths, and further having a communication ring that, when broken, can provide an effective interface to the outside of the node I / O bus path. 5. Arranged as a massively parallel machine, the nodes are interconnected as an n-dimensional network with parallel communication paths between processor and memory elements along the internal and external communication paths providing a processing array. And a further break, a communication ring that can provide a valid interface to the external I / O bus path, and an external storage device or additional display device, a subset of the processor memory elements of the processing array of the nodes. 5. The computer system of claim 4, having an interface for connecting to. 6. A node is coupled with other nodes by a four-dimensional modified hypercube that supports eight external ports, the nodes being connected through the ports to form a ring and the matching ports interconnected. Allows you to interconnect rings into rings of a ring, thereby logically zipping the edges of folded clusters and connecting them to the external system bus for I / O to external systems. The computer system according to claim 4, wherein a folded cluster structure can be formed. 7. A ring within a ring, any or all of those rings logically breaking the interface to external I / O, and the two ends of the broken ring to the external I / O bus as a logical operation. By connecting, a modified hyper-extension that allows for topologies that allow regular interprocessor memory elements inside node communication at one time interval and I / O at another time interval. A break process at the level of the ring inside the modified hypercube, including cube interconnects, effectively "unzips" the ring for I / O purposes and resides on 1-n edges of the modified hypercube. Providing an independent interface into a potential array, parallel inputs to multiple dimensions of the array or multiple orders of the array Wherein the supporting broadcast communication to a computer system according to claim 4. 8. A configuration-specific application requirement in which a node array alternates data transfers into and out of the array between two nodes that are directly connected to the zipper, with zipper of different sizes. The computer system according to claim 4, characterized in that: 9. An application processor interface is provided for managing a path to an input / output zipper, wherein data received from a host system in attached mode or data received from a device in independent mode is transferred to an array, Computer according to claim 4, characterized in that the processor memory elements in the array managing the I / O are started before the start of this type of operation.
system. 10. A plurality of processor memory elements forming a node, each processor memory element having a communication path providing a processing array inside and outside the node, each node having a node identification. , Nodes are interconnected as a network with parallel communication paths between nodes, processors, and memory elements along the communication path providing a processing array, and when the system communication path is broken, an external I / O bus path is provided. A multiprocessor memory computer system characterized in that each node can be provided with an effective interface to one or more processor memory elements of a processing array of nodes. 11. A plurality of processor memory elements having a communication path to another processor memory element and a node identification, wherein the nodes are in parallel between the processor memory elements along a communication path providing a processing array. Interconnected as an n-dimensional network with communication paths, and the system has communication rings that, when broken, provide a valid interface to external I / O bus paths and external storage or additional display. An interface for connecting a device to a subset of processor memory elements of a processing array of nodes and a computer system.