JPH0628325A - Array processor communication network - Google Patents

Abstract

PURPOSE: To provide an H-DOT for scale reduction in network implementation. CONSTITUTION: The H-DOT approach can execute one of several mesh configurations based on two-port fundamental elements of the same. H-DOT uses two or more links between two points and combines their functions to form one network having two or more systems and attachments. For example, in a twodimensional mesh, two adjacent north-south links and two adjacent east-west links are coupled to form one network having four processing elements and attachments. When the H-DOT approach is used, a processing element is connected to the next processing element by a link providing two vertical routes and two horizontal routes for an apparently H-shaped connection link with respect to mutual connection of processing elements, and dot OR operation is performed with respect to other mutual connection of arrays.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to computers and computer systems, and more particularly to interconnecting an array of processors with SIMD, MIMD, and SIMID processing elements and passing information through the array of processors. The present invention relates to a communication network of array processors, which provides a network of

Glossary ALU ALU is the arithmetic logic unit part of a processor. Array An array relates to an arrangement of elements in one or more dimensions. An array can include this kind of ordered set of data items (array elements) identified by a single name in languages such as FORTRAN (abbreviation for Formula Translator). In other languages, the names of data items in this kind of ordered set are associated with ordered sets or sets of data elements that all have the same attributes. The program array is
Generally, it has a dimension specified by a number or a dimension attribute. Array declarators may specify the size of each dimension of the array in some languages. In some languages, an array is an array of elements in a table. In the hardware sense, an array is a collection of structures or structures that are generally identical in a massively parallel architecture.
An array element in a data parallel operation is an element to which an operation is assigned, and when parallel, it is an element that can perform the required operation independently and in parallel. In general, an array can be thought of as a grid of processing elements. Sections of the array can be assigned partition data so that the partition data can be moved around in a regular grid pattern. However, the data may be indexed anywhere in the array, or
Or can be assigned. Array Director The Array Director is the unit programmed as the controller for the array. The array director performs the function of a master controller for grouping the functional elements arranged in the array. Array Processor Two major array processor types, Multiple Instruction Multiple Data (MIMD) and Single Instruction Single Data (SIMD).
There is. In a MIMD array processor, each processing element in the array executes its own unique instruction stream with its own data. SIMD
In an array processor, each processing element in the array is limited to the same instruction through a common instruction stream, however, the data associated with each processing element is unique. The preferred array processor of the present invention has other features. We call it the Advanced Parallel Array Processor and use the acronym APAP. -Asychronous Asynchronous means that there is no regular time relationship, that is, the execution of a function occurs with respect to the execution of other functions that occur in a regular or unpredictable manner relative to the execution of other functions. , An unpredictable state. In the control state, the controller addresses locations where control is passed while data is waiting for idle (idle) elements to be addressed. This allows the operation to remain in a sequence that does not match any event in time. BOPS / GOPS BOPS or GOPS is an acronym with the same meaning as billions of operations per second. See GOPS.・ Circuit switch / Store switch
rward) These terms relate to two mechanisms for moving data packets through a network of nodes. Store Forward is a mechanism by which a data packet is received by each intermediate node, stored in memory, and then sent towards its destination. Circuit switching allows the input part of a node to be logically connected to the output part so that data packets can pass directly through these nodes towards their destination without entering into the memory of intermediate nodes. Is the mechanism that is commanded for.・ Cluster A cluster is a control unit (cluster controller)
A station (or functional unit) consisting of hardware (which may be a terminal, a functional unit, or a virtual component) attached to it. Our cluster contains an array of PMEs, often called a node array. A cluster typically has 512 PMEs.

In our overall PME node array, each cluster consists of a set of clusters supported by a cluster controller (CC). Cluster Controller A cluster controller is an input / output (I) to one or more devices or functional units connected to them.
/ O) is a device for controlling the operation. The cluster controller is, for example, IBM 3601 Finance Communication Controller (Finance Communication).
Controller), which is usually controlled by a program stored and executed in a unit, such as I
It may be entirely controlled by hardware such as the BM3272 control unit. Cluster Synchronizer A cluster synchronizer is a functional unit that manages the operation of all or part of a cluster in order to maintain the synchronous behavior of the elements, by which the functional unit has a specific time relationship with the execution of the program. Can be held. • Controller A controller is a device that directs the transmission and command of data via links of network interconnections. Its operation is controlled by a program executed by the processor to which the controller is connected or by a program executed in the device. CMOS CMOS is an acronym for complementary metal oxide semiconductor technology. It is commonly used to fabricate dynamic random access memories (DRAMs). NMOS is another technique used to fabricate DRAMS. Although we prefer CMOS, the technology used to fabricate APAP is not limited within the scope of the semiconductor technology used. • Dotting Dotting refers to joining three or more leads by physically connecting them. The buses on most back panels share this connection approach.
This term relates to conventional OR (or) dots,
Used herein to identify multiple data sources that may be coupled to the bus by a very simple protocol.

Our concept for input / output (I / O) zippers (fasteners) is that the input port to the node is
It can be used to implement the concept that it can be driven by an output port from a node or by data sent from the system bus. Data from a node, on the other hand, is available to both other nodes and to the system bus. Data output to both the system bus and other nodes is not done at the same time,
Note that it is done in different cycles.

Dotting is used in H-DOT discussion where 2-port PEs or PMEs or pickets can be used in arrays of various configurations by utilizing dotting. 2D and 3D (dot) mesh, base 2N-c
ube, sparse base 4N-cube
Several topologies are described, including (cubes) and sparse base 8N-cubes. DRAM DRAM is an acronym for Dynamic Random Access Memory and is a common storage device used by computers for main memory. However, the term D
RAM can be used for use as cache or memory that is not main memory. Floating point floating point numbers are represented in two parts. There is a fixed decimal point or fractional part and an exponent part for some hypothesized radix or base. The exponent indicates the actual position of the decimal number (decimal number). In a typical floating point representation, a real number 0.0001234 is represented as 0.1234-3, where 0.1234 is the fixed point part and -3 is the exponent. In this example, the floating-point radix or base is 10, indicating an implicit fixed integer base greater than 1 (unity), which is explicitly indicated by the exponent in the floating-point representation, or Alternatively, it is raised to the power to be displayed by a property in the floating point representation and then multiplied by the fixed point part to determine the real number displayed. Constants can be expressed in real numbers as well as in floating point notation. FLOPS This term indicates the number of floating point instructions per second. Floating point operation is ADD, SUB, MPY, DIV
(Add, subtract, multiply, divide), and often many others. The floating point instruction count per second parameter is often calculated by addition and multiplication instructions and is typically 50/5.
Can be considered to have 0 mix. This operation includes the generation of exponents and fractions, and normalization of any fraction needed. We could address floating point formats of 32 or 48 bits (or longer bits are possible, but we didn't mix-compute these). Fixed point instructions (normal or RIS
Floating point operations, when performed by C), require multiple instructions. 1 in digitizing performance
While a ratio of 0 to 1 may be used, one particular study has shown that a ratio of 6.25 is more suitable for use. Different architectures have different ratios. -Functional unit A functional unit is an entity of hardware, software, or both capable of achieving an objective. -Gigabyte (Gbytes) Gigabyte indicates 1 billion bytes. G bytes / s is billion bytes per second. Gigaflops Shows (10) 9th floating point instructions per second. GOPS and PETAOPS GOPS or BOPS both have the same meaning, indicating billions of operations per second. PETAOPS means trillions of operations per second, which is the current machine's potential. Our AP
With respect to AP machines, this term has almost the same meaning as BIPS and GIPS, which means billions of instructions per second. On some machines, a single instruction can result in more than one operation (eg, add and multiply), but we do not. Alternatively, multiple instructions may be required to cause one operation. For example, we use multiple instructions to perform 64-bit operations. However, when calculating the number of operations, we did not choose to calculate log operations. GOPS
May be the preferred use for explaining performance, but is inconsistent in such uses. MIPs / MOPs, BIPs / BOPs and MegaFLOPs / GigaFLOPs / Tera
See FLOPs / PetaFLOPs, etc.・ ISA ISA is an instruction set architecture.
t Architecture). -Link A link is an element that can be physical or logical. A physical link is a physical connection for connecting elements or units, but in computer programming, a link is an instruction or address that passes control and parameters between separate parts of a program. In multisystem, a link is a connection between two systems that can be specified by a program code that identifies the link, which can be identified by a real or virtual address. This generally means that the link is a physical medium,
It is logical and physical, including any protocol and associated devices, and programming. MFLOPS MFLOPS indicates (10) to the sixth power of floating point instructions per second. MIMD In MIMD, each processor in the array executes its own instruction stream, that is, a multiple instruction stream (Multiple Instruction Stream) in order to execute a multiple data stream positioned one for each processing element.
Stream), which is used to refer to the processor array architecture. Module A module is a functional unit of hardware that is designed for use with a discrete and identifiable program unit, or other component. Furthermore, a set of PEs (processing elements) included in a single electronic chip is also called a module. -Node In general, a node is a connection of links. In a comprehensive array of PEs, one PE can be one node. A node can also include a collection of PEs called modules. According to the present invention, a node is a plurality of PMEs.
, And we refer to a set of PMEs (processor memory elements) as a node. The node is preferably 8 PMEs. Node Array A collection of modules composed of PMEs, sometimes called a node array, is an array of nodes composed of modules. A node array typically has more than a few PMEs, but the term embraces the plural. -PDE PDE is a partial differential equation.・ PDE relaxation method solving process PDE relaxation method solving process is PDE (partial differential equation)
Is a method for obtaining the solution of. By solving the PDE, most of the computational power of the supercomputer in the known field is used, which can be a good example of the relaxation process. There are many ways to find the solution to the PDE equation, and one or more of the numerical methods includes the relaxation method.
For example, if PDE is solved by the finite element method,
The relaxation method consumes most of the computation time. Consider the example of the field of heat transfer. What happens to the temperature gradient inside a chimney brick when hot gas is flowing inside the chimney and cold wind is blowing outside? Consider a brick as a small segment and write an equation that describes how heat flows between the segments as a function of the temperature difference by writing the heat transfer partial differential equation (PD
E) is converted into a finite element method problem. Given that all elements except the internal and external elements are at room temperature, while the boundary segments are hot gas and cold air temperatures, the problem starting with the relaxation method can be assembled. The computing program then models the time by updating the temperature variable in each segment based on the amount of heat flowing into or out of the segment. This requires a large number of cycles to process all the segments in the model before the set of temperature variable values through the chimney relaxes to show the actual temperature distribution that may occur in the physical chimney. If the objective was to model gas cooling in a chimney, these elements should extend into the gas equation, and the internal boundary conditions should be linked with other finite element models, then this process Will continue. Note that the heat flow depends on the temperature difference between the segment and its neighbors. Therefore, this process will use the PE-PE communication path to distribute the temperature variable values. This is a neighboring communication pattern or feature that allows the PDE relationship to be suitably applied to parallel computing. • PICKET This is an element in the array of elements that make up the array processor. This element has a data flow (ALU R
EGS), memory, control, and part of the communication matrix associated with this device. This unit represents 1 / nth of an array processor consisting of parallel processors and memory elements, with some of the control and array internal communication mechanisms. The picket takes the form of a processor memory element or PME. Our PME chip design processor logic can implement the picket logic described in the relevant application or have the logic for an array of processors formed as nodes. The term picket is similar to the array term PE commonly used for processing elements, and is composed of a combined processing element and a local (local) memory for processing bit parallel bytes of information in a clock cycle. Preferably, it is an element of a processing array comprising: The preferred embodiment includes a byte wide data flow processor, 32 kilobytes or more of memory, initial control, and ties for communication with other pickets.

The term "picket" is understood because military picket lines are very similar in function, but has its origins in Tom Sawyer and his white fence. -Picket chips A picket chip contains multiple pickets on a single silicon chip. Picket processor system (or subsystem) A picket processor consists of an array of pickets, a network, an input / output system, and a microprocessor that operates a microprocessor and a canned routine processor and array. It is a total system that has a SIMD controller. Picket Architecture The Picket Architecture is a SIMD with features that adapt to several diverse types of problems, including:
It is the preferred embodiment of the architecture.

-Set related processing-Parallel numerical enhancement processing-Physical array processing similar to images-Picket array A picket array is a set of arranged pickets in a regular array of geometric order. PME or processor memory element The PME is used as a processor memory element. We use this term PME to refer to a system element or unit capable of input / output forming a single processor, memory, and one of our parallel array processors. Processor memory device is a term that encompasses pickets. A processor memory device is a processor array consisting of a processor, its corresponding memory, a control interface, and part of the array communication network mechanism.
It shows one part. The device can have a processor memory device having a regular array of connectivity, as described above, as in a picket processor or as part of a sub-array, as in a multiprocessor memory device node. Routing Routing is the assignment of the physical route by which a message reaches its destination. A routing assignment has a source or origin and a destination. These elements or addresses have a temporary relationship or similarity. Message routing is often based on the keys obtained by the assignment table. In a network, the destination is any station or addressable unit of the network that is addressed as the destination for the information sent by the routing address that identifies the link. The destination field identifies the destination by the message header destination code. A processor array architecture in which all processors in a SIMD array are commanded from a Single Instrustion stream to execute a Multiple Data stream, one allocated per processing element. SIMDMIMD or SIMD / MIMD SIMDMIMD or SIMD / MIMD is from MIMD to S at some time to process some complex instructions.
It is a term for a machine that has a dual function that can be switched to an IMD and thus has two modes. When placed as the front or rear end of a MIMD, Thinking Machine
s, Inc.) connection machine model CM2 allows programmers to operate different modes for the execution of different parts of the problem, sometimes referred to as dual mode. These machines have been the machines since Illiac and use buses that interconnect the master CPU (Central Processing Unit) with other processors. These master control processors have the ability to interrupt the processing of other CPUs. Other CPUs could execute independent program code. During the interrupt, a checkpoint (close and save of the controlled processor's current state) must be provided. SIMIMD SIMIMD is a multiple data that all processors in the array allocate one for each processing element.
In order to execute the stream, a single instruction (Single Instr
is the processor array architecture that is commanded from the stream. Within this configuration, data-dependent operations within each picket that mimic instruction execution are SIMD.
Controlled by the instruction stream.

A single instruction stream machine that has the ability to sequence multiple instruction streams (one for each picket) using the SIMD instruction stream and operate on multiple data streams (one for each picket). SIMIMD may be implemented by a processor memory device system. -SISD SISD is an acronym for single instruction single data. -Swapping Swapping replaces the data contents of the storage area of the storage device with the data contents of other areas of the storage device. Synchronous Operation The synchronous operation of the MIMD machine is an operation mode in which each action is associated with one event (normal clock), and is a specific event that occurs regularly in the program sequence. An operation is sent to multiple PEs, which proceeds to perform this function alone. Control is not returned to the controller until the operation is complete.

If the request is for an array of functional units, the request for an element in the array is generated by the controller, but this requesting action must be completed before control is returned to the controller. TERAFLOPS TERAFLOPS means (10) to the power of 12 floating-point instructions per second. VLSI (as applied to IC) VLSI is an acronym for Very Large Scale Integrated Circuits.・ Zipper The zipper is a new feature provided. This allows the links to be made by devices external to the normal interconnection of the array's configuration.

[0010]

BACKGROUND OF THE INVENTION In the never-ending quest for faster computers, engineers have come to the task of creating hundreds, and even hundreds, of thousands to create branched super supercomputers in order to overcome the complex problems that plague today's machines. Thousands of low cost microprocessors are linked in parallel. Such a mechanism is called massively parallel. We have created a new way to build massively parallel systems. Many of the improvements we have made are considered in the context of many other jobs. This field is summarized in other referenced applications. For this, see US Patent No. 601,594, which describes our Parallel Associative Processor System and our Advanced Parallel Arra Processor.
y Processor-APAP).
System replacement is required to select the architecture that is most suitable for a particular application, but to date no satisfactory solution has been available. Our idea is to simplify the provision of solutions.

The interrelationships of processors in an array of processors, the methods used to communicate between the processors, have been the focus of considerable research, as cited in the literature for arrays of this type. Many studies
Focusing on minimizing the number of steps to move a message between any two elements of an array, many studies have supported image processing and other very regular problems of this kind. Emphasis has been placed on communicating with neighbors to do. In essence, SIMD or MIMD type parallel array processors require a highly organized and effective connection network for communication between processing elements (PEs).

The communication network may be required to communicate synchronously with all pickets transferring data in the same direction at the same time, or communicate randomly, such that each picket sends messages to random locations at random times. May be required to do so. The latter approach is called routed transfer.

Synchronous and router (route) transfers need to be addressed in either the MIMD or SIMD array control architecture, while attempting to simplify this communication complexity.

Several communication topologies have been described in the literature and are implemented in various ways in array machines. The basic communication topology is simple left-right connectivity in a linear array. In a linear array, each of the two-port PEs (processing elements) communicates with the processing element via a point-to-point network at either the right or left position. In a wider range of conventional mesh topologies of two or more dimensions, communication networks are implemented using direct links between source elements and elements in the dimension in which they are implemented. Therefore, each element has two links for each dimension of the array, so that in a prior art two-dimensional array with a NEWS (north-west-south-west) network, each element has four links to other elements. Will have a link,
And if another dimension is added, two more links must be added to each element of the mesh. Inside each element of the conventional mesh is a router function that receives and transmits message or data packets via suitable links. In some multi-based, multi-dimensional hypercube (hypercube) embodiments, the hypercube represents a near-final column of the processor array communication network. For example, in the case of a binary hypercube, the number of ports reaches the effective ratio quickly.

The processing elements in the prior art array are:
It requires enough ports to reach the required elements by the point-to-point network link. Depending on the topology (connection form) and extent (range) of the network to be executed, some processing elements have 4 ports, some processing elements have 6 ports, some processing elements have 8 ports, and some processing elements have 30 ports (32k elements). 15 dimensional binary hypercube). Furthermore, each link is
To meet ever increasing data transfer rate demands,
It can include 1 to perhaps 50 parallel lines.

When we incorporate these topologies into our hardware, we have chips, cards, drawers, racks,
And packaging of these arrays in a room (space) prompts us to pay attention to the number of links and the number of signal pins in each link. Wafer technology has enabled more circuits to be used per chip, making arrays of parallel processors increasingly useful and higher density arrays desirable.

This application uses a dot-processable network to interconnect two-port processing elements to implement many of today's topologies, while effectively reducing packaging pin counts. The main purpose is. Packaging an array of pickets with an arbitrary mesh configuration presents some packaging issues, most of which are limited to available package pins or desired reduction in pin count. It is related to

In the prior art of the patent, SI is generally
There are patents that describe MD and other networks. For example, US Pat. No. 4,270,170 describes a NEWS network connected SIMD array in which three dot-processed branch networks are used to interconnect chips containing four processing elements each. . Simultaneous transfers in one of multiple directions are provided. By using the dot network, there are 8 to 6 ports on one chip.
25% in pin count
Reductions can be achieved. In this patent only 2D (dimensional) networks are mentioned. Wide area routing technology reaches all elements in the array and
(North-south-west-south) Oriented by two lines that encode the four directions common to the network. This patent describes a prior art dot processing network to reduce the number of pins and ports through the network, but since only three branches can be addressed instead of four branches in each network,
With more than three ports per processing element (3.5 ports on average), this would lead to higher pin and port counts than we have reached. This patent describes only 2D (dimensional) NEWS networks. We have shown that it would be desirable to provide extensions to other dimensions and configurations, but this patent does not address these issues. Clearly, the array of this patent requires simultaneous transfer of data in a particular direction.

US Pat. No. 4,468,727 describes an array processor in which an array of radiation sensors is integrated such that image processing is performed on the same monolithic substrate with the sensors. Interconnection between the processing elements is accomplished by charge-coupled gates on the NEWS (northwest, southwest) edges of each processing element, and thus this patent represents only one of many NEWS arrays. This array processor does not have a dot communication network.

US Pat. No. 4,805,091 describes a hypercube interconnect used by machines manufactured by Thinking Machines., Inc., such as Connection Machines. A preferred example of a network is shown and 2 for packaging processing elements into chips, cards, boards, frames, etc., where each package is achieved by a higher (or lower) dimension hypercube. It describes the application of the Sudoku hypercube. Although this patent does not describe the morphology of the dot-based mechanism at all, it does describe a binary hypercube. This patent is another example of the applicability of the present invention, which is a dot communication network for array processors, as the present invention can be used to implement binary hypercubes. However, this patent does not describe the dot bus we illustrate.

US Pat. No. 4,985,832 is another example of a SIMD array processing system having a routing network. This patent describes a NEWS mesh that provides regular array processing, a mechanism by which processing elements can share large broadcast communication tasks, and several "butterfly" stages followed by a 16x16 crossbar switch. It describes a small group of processing elements that communicate through a shared memory with a random routing network of. However, this patent focuses on random routing, including crossbar switch chips, and this deficiency is a durable aspect. The patent focuses on a number of communication technologies, but does not mention the dot mechanism.

US Pat. No. 4,910,665 discloses that each processing element directly accesses eight of its neighboring elements.
A dimensional SIMD array processor interconnect technology is described. This communication medium is a dot processing network that interconnects four neighboring elements at the corners. Each processing element enjoys four such dot networks. Both the X-DOT proposal in this patent and the dot connection called H-DOT allow four processing elements to be connected by a dot network. However, this patent only mentions the topology of the mesh and the extension to the toroid (annular surface) and focuses on the circuitry within the processing element. We believe that improvements around connectivity and routing are needed.

[0023]

The improvement of the present invention lies in the dot network structure (H-DOT). HD
OT reduces the scale of networking practices.
The preferred embodiment of the invention applies to any number of topologies. Furthermore, H-DOT in the array
The connection processing elements allow the array of processors to be generally scaled in size and additional dimensions while retaining the basic two-port array processing elements. Both synchronous and routing transfer control can be included in the present invention, below we describe the routing algorithm of the present invention.

Although new machines are available today with parallel arrays on chips and multibyte word transfer capabilities, pin counts are becoming a serious problem as mesh communication paths become more parallel. . The present invention can be used to connect a microcomputer to parallel communication paths.

The H-DOT concept of the present invention is very suitable because it allows parallel communication with various topologies.
The H-DOT concept has 2 ports (more in some cases)
Is an approach for applying a processing element having a to various types of interconnection topologies. The pin count can be effectively reduced while the basic element holds only a two port debauss. The result of the inventive approach is the ability to extend the mesh to an additional dimension by the same two-port element concept. In the preferred embodiment of the invention, each processing element (PE) is limited to exactly two ports, regardless of the desired configuration. Therefore, each processing element (picket) is connected to exactly two nets.

We provide that each net can extend to several other pickets in multiple dimensions.

The pin count is reduced and our mechanized routing algorithm takes advantage of the above features. The routing algorithm that processes a message after it has been received is straightforward. If the message corresponds, then the message is held, or if it does not, the message is passed to another port.

The advantages of the H-DOT approach are: Pin reduction Simplified router (routing) algorithm Shorter transit time network traversal Potentially a few hops (nodes) Higher signaling in light load systems The ability to be placed and configured on a standard net is effective fault tolerance using alternative routing.

[0029]

[Means for Solving the Problems]

We have created a new way to create massively parallel processors and other computer systems by creating new "chips" and systems designed according to our new concept. This application relates to such a system. Our views are set forth through the representation of various concepts we teach in this and related applications. The components shown in each application are combined in our system to create a new system. These components can also be combined with existing technology.

In this and related applications, the picket processor and the so-called highly parallel array processor (AP
AP) will be described in detail. It is interesting to show that the picket processor uses PMEs (processor memory devices). Picket processors may be particularly useful for military use where very miniaturized arrays are desired. In this context, the picket processor is our highly parallel array processor (APAP).
Is slightly different from the preferred embodiment relating to. However, there is commonality and the aspects and features we have provided can be used to distinguish machines.

The term picket refers to the 1 / nth element of an array processor that is composed of a processor, memory, and communication elements applicable for intercommunication of the arrays contained therein.

The picket concept is also applicable to 1 / nth of an APAP processing array.

Although the picket concept may differ from APAP in data width, memory size, and number of registers, in a massively parallel embodiment, which is an alternative to APAP, the picket concept is that the PME in APAP is part of a subarray. However, it is configured to have connectivity for 1 / nth of a regular array. Both systems perform SIMIMD. However, since the picket processor is manufactured as a SIMD machine with MIMD in PE, SIMIMD
MIMD APA
The structure of P is controlled by MI to mimic SIMD.
SIMIMD can be performed by using MDPE. Both machines use PME.

In both systems, 1 / nth of the processor array is part of the processing element, its associated memory, control bus interface, and array communication network.
An array processing unit for an array having N elements interconnecting with an array communication network is provided.

A parallel array processor can have its processing units commanded to operate in either of two modes, or in two modes, and these two modes for SIMD and MIMD operations. It has a dual operating mode capability that allows it to move freely between, and when the SIMD is in its mode of operation, the processing unit commands each element to execute its own instructions in SIMIMD mode. And the MIMD is in execution mode for processing unit organization, the processing unit has the ability to synchronize selected elements of the array to simulate MIMD execution. . We call this MIMD-
It is called SIMD.

The parallel array processors in both systems provide the array communication network with paths between the elements of the array for passing information. For moving information, the first way the array controller specifies that all messages go to the same destination at the same time so that the moving data does not define its destination.
Each message decides where to go Self-routing (self-routing) by header at the beginning of the message
The second method is performed, and the two methods are directed.

A segment of a parallel array processor comprises multiple copies of a processing unit provided on a single semiconductor chip, each copy segment of the array having a portion of the array communication network associated with the segment, a buffer, and In order to expand the multiplexer and this array communication network,
A controller for enabling a segment portion of the array to be seamlessly connected to other segments of the array.

The control bus or path from the controller is
A control bus extends for each of the elements of the array and is provided for each processing unit to control its operation.

Each processing element segment of the parallel array has multiple copies of processing memory elements contained within a single semiconductor chip, and for supporting control communication to the array segments contained within the chip. Includes a portion of the array control bus and a register buffer.

Both can perform mesh movements or route movements. APAPs typically implement a dual interconnect structure with eight elements on the chip that are interrelated in one direction, but the chips are otherwise interrelated. On-chip programmable routing allows links to be set up between the PMEs (processor memory devices) described above, but nodes can be, and usually are, otherwise associated. On chip, a typical APAP arrangement is essentially a 2x4 mesh, where the interconnections of nodes can be rooted sparse octal N-cubes. Both systems allow PEs (or PMs) to allow the matrix to be constructed from point-to-point paths.
E) There is a PE intercommunication path between each other.

An aspect of the present invention is a parallel SIMD or M with multiple processing elements interconnected in an array topology that mechanizes the interconnections between processor array elements, depending on the interconnection network configuration.
An IMD array processor communication network, wherein said interconnection network configuration allows processing elements to each of a plurality of directions by apparently H-shaped connections which are links providing two paths to the next processing element in each dimension Is an array processor communication network comprising allowing interconnection with the following processing elements.

[0043]

DESCRIPTION OF THE PREFERRED EMBODIMENT The basic communication topology that can be used to send data from a processing element (PE) to a processing element is a linear array in the prior art.
2 is a simple left-right connectivity of the linear array shown in FIG. Each of the 2-port processing elements has 2
It communicates with either the left or right processing element via a point-to-point network. The basic idea of a 2-port processing element is the basis for the description of the H-DOT structure of the present invention.

In a wider range of conventional mesh topologies, communication networks are implemented using direct links (interconnections) between source and destination elements. Therefore, each element has two links for each dimension of the array. For example, NEWS (North, East,
In the conventional two-dimensional array by west, south) communication,
Each element has four links to the other elements, as shown in FIG. If other dimensions are added, then two more links must be added to each element of the mesh. Within each element of a conventional mesh is a router function that receives and transmits message or data packets over suitable links.

In the communication network, all pickets are
Either "synchronous communication" may be required to transmit data in the same direction at the same time, or "random communication" in which each picket sends messages to random locations at random times. The latter approach is called routing transmission. Both of these types of communication may need to be addressed to either the MIMD or SIMD array control architecture, and try to keep the communication complexity simple.

Each link can include from 1 to perhaps 50 parallel lines to meet ever-increasing data rate requirements.

Packaging of an array of pickets with arbitrary mesh configuration presents some packaging problems, most of which are limited or required use of package pins. Regarding the desire to minimize the number of pins taken.

A parallel related processor system (The Parallel Associative, cited above as a related application)
Processor System) is described in a parent patent application that focuses on a linear left-right communication mesh. However, several interconnected meshes are possible, as follows.

Left / Right (L / R) Mesh NEWS Mesh Slide Bus Shuffle Network Simple Crossbar Base 2 N-Cube Slide Crossbar Base 8 N-Cube

Ports and pins in a given topology
We describe how to implement some of these array interconnect topologies using the H-dot idea in order to significantly reduce the count.

Approach-H-DOT

Control of mesh communication can be classified into two categories. If the communication is regular, some form of global control directs all pickets to do the same. This can be done simultaneously or stepwise in some way. This type of communication is commonly associated with SIMD control organizations, however, it works as effectively as MIMD organization arrays.

In the preferred embodiment of the present invention, HD
OT is based on a basic two-port device that is all the same,
One of several mesh configurations can be performed. H-DOT can employ more than two point-to-point links and combine these functions into one network with attachments to more than two processing elements. For example, in a 2D (dimensional) mesh, two adjacent NS links (north-south) and two adjacent Es.
-W (East-West) links are combined to form one network with attachments to four processing elements. Mathematically, this four-port network replaces four two-port networks, resulting in a pin count of five.
It can be reduced by 0%. This is shown in FIG. 3 which shows a 2D mesh implementation with H-DOT interconnection technology. Further, as shown, NS (North-
Since the (south) link shares the same wire, array-wide synchronous transmission requires two cycles. One of these cycles can be for an even number of processing elements and the other cycle can be for an odd number of processing elements. When H-DOT is used, the interconnection of the processing elements provides that the processing elements provide two vertical paths and two horizontal paths to the link, which is apparently an H-shaped connecting link. The link is a dot-OR to the other interconnects in the array as shown in FIG. 3 so that it can be interconnected with the next processing element.
The square processing element in the preferred embodiment of the present invention is more than one processing element, or a picket or a chip having eight or sixteen pickets. In this regard, see the related application for additional details of suitable processing elements of the present invention. However, for the purposes of this application, the square processing element of the present invention may represent a conventional microcomputer.

The advantages of the H-DOT approach have been summarized above, but as is true without exception, HD-D
The OT approach also has its drawbacks. While the impacts of the H-DOT concept in some environments have minor impacts are listed herein, in other applications these impacts are significant. These effects are: Synchronous transmission, in which all elements simultaneously pass data in the same direction, required only one clock in the conventional implementation, but requires two clocks (or cycles) in the H-DOT implementation.

2. When routed transmission is performed, the H-DOT approach introduces temporary blocking, which is important when communication traffic is congested. This does not result in message loss, but it increases the time spent in transmission.

If the communication is of a random type, each message carries a destination address and may pass down the intermediate node, but through the network. Therefore, each element must implement some form of routing algorithm. The router (router) may be independent of the parallel processor control organization or may be incorporated into the parallel processor control organization.

In the case of a two-port element, some, but not many of the algorithms, require determining how to process the messages received by this element. This message either belongs to this element or is transmitted to the other. This algorithm is
It is universal for all forms of mesh implemented by two-port pickets or processing elements.

There are other algorithms that determine whether to accept an available message at a port. In the two-dimensional NEWS network, there are four ports to access the message, but only one port can actually receive the message. The algorithm for deciding to receive a message is based on getting the message to its destination and avoiding dead routes. This acceptance algorithm is based on the array configuration and is described below by the particular array.

H-DO for the following mesh topologies:
T will be described in detail. NEWS (northwest-southwest) mesh 3D mesh Binary N-Cube Base 4 N-Cube and Octal N-Cube

3-D NEWS Array

In this first description, in order to achieve a two-dimensional NEWS array, the above-mentioned EW shown in FIG.
(East and West) Basic 2 used in slide bus
Use port pickets.

In general, H-DOT uses wire dot-OR to connect one port from four (or more) different pickets. Another dot-OR connects one other port of the plurality of pickets with three (or more) other pickets. FIG. 3 shows a basic H-DO for a two-dimensional mesh.
The T pattern is shown.

One of the advantages of the H-DOT approach is that the number of pins on each device is reduced by half, and the number of links in various parts in the 2D mesh is reduced to two.
It lies in a reduction of more than half compared to the number required by the D (4 port) mesh. FIG. 3 shows that a single H-DOT link provides two vertical buses and two horizontal paths.

Another advantage of the H-DOT approach is its scalability. We can evolve from the 2-D (2-dimensional) mesh above to a 3-dimensional mesh by performing a double (double) H-DOT as shown in FIG. In this case, four elements per 3-D array connect to a DOT network that looks like a double H (Double-H), with one H type on top of the other H type. The inset of FIG. 4 shows one double H-DOT for clarity. Looking closely at FIG. 4, these double H-DOTs show that each processing element connects with each neighboring element in each direction, and
Staggered (staggered) in each dimension to maintain the integrity of the connection.

H-DOT communication requires more communication cycles than point-to-point links (interconnects). Two
DH-DOT requires one or two cycles for each picket to send data to the picket on a particular side. In addition, the double H (shape) forms four paths in each dimension, thereby requiring four cycles for every picket to send data to the picket in a particular direction.

Routing algorithm

The NEWS network is designed to be used for imaging and other regularly arranged data processing. In this case, the array controller directs all the elements to pass data to the elements on the same side at the same time.

The NEWS network can also be used for random communication. In this case, a router that has a routing algorithm to initialize the message, receive the message, and pass the message (route
r) must be present. With the H-DOT approach, an element must decide to receive a message from the active port. With respect to FIG. 3, if device A sees the message from the left port, device A receives the message if the destination address is:

The address of the message itself (Xd = X
o, Yd = Yo) -OR (logical sum) --- in the upper right quadland (quarter section) of the mesh, that is, destination X address => address of message itself or destination Y address = <address of message itself

Note that there are four different algorithms depending on whether the element is in position A, B, C, or D.

Binary hypercube

Next topology for explanation (connection form)
Uses H-DOT to implement a binary hypercube.

FIG. 5 shows a typical 4-dimensional binary hypercube. Each element of the cube has one connection for each dimension. An array of effective size has multiple dimensions because each dimension has only two values. The four-dimensional cube has 16 elements each having 4 ports. 102
An array with 4 elements is a 10-dimensional binary cube with 10 ports for each element.

When the binary n-cube is implemented in H-DOT, the four-dimensional version looks like FIG. Each element has two ports and is connected to the dot-OR bus in a characteristic H-DOT configuration (slightly offset) with respect to its communication partner.

The H-DOT limits the number of ports for each element to two, and greatly reduces the pin count as compared with the conventional embodiment, and the message can be reached each time the message moves. We are increasing the number of destination options. For example, in the conventional n-cube, the element 0000 is moved to 0001, 0010,
Four links can be used to communicate with addressable processing elements such as 0100 and 1000. When the H-DOT approach is performed, the element 0000 is moved to 00
Two links can be communicated to addressable processing elements such as 01, 0100, 0101, 0010, 1000, and 1010. In a four-dimensional binary cube implemented in H-DOT, when an additional connection is made in this way, compared to a conventional binary cube having a low message density,
The average number of moves per message is reduced by 25%. Thus, performing an H-DOT on a binary cube will yield something that is no longer just a binary n-cube. The binary n-cube definition indicates that a processing element connects to another processing element, and the address of this other processing element is one bit different from this processing element. However, in any case, this is nothing but a binary n-cube.

In FIG. 7, a 6-dimensional binary cube implemented in H-DOT with a 2-port processing element is shown. Further, notice that the maximum number of trips to send a message from any of the 64 elements to any of the other elements is 2 degrees. And each double H-DOT
Connect with 8 processing elements.

At one point, H-DOT is
It becomes ineffective due to problems with large wire dot nets and possible collisions on nets in high density messages. This may limit the applicability of binary n-cubes to relatively small arrays with as few as 32 processing elements per H-DOT. The sinking current (current on the receiving side) in a large dot-OR network poses a problem. This description applies particularly to binary cubes, however, at some point, inserting a transceiver in the net eliminates some of these problems.
The NEWS network does not have such a problem because random communication requires moving more intermediate nodes back and forth and left and right, but no matter how wide the range is, it remains a two-dimensional array.

Routing Argo for Binary n-Cube
rhythm

6 and 7, each element and each H-
Note that DOT is identified. The top left element is numbered 0000 and one of the element's links is numbered x0x0. The link name is a reference for all devices connected to the device. Acceptance algorithms for routing transmission mechanization are based on these link names.

When an element finds a message that is active on one of its links, only one of the elements, one, will accept the message. Our algorithm is unbelievably simple: "Accept the message when the destination matches the back link name ('Accept the message
when the destination matches the back side link n
ame ') ”is displayed. Four destinations are links x0x
Matches 0. These are 0000, 1000, 001, respectively.
0 and 1010. Note that the front and back links are orthogonal to each other, and one destination matches only one link.

After an element of the array chooses to receive a message, if the destination address matches the address of that message, then this element holds the message or ('else') it passes this message. .

When an element of the array needs to send a message, the destination address is two connected HDs.
Matches only one of the OT netnames. This is the port on which you can start messages.

The following is a summary of the H-DOT implementation of a binary n-cube.

[0084]

[Table 1]

To explain, the column called'DIM 'indicates the dimension of the binary n-cube. 'Element' is the number of PEs or processing elements that make up the binary n-cube of this dimension. 'Links' is the total number of separate nets or groups of interconnected ports needed to implement a binary n-cube of the dimensions shown when using the H-DOT interconnect technique. is there. '' Taps / Li
nks' (tap / link) indicates the number of taps or ports in each link. Finally, the last two columns show the maximum and minimum number of cycles required to move data from all elements to an element in one particular direction simultaneously. The term'Link 'refers to one of the DOTTed networks that combine processing elements (PEs).

Base 4 n-cube

There is increasing interest in implementing higher order N-cubes. The economics of interconnection drive this concern. Our H-DOT concept matches (mesh) exactly with good high-order N-cubes. For the sake of simplicity, we first describe the base 4 n-cube of a full implementation, then a sparse implementation, and finally a sparse base 4 implemented with H-DOT. The n-cube will be described.

FIG. 8 shows a standard base 4 n-cube. Each processing element connects to another processing element if its address matches the address of the other processing element in all but one digit.

The two-dimensional base 4 n-cube has the following 1
It has 6 elements: 00, 01, 02, 03, 10, 11, 1.
2, 13, 20, 21, 22, 23, 30, 31, 32, and 33. In the base 4 n-cube, the element 00 is 00, 01, 02,
Connects directly with 03, 10, 20, and 30. This rule also applies to other processing elements. Therefore, each processing element has 6 ports.

Sparse Base 4 n-Cube

We introduce the idea of the sparsity of a two-dimensional base 4 n-cube. To reduce the number of links and make the array easier to implement, one designer proposed simply removing some from the links. This is done by limiting the connection with an element (PE) that has all but one digit that matches two adjacent processing elements (PE) in that dimension. In the example above, therefore, PE00 is 01,
Limited to 03, 10 and 13, and connected. FIG. 9 illustrates this.

H-DOT Execution Base 4 n-Cube

We used H-DOT with a 2-port PE.
Implement a sparse two-dimensional base 4n cube in mechanization. The result is shown in FIG. This is a great simplification of the number of ports and networks compared to the implementation of FIG. Note, of course, that routes are shared and more cycles are needed. This array, as shown for the base 2 N-cube,
It can easily be extended to more dimensions.

H-DOT Octal N-Cube

An approximate relative cube of binary and base 4 n-cubes is an octal n-cube with 8 elements instead of 2 or 4 elements in each strip of the array. FIG. 11 shows a sparse 2 connection made by a conventional method.
A dimension octal n-cube is shown. Elements of a two-dimensional octal array have a pair connection, one connection is positive and the other connection is negative, for each dimension. Other pairs are added for each additional dimension, as in the binary cube.

FIG. 12 shows an H-DOT equivalent to a sparse two-dimensional octal n-cube. All of the advantages of this prior art, including reduced pin count, increased connectivity, and expandability (of range) are compatible.

The following is a summary of the implementation of octal H-DOT.

[0098]

[Table 2]

The H-DOT interconnect topology is particularly suitable for use in n-cubes with higher bases. 40 in 4 dimensions, based on octal radix
An array of 96 elements can be reached. The distance remains short despite the path collisions. The optimal distance between any two elements of a two-dimensional octal n-cube is 8 for conventional topologies and H-DOT
It is 4 in the case of topology. This is a factor that is improved by 2.

H-DOT Octal n-Cube Routing
algorithm

N-Cube topologies generally use routed message transmission techniques as opposed to synchronization techniques. We will discuss different radix n-cubes,
And we introduced sparseness and our H-DOT implementation of sparse octal n-cubes.

We describe a routing algorithm for multidimensional octal n-cubes. The routing algorithm has three parts. Initialize message, send message, receive message,
And to hold the message. Note that using sparsity is costly. Cost is the cost of the additional transfer to reach the target processing element after the address digits have been selected to match.

1. INITIATE: The PE initializes the message with the port closest to the destination on a given unmatched digit. With respect to FIG. 12, processing element (22) has the message of processing element (34). Processing element is from port to processing element (23)
Send a message to. This allows DestX
Is larger than the element X, or DX = EX and D
If Y> EY then the right port of the processing element (42) is used. (D indicates the destination, E indicates this element) ACCEPT: A message is received if the address matches the processing element or if the processing element can move the message closer to the destination. Therefore, the processing element (42) is DX =
If> EX and DY = <EX, then receive the message from the left. 3. KEEP: Keep the message if the message is for that processing element, otherwise pass the message to another port.

As with mesh routing, there are four different sets of routing criteria depending on the location of processing elements on the H-DOT.

FIG. 13 shows a block diagram of the parallel array processor we previously described with a two-dimensional H-DOT array, while FIG. 14 shows the picket (PM) we previously described.
E) is shown. It is not necessary to repeat the description incorporated by reference, as already described with the above figures by means of additional details about the related application. The system is a parallel array processor that provides SIMD (single instruction multiple data) / MIMD (multiple instruction multiple data) operating characteristics. Picket PME
The (processor memory device) does not have to embed the entire operating system, but can function independently in MIMD mode, and SIMD by dynamic switching.
It can also work in mode. Each picket has the arrangement configuration described above and the other configurations.

[0106]

The present invention seeks to provide an H-DOT approach for reducing the scale of network implementations.

[Brief description of drawings]

FIG. 1 shows a conventional linear array that typically utilizes a two-port processing element (PE).

FIG. 2 shows a NEWS network conventionally connected by four point-to-point links with each of four adjacent processing elements (PEs).

FIG. 3 is a diagram showing the implementation of a NEWS network using H-DOT connection technology. (Note that the processing element (PE) is 2 ports rather than 4 ports.)

FIG. 4 is a diagram showing execution of a three-dimensional mesh using the H-DOT connection technique. (Note that the processing elements are 2-port rather than the traditional 6-port processing elements used in conventional 3D mesh arrays.)

FIG. 5 illustrates a 4-dimensional conventional binary N-cube implemented on a 4-port processing element.

FIG. 6 shows the implementation of a 4-dimensional binary n-cube using the H-DOT connection technique. (The processing element is 4 in FIG.
Note that it is a 2-port rather than a port processing element. )

FIG. 7 shows the implementation of a 6-dimensional value n-cube using the H-DOT connection technique. (The processing element is a conventional n-
Note that it is 2 ports rather than the 6 port processing element used in the cube implementation. )

FIG. 8 is a diagram showing a conventional base 4n-cube.
(There is a path to all processing elements that have one base 4 address digit different from the first processing element.)

FIG. 9 shows a sparse base 4n-cube. (There is a path only to processing elements that have one base 4 address digit that differs from the first processing element by only one address.)

FIG. 10 shows a sparse base 4n-cube implemented by the H-DOT connection technique. (Each processing element has two ports.)

FIG. 11 is a diagram showing a sparse n-cube idea digitized to base 8 and showing this type of topology.

FIG. 12: Sparse 8 performed using H-DOT connection technology
FIG. 6 is a diagram showing execution of a binary n-cube. (2 processing elements
Have a port. )

FIG. 13 is a block diagram of the above parallel array processor with a 2-D H-DOT array.

FIG. 14 is a view showing the picket processing element.

 ─────────────────────────────────────────────────── —————————————————————————————————————————————————————————–——————————————— PrinceMichaelCoggs / DorchesterDrive7, Endicott, NY 7760

Claims (4)

[Claims] 1. A parallel SIMD or MIMD array processor communication network comprising a plurality of processing elements interconnected in an array topology that mechanizes interconnections between processor array elements with an interconnection network configuration, the method comprising: Interconnecting a processing element with each subsequent processing element in each of a plurality of directions by an apparent H-shaped connection that is a link that provides two paths to the next processing element in each dimension, depending on the interconnection network configuration An array processor communication network comprising allowing. 2. The array processor communication network of claim 1, wherein the processing elements are connected to neighboring processing elements via ORdot network connections. 3. The array processor communication network of claim 1, wherein the communication control for interconnection within the array processor can be of the synchronous type or the routing type. 4. The array processor communication network of claim 1, wherein the array can be expanded in area or size by adding to an existing interconnection network or by adding additional networks.