JPH0675742A - Data converter - Google Patents

Abstract

PURPOSE:To provide a data converter which can automatically convert the array of bytes in a memory access mode. CONSTITUTION:The data buses 5-8 are connected to a processor 9 via a selector 21. The information 17 showing the arrangement sequence of the data on pages is stored in response to each page in a page table 14 of an address converter used by the processor 9 in a memory access mode. Thus the selector 21 refers to the information 17 in a memory access mode and supplies the data to the processor 9 after conversion of the arrangement order of data on the data buses.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system, and more particularly to a data conversion system for controlling access to data on a data bus of a processor.

[0002]

2. Description of the Related Art When storing a plurality of bytes of integer data in a memory, there are several methods for storing each byte data in the memory. As a storage method for these
What is called little endian and what is called big endian are widely used.

Of these, the one called "little endian" is the least significant byte of data consisting of multiple bytes.
The data is stored in order from the youngest address, and the data is stored in order from the lowest address. On the other hand, what is called big endian is stored in order from the most significant byte data, and from a young address.

When a plurality of bytes of data are conventionally accessed, the data order stored in the memory is different from the storage order of the data stored in the memory, and the data order is converted by software. There was a need.

For example, a processor designed on the assumption that data is stored in little endian is a big endian
When reading the 2-byte word data stored in, the byte data originally read in the lower byte is stored in the upper byte, and the byte data that should be stored in the upper byte is stored in the lower byte. Become. Therefore, it is necessary to change the byte order before using this data. Similarly, when writing, the byte order must be changed before writing to memory. These conversion operations must be done in software. Even if the processor has an instruction to convert the byte sequence of the read data, the instruction must be explicitly executed by software.

The tightly coupled shared memory system shown in FIG. 2 will be taken as an example. This system little end the data in memory
processr to access as stored in ian
o (1) (eg DEC VAX series, Inte
l company's 86 series, etc.) and a processor (2) that accesses as stored as big endian (for example,
Motorola 68000 series, SUN SPARC processor, etc.), shared memory (3) accessed by these processors, and a data bus (4) connecting them. Here, when the data written by the little endian processor is read by the big endian processor, software had to first convert the byte sequence and then handle it.

When accessing data with different endians in a distributed environment using a conventional network, the data size is specified for each access by the basic software, the byte sequence is converted as necessary, and then the data is applied to the application.・ It is passed to the software. Even in this case, if the byte arrangement needs to be converted, the conversion is performed by software.

In processors such as R4000 manufactured by MIPS and M88000 manufactured by Motorola, little endian and big endian can be switched by rewriting the value of the internal register. By rewriting the value of this register, the sequence of all subsequent memory accesses is converted. Here, memory access is classified into one for instruction codes and one for data. However, when the arrangement of memory accesses is converted in these processors, the arrangement of data in the access of instruction codes is also converted. Here, the instruction code to access little endian data must be little endian, so instruction codes with different data sequences must be mixed in one program code.
Therefore, the generation of program code becomes complicated. The problem of complicated program code generation can be solved by fixing the byte sequence of the program code and converting only the data sequence of the memory access to the data. Every time the data having a different arrangement is accessed, the data of the data and an instruction for converting the arrangement of the data (writing instruction to the internal register) must be inserted.

Next, conversion of floating point data will be described as an example.
Similar to the data arrangement, several methods are used as a data format, that is, a bit representation method of a floating point value. For example, the IEEE standard format, the IBM format, the DEC format and the like are widely used. Conventionally, when accessing these data, the program must be aware of the format of the target data, and if necessary, explicitly convert the data format by including a conversion instruction in the program. did not become.

[0010]

As described above, when a conventional processor or the like attempts to access data in a byte arrangement different from the byte arrangement assumed by the processor, the data arrangement is taken into consideration. It was necessary to access while paying attention to the arrangement of the data, such as changing the arrangement of the data by software or inserting an instruction to convert the byte arrangement when accessing the memory.

Also in the case of floating point data, it is necessary to convert the format by software, if necessary, in consideration of which format the accessed data is.

The present invention has been made in view of the above points, and an object of the present invention is to provide a data conversion device capable of automatically converting byte arrangement or data format at the time of memory access.

[0013]

A data conversion apparatus according to the present invention connects a data bus and a processor, and a data converter for data of an address
Means for knowing the arrangement order on the bus and means for converting the arrangement order of the data on the data bus according to the arrangement order and supplying the data to the processor are provided.

The present invention further comprises means for storing the arrangement order on the data bus of each corresponding page in each entry of the page table in the address translation device as means for knowing the arrangement order. .

A data conversion device according to another invention of the present invention is a data conversion device which operates in accordance with a signal supplied from a data bus which indicates an arrangement order of data on the data bus.
A means for converting the arrangement order of the data on the bus and supplying it to the processor is provided.

[0016]

According to the present invention, it becomes possible to know the data arrangement order from the data address at the time of data access. When it is found that the arrangement order of the data needs to be changed by this information, the arrangement order of the data is changed by using the means for changing the arrangement order.

Further, according to the present invention, by storing the arrangement order of the data of each page in each page table entry in the address translation device, the page table is pulled by the access address at the time of data access, It is possible to obtain information indicating this ordering of the corresponding page table entries. Thereby, the arrangement order of the data is changed as necessary.

Further, according to the present invention, a signal indicating the data arrangement order is supplied from the data bus together with the data when the data is accessed. Then, according to the data arrangement information indicated by this signal, the arrangement order of the data is changed as necessary.

[0019]

FIG. 1 shows the configuration of a data converter according to a first embodiment of the present invention. This is little endian or bi
32 bit system data bus (5), (6), (7), (8) and 32 bit where gendian data appears
The processor data buses (10), (11), (12) and (13) which are the data buses of the processor (9) are connected to each other. System data bus (5-
Reference numeral 8) corresponds to the system bus 4 in FIG. 2, and is connected with other processors, I / O devices, data input / output devices such as memories. The processor (9) accesses (reads / writes) other data input / output devices via these data buses.

In this example, the short word (2by
te) and word (4 byte) data are aligned with the respective word boundaries. I mean short
It is assumed that the lowest 1 bit of the address of the word data is 0 and the lowest 2 bits of the address of the word data is 0.

8 32-bit system data bus
Each bit is divided into four groups. Below, B0 (5) from 0th bit to 7th bit, B1 (6) from 8th bit to 15th bit, and B2 from 16th bit to 23th bit.
(7), the 24th bit to the 31st bit are called B3 (8), respectively. As shown in FIG. 3, the byte data is the least significant 2 bits of the address, and the least significant 2 bits of the address are in binary notation 00, 01, 10 and 11 in the byte data B0, B1, B2 and B3, respectively. Each appears.

Similarly, 32 bits of processor data
The buses are also divided into 4 groups every 8 bits. 0 from the bottom
P0 (10) from the 7th bit to P1 (11) from the 8th bit to 15th bit, and 23 from the 16th bit
Bit 2 is P2 (12), 24 bits to 31 bits
The eyes are called P3 (13), respectively. Signals appear on this processor data bus in the bit order used within the processor. That is, P0 and P in order from the least significant byte
Appears at 1, P2, P3.

In FIG. 1, the page table (14)
Stores 1-bit information indicating whether the data arrangement of the currently accessed data address is little endian or big endian, in addition to the information for normal address translation / data protection, etc. A signal indicating this data sequence corresponding to the page being output is output. Each page table entry of this page table contains, in addition to the physical page number of the normal corresponding page (15), some flag bits (16) for storing access protection information, etc. Endian bit (1 indicating whether page data appears as big endian or little endian on the system data bus
Have 7). When accessing data, the corresponding page
The value of the endian bit is output as the endian signal (18).

In FIG. 1, the data size signal size
(19) is a signal output by the processor, and the data access size at the time of data access is byte (8
bit), short word (16 bits), or word (32 bits). Similarly, the address signal adrs [1: 0] (20) is also a signal output by the processor and indicates the lowest 2 bits of the data address at the time of data access.

In FIG. 1, (21) indicates a system data bus and a processor data bus according to the values of the endian signal, the data size signal size, and the address signal adrs [1: 0] which are the input control signals. Is a data selection device for converting byte sequences and connecting them (FIG. 4).

In this data selection device, four sets of 8 bi
t signal selection device (22), (23), (24), (2
There is 5). These are control signals C0 corresponding to the respective
(26), C1 (27), C2 (28), C3 (29)
Either 2 or 4 sets of 8 bit signals on the system data bus side and 8b on the processor side according to the value of
Connect the it signal. For example, when the internal control signal C2 is 0, the processor data bus P2 and the system data bus B1 are connected. Similarly, when the internal control signal C2 is 1, the processor data bus P2 and system
Connect to B2 of data bus.

When the processor (9) is little endian, the input control signal, endian signal,
Data size signal size, address signal adrs
Each value of [1: 0] and internal control signals C0, C
The correspondence with 1, C2 and C3 is shown in FIG. The figure also shows how the processor data bus and the system data bus are connected according to internal control signals generated according to these input control signals. For a selection device connected to a processor that accesses big endian, perform the operation shown in the lower part of the table when the endian signal is little and the operation shown in the upper part of the table when the endian signal is big. become. The operation at the time of data access of this embodiment will be described below. The operation flow is shown in FIG.

First, the processor (9) outputs the logical address of the data to be accessed (S1). The entry corresponding to the memory page including this logical address is selected from the page table (14) (S2). In this page table, information (17) indicating the byte order of the page is stored in advance together with the physical address (15) and protection information (16) of the page. When accessing the memory, this selected page table
Information indicating the entry byte sequence is the endian signal (18)
Is output as (S3).

Also, siz indicates the data size of the data access together with the address from the processor (9).
The e signal (19) is also output. This size (19) signal, the previous endian signal (18), and the lower 2 bits of the address signal
(20) is given to the selection device. From these signals, the selector selects the internal control signals C0 (26), C1 (27), C2.
(28) and C3 (29) are generated and given to the four sets of 8-bit signal selection devices (22), (23), (24) and (25) (S4, S5). This allows system data
The buses (5), (6), (7) and (8) and the processor data buses (10), (11), (12) and (13) are connected with their byte sequences appropriately converted ( S6). That is, for processors that access as if the data is stored in little endian, little endia
The data converted to n is supplied, and the processor converted as big endian is supplied with the data converted to big endian.

Further, as can be seen from FIG.
Since endian is converted for data and short word data, but not for byte data, even if numeric data and character data are mixed, endian is converted for numeric data (word) and character The operation of not converting data (bytes) can be realized without using software.

Next, FIG. 7 shows a second embodiment of the present invention.
This is also a little endian or big as in the previous embodiment.
It connects the 32-bit system data bus where the endian data appears and the 33-bit processor data bus, and the data input / output device 31 is connected to the system data bus.

In this system, the system data bus is provided with a signal line (30) indicating a data arrangement, and the data input / output device is provided with a signal line drive section 32. Also, it is assumed that data is normally provided on this system data bus in little endian. The signal (30) indicating the data arrangement is pulled up to the high level. Leave this signal high for littl endian data to be output on this system data bus. On the other hand, a device (processor, I / O device, memory, etc.) that outputs data in big endian uses the signal line driver 32 to pull down this signal (30) to a low level when outputting data. When little endeian and big endian data are mixed in one data input / output device, it is determined which endian the signal line driving unit is based on the data storage position or the like. As a result, the device that inputs data from the bus can appropriately convert the byte order of the data by supplying this signal to the selection device (21) described above.

In the above embodiment, if the signal indicating that the current data access is an access to floating point data is output from the processor to the selecting device, the floating point format is converted by the same means. Can be converted. For example, in the first embodiment, the page
Instead of storing the information on the byte arrangement of the table, the information indicating the type of the floating point format (the number of digits of each of the mantissa part and exponent part) is stored, and the selection device accesses the floating point data according to this format information Sometimes it does a format conversion. This makes it possible to properly convert the data format of floating point data.

[0034]

As described above, according to the present invention, even when attempting to access data having a byte arrangement different from the byte arrangement assumed by the processor such as a conventional processor, conversion of the byte arrangement is automatically performed at the time of access. Will be performed. As a result, it becomes unnecessary to change the data arrangement by software and to insert an instruction for converting the byte arrangement at the time of memory access as in the conventional case.

Similarly, in the case of floating point data,
It becomes unnecessary to convert the format by software when necessary, considering which format the data to access is.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a data conversion device according to a first embodiment of the present invention.

[Fig. 2] Configuration diagram of the tightly coupled shared memory system

[Fig. 3] Data on external Data Bus and lowest 2 of address
Diagram showing the correspondence with bits

FIG. 4 is a block diagram of the selection device of FIG.

5 is a diagram showing the operation of the selection device of FIG.

FIG. 6 is a flow chart showing the operation of the first embodiment device.

FIG. 7 is a configuration diagram of a data conversion device according to a second embodiment of the present invention.

[Explanation of symbols]

1 little endian processor 2 big endian processor 3 shared memory 4 system data bus 5 system data bus (0-7 bits) 6 system data bus (8-15 bits) 7 system data bus (16- 23 bit) 8 system data bus (24-31 bit) 9 processor 10 processor data bus (0-7 bit) 11 processor data bus (8-15 bit) 12 processor data bus (16-23 bit) 13 processor Data bus (24-31 bits) 14 page table 15 physical page number 16 flags such as access protection information 17 endian bit 18 endian signal 19 data size signal 20 address signal 21 data selection device 22, 23, 24, 258 bit Signal selection equipment 26, 27, 28, 29 8bit signal control signal 30 signal 31 data input-output device 32 a signal line drive unit 33 data storage unit representing the data arrangement of the selection device

Claims (3)

[Claims] 1. A data conversion device for connecting a data bus and a processor, and means for knowing the arrangement order or format type of the data of the address on the data bus by the address, and the arrangement order or format.
And a means for converting the arrangement order of data on the data bus or the format according to the type of mat and supplying the converted format to the processor. 2. The data conversion device according to claim 1, further comprising means for managing an address of data accessed by the processor, and data of each page corresponding to each entry of the page table for performing this management. A data conversion device characterized in that information indicating the arrangement order or the type of format on the bus is stored in advance and the arrangement order or the type of format is known by referring to this information. 3. A data converter for connecting a data bus and a processor, wherein the data bus is provided with a signal line indicating an arrangement order of data on the data bus or a type of format. A data conversion device comprising means for converting the arrangement order of data on the data bus according to a signal supplied and supplying the converted data to a processor.