JPH0673344B2 - Electron beam drawing method - Google Patents
Electron beam drawing methodInfo
- Publication number
- JPH0673344B2 JPH0673344B2 JP62084755A JP8475587A JPH0673344B2 JP H0673344 B2 JPH0673344 B2 JP H0673344B2 JP 62084755 A JP62084755 A JP 62084755A JP 8475587 A JP8475587 A JP 8475587A JP H0673344 B2 JPH0673344 B2 JP H0673344B2
- Authority
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- Japan
- Prior art keywords
- term
- detected
- axis
- alignment
- shift
- Prior art date
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Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
- H01J37/317—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
- H01J37/3174—Particle-beam lithography, e.g. electron beam lithography
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
- H01J37/304—Controlling tubes by information coming from the objects or from the beam, e.g. correction signals
- H01J37/3045—Object or beam position registration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/30—Electron or ion beam tubes for processing objects
- H01J2237/304—Controlling tubes
- H01J2237/30433—System calibration
- H01J2237/30438—Registration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/30—Electron or ion beam tubes for processing objects
- H01J2237/317—Processing objects on a microscale
- H01J2237/3175—Lithography
- H01J2237/31761—Patterning strategy
- H01J2237/31764—Dividing into sub-patterns
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- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Nanotechnology (AREA)
- Analytical Chemistry (AREA)
- Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Electron Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電子線描画方法に係り、特に合わせマーク検出
方法による電子線直接描画に好適な合わせ補正方法に関
する。Description: TECHNICAL FIELD The present invention relates to an electron beam drawing method, and more particularly, to an alignment correction method suitable for electron beam direct drawing by an alignment mark detection method.
電子線直接描画で半導体デバイスを製造する場合、各層
間でのパターン合わせが重要である。When manufacturing a semiconductor device by electron beam direct writing, pattern matching between layers is important.
半導体ウエハー上の多数の半導体デハイスチツプの配列
は、設計段階で正確に決められているので、理論的には
各層毎に該当するチツプの座標に重ね合わせて描画して
いけば良。しかし、現実には電子線描画装置内へのウエ
ハーセツテイングの回転・シフト，プロセス工程に伴う
ウエハーの変形等が有り、特開昭57-20412号公報に記載
されているように、描画に当つてはこれらの情報を把握
し、電子線の偏向系に補正を加えて描画する必要があ
る。The arrangement of many semiconductor dehigh-chips on a semiconductor wafer is accurately determined at the design stage, so theoretically each layer should be drawn by superimposing it on the corresponding chip coordinates. However, in reality, there are rotation / shift of the wafer setting in the electron beam drawing apparatus, deformation of the wafer accompanying the process steps, etc., and as described in JP-A-57-20412, Then, it is necessary to comprehend such information and correct the electron beam deflection system to draw.
すなわち、ウエハーの回転量，シフト量および変形量を
計測するために、半導体デバイスチツプ配列を、合わせ
ブロツクに分割し、合わせブロツクの４隅に設けた合わ
せマークを電子線で検出する。検出された合わせマーク
の座標から、回転・シフト・変形量を算出し、電子線の
偏向補正系に補正を加えて描画する。That is, in order to measure the rotation amount, shift amount, and deformation amount of the wafer, the semiconductor device chip array is divided into alignment blocks, and alignment marks provided at the four corners of the alignment blocks are detected by an electron beam. From the detected coordinates of the alignment mark, the amount of rotation, shift, and deformation is calculated, and the electron beam deflection correction system is corrected to draw.
このときの補正式は第１式で表わされる。The correction equation at this time is represented by the first equation.
第１式において、X,Yはそれぞれ、ブロツク中心からの
座標、ΔY,ΔＹは補正量である。A,B,C,D,A′,B′,C′,
D′は補正係数と呼ばれそれぞれ次に示す様な意味が有
る。 In the first equation, X and Y are coordinates from the block center, and ΔY and ΔY are correction amounts. A, B, C, D, A ′, B ′, C ′,
D'is called a correction coefficient and has the following meanings.
Ａ :X方向のゲイン項 Ｂ :Y軸に関する回転項 Ｃ :Y軸に対称な台形項 Ｄ :X方向のシフト項 Ａ′:X軸に関する回転項 Ｂ′:Y方向のゲイン項 Ｃ′:X軸に対称な台形項 Ｄ′:Y方向のシフト項 これらの補正係数Ａ〜Ｄ′は、次の手順で算出される。
４つの合わせマークはそれぞれブロツクの第１象限、第
２象限，第３象限、第４象限に設定されており、それら
の座標をそれぞれ、(X1，Y1)，(X2，Y2)，(X3，Y3)，(X
4，Y4)で表わす。一方、実際に検出されたブロツクの合
わせマーク位置の検出座標を(x1，y1)，(x2，y2)，
(x3，y3)，(x4，y4)で表わす。A: X-direction gain term B: Y-axis rotation term C: Y-axis symmetric trapezoidal term D: X-direction shift term A ': X-axis rotation term B': Y-direction gain term C ': X Axial symmetric trapezoidal term D ': shift term in Y direction These correction coefficients A to D'are calculated by the following procedure.
The four alignment marks are set in the first quadrant, second quadrant, third quadrant, and fourth quadrant of the block, and their coordinates are (X 1 , Y 1 ), (X 2 , Y 2 ), respectively. , (X 3 , Y 3 ), (X
4 , Y 4 ). On the other hand, the detection coordinates of the alignment mark position of the actually detected block are (x 1 , y 1 ), (x 2 , y 2 ),
Represented by (x 3 , y 3 ), (x 4 , y 4 ).
設計上のマーク座標(Xi，Yi)と実際に検出されたマーク
座標(xi，yi)の間に補正式（第１式）を当てはめ、次の
式を得る。A correction equation (first equation) is applied between the designed mark coordinate (X i , Y i ) and the actually detected mark coordinate (x i , y i ) to obtain the following equation.
これら８ケの式より、８ケの未知数Ａ〜Ｄ′を最小二乗
法で計算し求める。上記手順を各合わせブロツク毎に実
施し、高精度な層間合わせを実現する。 From these eight equations, eight unknowns A to D'are calculated and obtained by the least square method. The above procedure is performed for each alignment block to achieve highly accurate interlayer alignment.
一般的には、上記の如く、合わせブロツクの４隅の合わ
せマークを検出して補正係数を求め、合わせ描画を実施
するわけであるが、実際に応用した場合、合わせマーク
の崩れ等の理由で、４隅の合わせマークのうちのいくつ
かが検出されないことがある。第２式から判かる様に、
４つの合わせマークのうち１つでも検出エラーが発生す
ると、８つの未知数である補正係数Ａ〜Ｄ′を算出する
ことは不可能である。従来は、この様にマークエラーが
発生した場合は、該当するブロツクの描画をしないでシ
フトブロツクに進むか、又は、直前のブロツクの補正係
数を用いて描画していた。Generally, as described above, the alignment marks at the four corners of the alignment block are detected and the correction coefficient is calculated to perform the alignment drawing. However, in the actual application, the alignment marks may be broken or the like. Some of the four corner alignment marks may not be detected. As you can see from the second formula,
If even one of the four alignment marks has a detection error, it is impossible to calculate the eight unknown correction coefficients A to D '. Conventionally, when such a mark error occurs, the corresponding block is not drawn and the shift block is moved to, or the correction coefficient of the immediately preceding block is used for drawing.
上記従来技術は、合わせマークの検出エラーが発生した
場合、単純に該当ブロツクの描画をスキツプするか、直
前ブロツクの補正係数を用いるかの手段しか講じておら
ず、前者の場合は、ウエハー全体から完成品としてとれ
る半導体デバイスチツプの歩留を低下せしめる問題があ
り、後者の場合は、正確な合わせ精度を実現し得ない問
題があつた。In the above-mentioned conventional technique, when a registration mark detection error occurs, only the means of simply skipping the drawing of the corresponding block or using the correction coefficient of the immediately preceding block is taken. There is a problem that the yield of semiconductor device chips that can be obtained as a finished product is reduced, and in the latter case, there is a problem that accurate alignment accuracy cannot be realized.
本発明の目的は、合わせマーク検出エラーが発生した場
合にも、高精度な合わせを実現する方法を提供すること
にある。An object of the present invention is to provide a method for realizing highly accurate alignment even when an alignment mark detection error occurs.
半導体デバイスは、一般に十数回のプロセス工程を経て
形成される。各工程毎にウエハーをカセツトに保持し、
描画装置内に入れて前の工程で形成されたパターンに精
度良く重ね合わせ描画していく。このとき、カセツトの
加工精度のバラツキウエハーセツテイングのバラツキ等
により、装置の基本座標系に対して回転，シフトを生じ
る。この回転，シフト量を計測し、描画座標系を補正し
て描画する必要がある。このときの補正式は、下記のよ
うになる。Semiconductor devices are generally formed through a dozen or more process steps. Hold the wafer in the cassette for each process,
It is put in the drawing apparatus and the pattern formed in the previous step is accurately superimposed and drawn. At this time, due to variations in the processing accuracy of the cassette, variations in the wafer setting, etc., rotation and shift occur with respect to the basic coordinate system of the apparatus. It is necessary to measure the amount of rotation and shift and correct the drawing coordinate system to draw. The correction formula at this time is as follows.
但し、ウエハーの単純回転では座標変換の理論から、
Ａ′＝−Ｂであり、ウエハー全面との場所においても同
一の値である（ウエハーの変形，歪みを考えない場
合）。シフト量D,D′はチツプ毎（ブロツク毎）に変わ
るため、各チツプ毎に求める必要がある。 However, in the simple rotation of the wafer, from the theory of coordinate conversion,
A ′ = − B, which is the same value at the place on the entire surface of the wafer (when the deformation and distortion of the wafer are not considered). Since the shift amounts D and D'change for each chip (for each block), it is necessary to obtain it for each chip.
回転量は、カセツトの加工精度等により、ウエハーのセ
ツテイング毎、カセツト毎に異なるが、最大量としては
1mmに対して１μｍ程度であり、補正しない限り0.1μｍ
以下の合わせ精度は期待できない。シフト量は、ウエハ
ーの左右両側に設けられたウエハーマークの検出座標か
ら個々のチツプ（ブロツク）の中心座標をウエハーの回
転を考慮し計算するため、最大0.1μｍ程度であるが、
個々のチツプ（ブロツク）について正確に計測し補正し
ないと、0.1μｍ以下の合わせ精度は期待できない。The amount of rotation differs for each wafer setting and each cassette depending on the processing accuracy of the cassette, etc., but the maximum amount is
About 1 μm for 1 mm, 0.1 μm unless corrected
The following alignment accuracy cannot be expected. The shift amount is about 0.1 μm at maximum because the center coordinates of individual chips (blocks) are calculated in consideration of the rotation of the wafer from the detected coordinates of the wafer marks provided on the left and right sides of the wafer.
Unless each chip (block) is accurately measured and corrected, alignment accuracy of 0.1 µm or less cannot be expected.
また、回転，シフト以外に、プロセスを経ることによる
ウエハーの変形に起因するチツプ（ブロツク）の変形に
対して補正する必要がある。これは、X,Y方向のチツプ
の伸び縮み、ひし形変形，台形変形として現われるが、
一般にこれらの量は少なくて、ひし形変形，台形変形は
共に1mmに対して0.02μｍ以下、伸び縮みは1mmに対して
0.1μｍ以下である。伸び縮みは、一般にX,Y方向に等方
的である。ウエハーの変形に起因する補正項は、量的に
小さく、高精度の重ね合わせを要求される場合は省略で
きないが、粗い補正で良い場合には無視し得る。In addition to rotation and shift, it is necessary to correct for chip (block) deformation due to wafer deformation due to the process. This appears as expansion and contraction of the chip in the X and Y directions, rhombus deformation, and trapezoidal deformation.
Generally, these amounts are small, both rhombic and trapezoidal deformations are 0.02μm or less for 1mm, and expansion and contraction for 1mm
It is 0.1 μm or less. The expansion / contraction is generally isotropic in the X and Y directions. The correction term due to the deformation of the wafer is small in quantity and cannot be omitted when high-precision overlay is required, but can be ignored when rough correction is sufficient.
したがって本発明は、２個のマークを検出ミスした場合
は、台形変形とひし形変形を無視し、ウエハーは単純回
転し、かつX,Y方向に等方的に伸び縮みしていると仮定
して補正を行う。Therefore, the present invention ignores trapezoidal deformation and diamond-shaped deformation when two marks are missed, and assumes that the wafer is simply rotated and isotropically expanded and contracted in the X and Y directions. Make a correction.
以下、本発明の実施例を示す。 Examples of the present invention will be shown below.
１）１つの合わせマーク検出エラーが発生した場合 第１図に、４つの合わせマーク7,8,9および10のうち、
第一象限のマーク７がマーク検出エラーで検出できなか
つた場合の実施例を示す。1) When one alignment mark detection error occurs In Fig. 1, of the four alignment marks 7, 8, 9 and 10,
An example in which the mark 7 in the first quadrant cannot be detected due to a mark detection error will be described.
本実施例のように、４つの合わせマークのうちの１つが
検出できなかつた場合の補正式は、第１式の補正式から
台形項を除き次式とする。As in the present embodiment, the correction formula when one of the four alignment marks cannot be detected is the following formula except the trapezoidal term from the correction formula of the first formula.
６つの定数は未知数であり、検出された３つの合わせマ
ーク座標値(xi，yi)（ｉ＝2,3,4）と合わせマーク座標
の設計値(Xi，Yi)（ｉ＝2,3,4）を結びつける６個の式
（第５式）より最小二乗法にて求められる。 The six constants are unknowns, and the three detected alignment mark coordinate values (x i , y i ) (i = 2,3,4) and the alignment mark design values (X i , Y i ) (i = It is obtained by the least-squares method from the six equations (fifth equation) that connect 2,3,4).
（ｉ＝2,3,4） 本実施例では、第１象限のマーク、７が検出されなかつ
た場合について記述したが、他の象限のマークが検出さ
れなかつた場合も、検出されたマークの座標について
（５）式を立てることにより、そのブロツクの補正係数
を求めることができる。 (I = 2, 3, 4) In this embodiment, the case where the mark in the first quadrant, 7 is not detected, is described. However, even when the mark in another quadrant is not detected, the detected mark is not detected. By establishing the equation (5) for the coordinates, the correction coefficient for the block can be obtained.
２）２つの合わせマーク検出エラーが発生した場合、 第２図に、４つの合わせマーク、7,8,9および10のう
ち、第１象限と第２象限のマーク7,8がマーク検出エラ
ーで検出できなかつた場合の実施例を示す。2) When two alignment mark detection errors occur, in Fig. 2, among the four alignment marks 7, 8, 9 and 10, the marks 7, 8 in the first and second quadrants are mark detection errors. An example in the case of failure in detection will be shown.
本実施例のように、４つの合わせマークのうちの２つが
検出できなかつた場合の補正式は、第４式の補正式にお
いて、Ｘ方向のゲイン項とＹ方向のゲイン項は等しく
（Ａ＝Ｂ′）、さらに回転項はX,Y軸に関し単純に回転
している（Ａ′＝−Ｂ）と仮定し、第６式の補正式を立
てる。As in the present embodiment, the correction equation when two of the four alignment marks cannot be detected is the same as the correction equation of the fourth equation, where the gain term in the X direction and the gain term in the Y direction are equal (A = B '), and assuming that the rotation term is simply rotating about the X and Y axes (A' =-B), the correction equation of the sixth equation is established.
４つの未知数である補正係数A,B,D,D′は検出された２
つの合わせマーク座標(xi，yi)（ｉ＝3,4）と、合わせ
マーク座標の設計値(Xi，Yi)（ｉ＝3,4）を結びつける
４個の式（第７式）より、最小二乗法にて求められる。 The four unknowns, correction factors A, B, D and D ', were detected 2
Four formulas (7th formula) for connecting one alignment mark coordinate (x i , y i ) (i = 3,4) and the design value (X i , Y i ) of the alignment mark coordinate (i = 3,4) ), The least squares method is used.
（ｉ＝3,4） 本実施例では、第１象限および第２象限の合わせマーク
7,8が検出されなかつた場合について記述したが、他の
象限のマークが検出されなかつた場合も、検出された２
つのマーク座標について第６式を立てることにより、そ
のブロツクの補正係数を求めることができる。 (I = 3,4) In the present embodiment, the alignment marks in the first and second quadrants
Although the case where 7,8 was not detected was described, it was detected even when the marks in other quadrants were not detected.
The correction coefficient for the block can be obtained by establishing the sixth equation for one mark coordinate.
３）３つの合わせマーク検出エラーが発生した場合、 第３図に、４つの合わせマーク、7,8,9および10のう
ち、第１象限，第２象限および第３象限のマーク、7,8,
9かマーク検出エラーで検出できなかつた場合の実施例
を示す。3) When three alignment mark detection errors occur, in FIG. 3, among the four alignment marks, 7, 8, 9 and 10, quadrants 1, 2 and 3 quadrants, 7, 8 ,
An example will be shown in the case where detection cannot be performed due to 9 or mark detection error.
本実施例のように、４つの合わせマークのうちの２つが
検出できなかつた場合の補正式は、第８式を用いる。As in the present embodiment, the correction formula when two of the four alignment marks cannot be detected uses the eighth formula.
但し、＊A,＊B,＊C,＊Ａ′，＊Ｂ′，＊Ｃ′は直前のブ
ロツクの補正係数を用いる。未知数は、ＸおよびＹ方向
のシフト項D,D′の２つであり、検出されたマーク座標
(xi，yi)とマーク座標の設計値(Xi，Yi)ｉ＝４から第９
式で求められる。 However, * A, * B, * C, * A ', * B', * C 'use the correction coefficient of the immediately preceding block. The unknowns are two shift terms D and D'in the X and Y directions, and the detected mark coordinates
(x i , y i ) and design value of mark coordinates (X i , Y i ) i = 4 to 9
It is calculated by the formula.
（ｉ＝４） 本実施例は、第４象限のマークのみ検出された場合であ
るが、他の象限のマークが検出された場合も同様であ
る。 (I = 4) In the present embodiment, only the marks in the fourth quadrant are detected, but the same applies when marks in other quadrants are detected.
４）全部のマークが検出エラーに成つた場合 全部のマークが検出エラーに成つた場合は、補正係数の
求めようがないので、そのブロツクを描画しないで進め
るか、直前のブロツクの補正係数を用いて描画する従来
の方法に従う。4) When all marks have a detection error When all the marks have a detection error, it is impossible to find the correction coefficient, so proceed without drawing the block or use the correction coefficient of the immediately previous block. Follow the traditional method of drawing.
本発明によれば、４つのブロックマークのうちの２つの
ブロックマークが検出できないときに、検出された２つ
のブロックマークにより、補正を実施することができる
ので、ウエハー全体における合わせ精度の向上、ひいて
は完成チップの歩留り向上の効果がある。According to the present invention, when two of the four block marks cannot be detected, the correction can be performed by the two detected block marks. Therefore, the alignment accuracy of the entire wafer can be improved, and It has the effect of improving the yield of finished chips.
第１図乃至第３図は本発明の実施例であるマーク検出エ
ラーが発生した場合の補正描画の説明図である。 １……設計上の合わせブロツク外形、2,3,4,5……設計
上の合わせマーク位置、６……検出された合わせブロツ
ク外形、7,8,9,10……検出された合わせマーク位置。FIG. 1 to FIG. 3 are explanatory diagrams of correction drawing when a mark detection error occurs, which is an embodiment of the present invention. 1 …… Designed alignment block outline, 2,3,4,5 …… Designed alignment mark position, 6 …… Detected alignment block outline, 7,8,9,10 …… Detected alignment mark position.
Claims (1)
分割し、このブロック内を複数のチップに分割し、前記
ブロックに４つの合わせマークを設け、検出された合わ
せマークの位置情報に基づいて電子線偏向系に補正を加
えて前記ブロックの描画を行う方法において、前記４つ
の合わせマークが検出されたときに、検出された４つの
マークの位置情報に基づいて、Ｘ方向のゲイン項,Y軸に
関する回転項,Y軸に対称な台形項,X方向のシフト項,X軸
に関する回転項,Y方向のゲイン項,X軸に対称な台形項、
及び、Ｙ方向のシフト項をそれぞれ求め、これにより、
前記電子線偏向系に補正を加え、さらに、前記４つの合
わせマークのうち２つの合わせマークが検出できないと
きは、検出された２つの合わせマークの位置情報に基づ
き、前記Ｘ軸に対称な台形項及び前記Ｙ軸に対称な台形
項を省き、前記Ｘ方向のゲイン項と前記Ｙ方向のゲイン
項は等しいと仮定し、また、前記回転項はX,Y軸に関し
単純に回転していると仮定し、前記Ｘ方向のゲイン項，
前記Ｙ軸に関する回転項，前記Ｘ方向のシフト項，前記
Ｙ方向のゲイン項，前記Ｘ軸に関する回転項及び前記Ｙ
方向のシフト項を求め、これにより、前記電子線偏向系
に補正を加えることを特徴とする電子線描画方法。1. A surface of a semiconductor wafer is divided into a large number of blocks, the inside of this block is divided into a plurality of chips, and four alignment marks are provided in the blocks, and an electronic signal is obtained based on position information of the detected alignment marks. In the method of drawing the block by correcting the line deflection system, when the four alignment marks are detected, the gain term in the X direction and the Y-axis are calculated based on the positional information of the detected four marks. Rotation term about, Y-axis symmetric trapezoidal term, X-direction shift term, X-axis rotation term, Y-direction gain term, X-axis symmetric trapezoidal term,
And the shift terms in the Y direction are obtained, respectively, and
When a correction is applied to the electron beam deflection system and two alignment marks out of the four alignment marks cannot be detected, a trapezoidal term symmetrical to the X axis is based on position information of the detected two alignment marks. And the trapezoidal term symmetrical to the Y axis is omitted, and it is assumed that the gain term in the X direction and the gain term in the Y direction are equal, and the rotation term is simply rotating about the X and Y axes. , The gain term in the X direction,
The rotation term about the Y axis, the shift term in the X direction, the gain term in the Y direction, the rotation term about the X axis, and the Y
An electron beam drawing method, characterized in that a shift term in a direction is obtained and a correction is applied to the electron beam deflection system based on the shift term.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62084755A JPH0673344B2 (en) | 1987-04-08 | 1987-04-08 | Electron beam drawing method |
| EP88105547A EP0286086A3 (en) | 1987-04-08 | 1988-04-07 | Electron beam drawing method |
| US07/178,970 US4853549A (en) | 1987-04-08 | 1988-04-07 | Electron beam drawing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62084755A JPH0673344B2 (en) | 1987-04-08 | 1987-04-08 | Electron beam drawing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63250817A JPS63250817A (en) | 1988-10-18 |
| JPH0673344B2 true JPH0673344B2 (en) | 1994-09-14 |
Family
ID=13839502
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62084755A Expired - Lifetime JPH0673344B2 (en) | 1987-04-08 | 1987-04-08 | Electron beam drawing method |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US4853549A (en) |
| EP (1) | EP0286086A3 (en) |
| JP (1) | JPH0673344B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5422491A (en) * | 1988-11-04 | 1995-06-06 | Fujitsu Limited | Mask and charged particle beam exposure method using the mask |
| JP2702183B2 (en) * | 1988-11-04 | 1998-01-21 | 富士通株式会社 | Semiconductor manufacturing equipment |
| US5345310A (en) * | 1993-06-15 | 1994-09-06 | Lsi Logic Corporation | Identifying and compensating for slip-plane dislocations in photolithographic mask alignment |
| JPH11233397A (en) * | 1998-02-13 | 1999-08-27 | Mitsubishi Electric Corp | Aligning method and semiconductor device |
| CA2311017C (en) * | 1999-06-14 | 2004-07-20 | Canon Kabushiki Kaisha | Recording head, substrate for use of recording head, and recording apparatus |
| JP2004219876A (en) * | 2003-01-17 | 2004-08-05 | Toppan Printing Co Ltd | Correction drawing method in lap drawing |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57204127A (en) * | 1981-06-10 | 1982-12-14 | Hitachi Ltd | Drawing method for pattern of electron-ray drawing device |
| JPS6074619A (en) * | 1983-09-30 | 1985-04-26 | Fujitsu Ltd | Method for exposure by electron beam |
| JPS6233427A (en) * | 1985-08-06 | 1987-02-13 | Fujitsu Ltd | Electron beam exposure method |
-
1987
- 1987-04-08 JP JP62084755A patent/JPH0673344B2/en not_active Expired - Lifetime
-
1988
- 1988-04-07 EP EP88105547A patent/EP0286086A3/en not_active Withdrawn
- 1988-04-07 US US07/178,970 patent/US4853549A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0286086A2 (en) | 1988-10-12 |
| US4853549A (en) | 1989-08-01 |
| JPS63250817A (en) | 1988-10-18 |
| EP0286086A3 (en) | 1990-03-07 |
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