JPH0671048B2 - Wiring structure for repairing semiconductor integrated circuit and wiring method thereof - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an integrated circuit repair for making a logic change by cutting, wiring or the like on a chip after manufacturing a chip of a semiconductor integrated circuit, and particularly, at the time of repair. The present invention relates to a repair wiring structure for a semiconductor integrated circuit and a repair wiring method for facilitating processing and improving the yield of repair integrated circuits.

[Prior Art] In recent years, along with the high integration and miniaturization of semiconductor integrated circuits (hereinafter referred to as LSI), in the development process, some of the wiring in the chip of the LSI is cut or new wiring is performed. It has been reported that the defect location is corrected and the LSI logic is changed in a short period of time.

As such a conventional technique, for example, JP-A-62-22
Japanese Patent Laid-Open No. 9956 describes a method for forming a hole by a laser or a focused ion beam, cutting a wiring, and forming a wiring for connection by a CVD method.

Further, Japanese Patent Application Laid-Open No. 62-298134 discloses a technique in which spare wiring is provided in an LSI and the spare wiring is utilized at the time of logic change to facilitate connection between wirings at the time of repair. There is.

[Problems to be Solved by the Invention] By the way, as shown in FIG. 3, the fine highly integrated wiring has a plurality of wiring pattern layers AL provided on an insulating substrate 65.
It has a multilayer structure consisting of 1, AL2 and AL3. For example, since the wiring patterns 66 and 64 belonging to the uppermost layer AL3 are close to each other as shown in FIG. There is a risk of cutting. Further, as shown in FIG. 6B, when the wiring pattern 69 of the wiring pattern layer AL2 is cut at a part 62 thereof, the wiring patterns 63 and 61 belonging to the wiring pattern layer AL3, which is the upper layer, are close to each other. On the other hand, there is a possibility that part or all of the wiring pattern 61 may be cut. Thus, the possibility of cutting a wiring pattern other than the intended wiring pattern lowers the reliability of the repaired LSI.

Further, when forming a new wiring pattern for repair, as shown in FIG. 3 (c), a part of the surface of the wiring pattern 72 for the purpose of connecting the new wiring pattern 70 is Need to be exposed. At that time, there is a possibility that a part of the adjacent wiring patterns 71 adjacent to each other is exposed at the same time. In that case, when the wiring pattern 70 is formed, the wiring patterns 71 and 72 are short-circuited. Similarly, in order to connect a new wiring pattern 60 to the wiring pattern 69 of the lower layer AL2, as shown in FIG.
When exposing a part of the wiring pattern 69, a part of the wiring pattern 68 in the upper layer may be cut off. Also in this case, when the wiring pattern 60 is formed, the wiring patterns 68 and 69 may be short-circuited. Such a short circuit causes malfunction of the repaired LSI.

When cutting or connecting a miniaturized wiring pattern, high processing accuracy is required in order to prevent inconveniences such as cutting of the wiring pattern other than the above-mentioned purpose and short circuit. An expensive repair device such as a high precision ion beam device is required.

Moreover, even with such a high-precision device, it is difficult to process multilayer wiring and fine high-concentration wiring.
There was a problem that the yield of I also decreased.

An object of the present invention is to provide a repair wiring structure and a repair wiring method for a semiconductor integrated circuit, which can improve the yield of repaired LSIs.

Another object of the present invention is to provide a repair wiring structure and a repair wiring method for a semiconductor integrated circuit, which can alleviate the requirements for the positioning accuracy and processing accuracy of the repair device.

[Means for Solving the Problems] A repair wiring structure for a semiconductor integrated circuit according to the present invention is such that, with respect to a specific wiring pattern, a part of the wiring pattern adjacent to the specific wiring pattern is provided with both wiring patterns. It is characterized in that a detour portion for expanding the interval is provided.

The bypass portion of the adjacent wiring pattern is provided in the same layer as the adjacent wiring pattern, or the bypass portion of the adjacent wiring pattern is provided in a different layer from the adjacent wiring pattern via a through hole. be able to. When they are provided in different layers, it is desirable that they are provided above the adjacent wiring pattern layers.

According to another aspect, a repair wiring structure for a semiconductor integrated circuit according to the present invention is a repair wiring structure in which, for two adjacent wiring patterns that are substantially parallel to each other, a part of both wiring patterns is expanded with an interval between the wiring patterns. An area is provided, and the repair area is provided for repair by changing the wiring after the chip is manufactured.

Further, a repair wiring method for a semiconductor integrated circuit according to the present invention is a repair wiring method for creating a wiring pattern to be used for repairing a semiconductor integrated circuit after the chip is manufactured. And then
Paying attention to the wiring pattern that can be repaired, it is checked whether or not there is a portion where the distance between the wiring pattern and the wiring pattern adjacent to the wiring pattern is wider than a predetermined distance. If the determination is negative, the route of the adjacent wiring pattern is changed to provide a detour portion that makes the distance from the focused wiring pattern larger than the predetermined distance.

More specifically, the repair wiring method for a semiconductor integrated circuit according to the present invention is a repair wiring method for creating a wiring pattern used for repair after manufacturing a chip of a semiconductor integrated circuit,
a) Perform wiring that does not consider the spacing between adjacent wiring patterns,
b) Register the wiring pattern that can be the target of repair, and c)
With respect to each of the registered wiring patterns, a wiring pattern adjacent to the wiring pattern is searched, and d) there is a portion in which the distance between the wiring patterns adjacent to each other is wider than a predetermined distance. E) If the result of the check is affirmative, the relevant part is registered as a repair area, and f) If the result of the check is negative, an appropriate part is registered. In the step (3), by changing the route of the adjacent wiring pattern, a detour portion having a distance from the focused wiring pattern larger than the predetermined distance is provided, and the portion is registered as a repair area, g) the step It is characterized in that steps c) to f) are repeated for all the registered wiring patterns.

The check in step d) is performed, for example, for one of the registered wiring patterns, sequentially from one end to the other end of the wiring pattern for each unit length for each location.

After the steps e) and f) and / or after the step g), the registration result of the repair area may be output to an output device. For example, it is conceivable to display a list on a display device or a printer, or to display a graphic on a graphic display device or an XY plotter.

As the adjacent wiring pattern to be checked,
Not only for the wiring pattern in the same layer as the focused wiring pattern, but also for the wiring pattern above the layer,
The wiring pattern of the upper layer can be projected onto the layer and taken into consideration.

The detour section is preferably provided in the same layer as the adjacent wiring pattern or in an upper layer.

In this specification, “wiring” means the actual LS.
It is not the act of forming conductors in I, but the decision of the layout of the wiring pattern in the LSI by design.

[Operation] According to the present invention, a repair area is positively provided in advance in each part of the LSI where repair may be required after the LSI is manufactured, and adjacent wiring pattern intervals are set within the repair area. Provide a part that is larger than the gap. At the time of repair, the existing wiring is cut and a new wiring is formed in any one of the repair areas.

That is, when cutting the existing wiring, the distance between adjacent wiring patterns in the repair area of the target wiring pattern is set to a predetermined interval or more,
If the cutting is performed within the repair area, there is no risk of cutting the adjacent wiring pattern due to lack of processing accuracy.

In addition, when forming a new wiring pattern, similarly, if the wiring pattern is formed in a portion within the repair area of the target wiring pattern, a short circuit to an adjacent pattern may be caused due to insufficient positioning and processing accuracy. Also disappears.

Preferably, if the repair area is provided between all terminals, between terminals and branch points, and between branch points and branch points, any logical change can be dealt with. The branch point is a point where three or more wiring patterns are derived from one point.

As described above, according to the present invention, highly reliable repair can be performed without requiring excessive alignment and processing accuracy. Therefore, the yield of repair LSIs can be improved without using an ultrahigh-precision repair device.
Of course, the present invention does not prohibit the use of an ultra-high-precision repairing device, and it is easily understood that repairing a finer and more complicated multilayer wiring pattern is possible by using such a device. See.

In addition, as a method of cutting and forming the wiring pattern,
Known methods such as those disclosed in JP-A Nos. 62-229956 and 62-298134 can be used.

[Embodiment] An embodiment of the present invention using a logic LSI as an example will be described below in detail with reference to the drawings.

FIG. 1 shows a schematic structure of a part of one wiring layer inside an LSI having multi-layered wiring. Within the LSI, there are areas (called cells) A to F in units of logic circuits such as logic gates,
Each cell is provided with terminals 1 to 7 for connection with other cells or the like.

In this example, the cells A, B, and C are in a logical connection relationship before the repair, and the respective terminals 1 to 3 are connected to each other. That is, the terminals 1 are sequentially connected to the wiring pattern.
31, through hole 11, wiring pattern 32, through hole 12
And the terminal 2 through the wiring pattern 33, and the terminal 2 is sequentially connected to the terminal 3 through the wiring pattern 33, the through hole 12, the wiring pattern 34, the through hole 13, and the wiring pattern 35.

On the other hand, the cells D, E, and F also have a logical connection relationship, and their terminals 4 to 6 are connected to each other. That is, the terminal 4 is sequentially connected to the terminal 5 via the wiring pattern 36, the through hole 14, the wiring pattern 37, the through hole 15, and the wiring pattern 39, and the terminal 5 is sequentially connected to the wiring pattern 3
9, through hole 15, wiring pattern 40, through hole 1
6, wiring pattern 41, through hole 17, wiring pattern 4
2, through hole 18, wiring pattern 43, through hole 1
9, the wiring pattern 44, the through hole 20, and the wiring pattern 45 are connected to the terminal 6.

In this embodiment, the repair area 101 is provided between the through holes 11 and 12 and between the through holes 14 and 15, and the through hole 1
Repair area 102 between 2 and 13 and between through holes 15 and 20
Is provided. In this case, the through holes 12 and 15 form branch points of the wiring pattern. If possible, it is preferable to provide a repair area between the terminal 2 and the through hole 12 and between the terminal 5 and the through hole 15 as a repair area between the terminal and the branch point.

In the repair area 101, a portion of the wiring pattern 37 between the through holes 14 and 15 is provided with a curved portion or a detour portion 38 that deviates from the straight line connecting both through holes in the same layer, and with the adjacent wiring pattern 32. The interval is expanded.
The expanded width is set to a width that does not hinder the adjacent wiring pattern due to processing associated with repair such as cutting and forming of the wiring pattern. This width also changes depending on the processing accuracy of the repair device used.

In the repair area 102, the bypass portion 46 is provided in the wiring pattern between the through holes 15 and 20. However, unlike the detour section 38, the wiring patterns 41 to 43 forming the detour circuit 46 are provided in other wiring pattern layers by utilizing the through holes 16 to 19. The wiring patterns 41 to 43 do not necessarily have to be provided in the same layer, and at least the wiring pattern 42
Is preferably provided in a layer above the layer shown in FIG.
As shown in FIG. 3, generally, in even-numbered layers and odd-numbered layers of the wiring pattern layers, the running directions of the wiring patterns intersect, and between wiring patterns that can be used for new wiring. Gaps (channels) often run in that direction. Therefore, as an example, if the layer shown in FIG. 1 is the AL1 layer, the wiring patterns 41 and 43 may be provided in the AL2 layer and the wiring pattern 42 may be provided in the AL3 layer.

If the wiring pattern of the detour portion is provided in the same layer as in the repair area 101, the number of through holes can be reduced. On the other hand, if the wiring pattern of the bypass is provided in the upper layer like the repair area 102, the number of through holes increases, but for example, when the wiring pattern between the terminals 5 and 6 needs to be repaired, There is an advantage that processing can be performed in a higher layer. If the wiring pattern 46 is provided in the uppermost layer, it is not necessary to consider the wiring pattern in the upper layer when cutting the wiring pattern, and since the processing can be performed with a shallow hole, the processing is facilitated and the processing defects can be reduced.

In FIG. 1, it is assumed that the terminal 2 of the cell B needs to be reconnected to the terminal 7 of the cell F instead of the terminal 3 of the cell C. In this case, first, the wiring pattern 34 is cut at the "X" portion in the repair area 102 by a conventional method using a laser, a focused ion beam, or the like. At this time, as shown in FIG. 1, since there is a sufficient distance from the adjacent wiring pattern, it is possible to avoid a situation in which the adjacent wiring pattern is cut as in the conventional case. Next, wire from the point on the terminal 2 side of the cut wiring pattern 34 to the terminal 7
Give 50. The wiring 50 is shown as connected by discrete lines in the figure, but this is merely a schematic illustration.

FIG. 2 shows the LSI structure of the present invention in contrast to the conventional case shown in FIG. FIG. 2 is a sectional view of an area for repairing an LSI according to the present invention. As can be seen in comparison with FIG. 3 (a), in FIG. 2 (a), the interval between the adjacent wiring patterns 64 and 66 of the AL3 layer is expanded, so that wiring accuracy is not required and wiring is performed. Only the pattern 66 can be cut properly. Similarly, in the case of FIG. 2B, since the wiring pattern 61 is separated from the adjacent wiring pattern 63 by a predetermined distance or more, even when the lower layer wiring pattern 62 is cut, the wiring pattern of the upper layer is obtained even with normal processing accuracy. Does not damage either 61 or 63. In the case of FIG. 2 (c),
Since the wiring pattern 71 is separated from the wiring pattern 72 by a predetermined distance or more as compared with the case of FIG. 3C, the possibility that the wiring patterns 71 and 72 adjacent in the same layer are short-circuited by the wiring pattern 70 is reduced. . Similarly, in the case of FIG. 2 (d), the wiring pattern 68 is separated from the wiring pattern 67 as compared with the case of FIG. 3 (d), so that the wiring pattern between the upper and lower layers is interposed via the wiring pattern 60. The possibility of a short circuit in is reduced.

Next, an example of the creation processing of the repair area as shown in FIG. 1 will be described with reference to the flowchart of FIG.

First, conventional general automatic wiring is performed without considering the repair area (SO). Therefore, all wiring patterns that can be repaired are registered (S1). The unit of this wiring pattern is a wiring pattern between terminals and, if there is a branch, a wiring pattern between terminals and branch points or between branch points and branch points. The wiring pattern to be registered may be specified by designating a specific wiring group having a high logic change frequency, such as a clock signal pattern. Alternatively, it may be performed only for a wiring pattern within a specific range. As a result, it is possible to eliminate the change of the wiring pattern in which the logic change hardly occurs, and to speed up the process of the present invention and improve the wiring efficiency and the wiring density.

Next, an adjacent wiring pattern is searched for and recognized for each wiring pattern thus registered (S2). At this time, as the “adjacent wiring pattern”, it is necessary to consider not only the wiring pattern in the same layer as the wiring pattern but also the wiring pattern in the upper layer. Because the repair is
This is because it is performed from the surface of the LSI as described above. Therefore, when considering whether or not a wiring pattern of a certain layer is "adjacent" to a wiring pattern of another layer, only the layers above that layer need be considered. Some layer, eg AL in the example above
Whether or not the wiring pattern of 1 is adjacent to the wiring pattern of the upper layer, for example, AL3, the wiring pattern of the layer AL3 is set to the layer AL1.
By mapping to, it is possible to judge as a relationship within the same layer. Further, among the wiring patterns in the upper layer, a wiring pattern that intersects the wiring pattern of interest is also considered as an “adjacent wiring pattern”.

Next, it is checked whether or not there is a predetermined predetermined interval between any of the wiring patterns determined to be adjacent to each other in any part of a certain wiring pattern (S
3). For example, the inspection location is shifted by one unit length from one end to the other end of the wiring pattern to inspect the distance from the adjacent wiring pattern. In this case, as described above, the adjacent wiring pattern also includes the wiring pattern of the upper layer. If there is a portion that satisfies the condition of step S3, the area is registered as a repairable area, that is, a repair area (S5).

If there is no location that satisfies the above conditions, at least one new repair area is provided (S4). As this position, it is preferable to select a position that does not need to be changed for the wiring patterns intersecting in the upper layer. That is, a part of the wiring pattern paths that are parallel and adjacent to each other is changed to form the bypass portion. As the mode of the repair area, at least two modes (repair areas 101 and 102) can be considered as shown in FIG. At this time, it is prohibited to change the net of the area already registered as the repair area. The new repair area created in this way is also registered (S5).

Such processing is repeated for all wiring patterns (S6), and when completed, an appropriate output device (not shown),
For example, the wiring pattern is displayed for each layer on the graphic display device or the XY plotter, and the repair area registered on the wiring pattern is displayed. (S7) The output mode of the registration result of the repair area is not limited to such graphic display as long as it can be recognized by the operator, and may be a list display of characters, symbols, or the like.
Thereby, the position of the registered repair area can be confirmed. Further, this display helps determine which part of the wiring pattern should be cut and which part should be laid when repair is required.

Although the process of FIG. 4 can be performed manually, it is preferably performed automatically by a computer program.
In this computer program, each wiring pattern is defined as a connection of coordinate points, and processing such as calculation of an interval with an adjacent pattern and change of a wiring pattern route can be performed by calculation and change of coordinate values.

Although only the preferred embodiments of the present invention have been described above, it will be easily understood by those skilled in the art that various changes and modifications can be made without departing from the gist of the present invention.

[Effects of the Invention] According to the present invention, by providing a repair area in advance as a dedicated place for cutting and connecting a wiring pattern at the time of logic change after LSI change, processing accuracy at the time of LSI repair can be improved. Since the requirement of (3) is relaxed, processing is facilitated and processing defects are reduced, and as a result, the success rate of logic change is increased and the yield of repaired LSI is improved.

[Brief description of drawings]

FIG. 1 is a schematic view of the inside of an LSI to which the present invention is applied, FIG. 2 is a sectional view of a repair LSI according to the present invention, and FIG. 3 is a conventional repair LSI.
FIG. 4 is a flow chart of an embodiment of the repair wiring method of the present invention. 1 to 7 ... terminals, 11 to 20 ... through holes, 31 to 45 ...
Wiring pattern, A to F ... Cell, 101, 102 ... Repair area

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yosuke Nagao, 1 Horiyamashita, Horiyamashita, Hadano City, Kanagawa Prefecture, Kanagawa Plant, Hiritsu Manufacturing Co., Ltd. (56) References JP 61-125045 (JP, A) JP 60 -52040 (JP, A)

Claims (11)

[Claims] 1. A semiconductor integrated circuit for a specific wiring pattern, wherein a part of the wiring pattern adjacent to the specific wiring pattern is provided with a bypass portion for expanding a space between the both wiring patterns. Wiring structure for repair. 2. The repair wiring structure for a semiconductor integrated circuit according to claim 1, wherein the bypass portion of the adjacent wiring pattern is provided in the same layer as the adjacent wiring pattern. 3. The wiring structure for repairing a semiconductor integrated circuit according to claim 1, wherein the bypass portion of the adjacent wiring pattern is provided in a layer different from the adjacent wiring pattern via a through hole. 4. The wiring structure for repairing a semiconductor integrated circuit according to claim 3, wherein the different layer is a layer above the layer of the adjacent wiring pattern. 5. A repair area in which an interval between the two wiring patterns is expanded is provided in a part of both wiring patterns of two adjacent wiring patterns which are substantially parallel to each other, and the repair area is provided after the chip is manufactured. A wiring structure for repair of a semiconductor integrated circuit, which is provided for repair by changing the above. 6. A repair wiring method for creating a wiring pattern to be used for repairing a semiconductor integrated circuit chip after manufacturing, comprising: first performing wiring without considering an interval between adjacent wiring patterns; Pay attention to the wiring pattern
It is checked whether or not there is a portion where the distance between the wiring pattern and the wiring pattern adjacent to the wiring pattern is wider than a predetermined distance. If the result of the check is negative, the adjacent wiring pattern A wiring method for repairing a semiconductor integrated circuit, characterized in that a detour portion is provided by changing a path so that a distance from the focused wiring pattern is larger than the predetermined distance. 7. A repair wiring method for creating a wiring pattern to be used for repairing a semiconductor integrated circuit after chip manufacture, comprising: a) performing wiring without considering a space between adjacent wiring patterns; and b) being a target of repair. Registering a wiring pattern, c) searching for a wiring pattern adjacent to the wiring pattern with respect to each of the registered wiring patterns, and d) determining an interval between adjacent wiring patterns for one of the registered wiring patterns. Check whether there is a part wider than the interval, e) If the result of the check is positive, register the part as a repair area, and f) If the result of the check is negative. In some cases, by changing the route of the adjacent wiring pattern at an appropriate location, the distance from the focused wiring pattern is made larger than the predetermined distance. The detour portion which is provided to register the location as repair area, g) said step c) ~f) the repair wiring method for a semiconductor integrated circuit, characterized in that repeated for all the wiring pattern the registration. 8. The check of step d) is performed for each of the registered wiring patterns, sequentially from one end to the other end of the wiring pattern for each unit length. The wiring method for repairing a semiconductor integrated circuit according to claim 7. 9. The method according to claim 7, wherein after the steps e) and f) and / or after the step g), the registration result of the repair area is output to an output device. Wiring method for repairing semiconductor integrated circuit. 10. The adjacent wiring pattern to be checked is not only the wiring pattern in the same layer as the focused wiring pattern but also the wiring pattern in the upper layer above the wiring pattern in the upper layer. 8. The wiring method for repairing a semiconductor integrated circuit according to claim 6, wherein the wiring is projected on a layer and taken into consideration. 11. The wiring method for repairing a semiconductor integrated circuit according to claim 6, wherein the detour is provided in the same layer as the adjacent wiring pattern or in an upper layer.