JPH066717A - Picture signal processor - Google Patents

Abstract

PURPOSE:To attain picture signal processing for various broadcasting media by a simple constitution by selecting a combination of plural programs within the maximum signal processing capacity range of an arithmetic means based upon the receiving status of image data. CONSTITUTION:A picture signal outputted from a switch 14 is supplied to an image decoder digital signal processor(DSP) 23 and led to also a signal judging circuit 77 for judging the size of a ghost. A CPU 35 selects a combination of plural programs within the maximum signal processing capacity range of the DSP 23 based upon the judging result of the circuit 77. Then a program loader 34 is controlled to load plural programs from a program memory 33 to the DSP 23. Since plural picture signals can be decoded by the single DSP 23, the picture signal processing of various broadcasting media can be attained by the simple constitution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a DSP (digital
The present invention relates to an improvement of an image signal processing device that reproduces an image signal using a signal processor).

[0002]

2. Description of the Related Art As is well known, in recent years, the diversification of broadcasting media has advanced along with the progress of digital technology, and at present, not only television broadcasting of NTSC format using terrestrial VHF and UHF bands but also NTSC broadcasting and high-definition broadcasting using BS (broadcast satellite) have been realized.

Further, in the future, it will be more effective to transmit a signal corresponding to a horizontally long screen by using the existing terrestrial waves and a screen aspect ratio of 16: 9, which corresponds to a horizontally long screen. In order to transmit as many broadcasts as possible with one satellite, digital broadcasting is also planned to be transmitted in a smaller band by digitizing images and performing information compression.

As the broadcasting media have become more diverse in this way, it is naturally required for the television receiver to have a function of receiving the broadcasting of each media. It is also desired to have a function capable of simultaneously receiving media and displaying them on a multi-screen at the same time.

However, in the case of manufacturing a television receiver capable of coping with such diversified broadcasting media, if the receiving circuit corresponding to each broadcasting media is simply provided individually, There is a problem in that it causes an increase in size and is very economically disadvantageous.

[0006]

As described above, in the case of manufacturing a television receiver capable of receiving various broadcasting media, if the circuit for processing the signals is provided for each broadcasting media, the equipment becomes large in size. It has the problem of becoming economically disadvantageous.

Therefore, the present invention has been made in consideration of the above circumstances, and it is possible to realize image signal processing of various broadcasting media with a simple configuration, and it is economically advantageous to obtain a very good image signal. An object is to provide a processing device.

[0008]

An image signal processing apparatus according to the present invention is an arithmetic operation for performing arithmetic processing for decoding input image data based on a signal processing algorithm formed by combining a plurality of programs. Means, a judging means for judging the reception status of the image data given to the calculating means, and a combination of a plurality of programs to be given to the calculating means based on the judgment result of the judging means, the maximum signal processing capacity of the calculating means. And a control means for selecting within a range not exceeding.

[0009]

According to the above construction, the combination of a plurality of programs to be given to the arithmetic means is selected based on the judgment result of the receiving condition of the image data within a range not exceeding the maximum signal processing capacity of the arithmetic means. Therefore, the image signal processing of various broadcasting media can be realized with a simple configuration, which is economically advantageous.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. In Fig. 1, terrestrial VHF
An NTSC format television broadcast signal using the UHF band or the UHF band is received by the antenna 11, demodulated by the VSB / FM demodulator 13 via the tuner IF (intermediate frequency) amplifier 12, and converted into an analog baseband signal. After that, it is output to the switch circuit 14. In this case, the tuner IF amplifier 12 and the VSB / FM demodulator 13 are
A plurality of systems are provided so that a plurality of television broadcasts of the same system or different systems can be simultaneously received and demodulated.

The digital broadcast signal is transmitted to the antenna 11
The pit string (digital sequence) consisting of 1,0 information is received by the tuner IF (intermediate frequency) amplifier 12, and then demodulated by the QAM (amplitude modulation using two orthogonal carriers) demodulator 15. Image data) and output to the switch circuit 14.

Here, an analog baseband signal and digital image data are externally input to the switch circuit 14 via the input terminals 16 and 17, respectively. Then, the switch circuit 14 outputs the signal selected by the user among the four types of input signals described above.

Of these, the analog voice signal is output from the output line 1.
After being converted into digital audio data by an A / D (analog / digital) converter 19 via a signal processing unit 8 and subjected to predetermined data processing by an audio DSP 20, it is taken out from an output terminal 21 and used for audio reproduction.

The analog baseband image signal is
It is input to the video decoder DSP 23 via the output line 22. In this case, the output lines 22 are also provided by the number of a plurality of television broadcasts that can be simultaneously received and demodulated as described above. The video decoder DSP 23 can decode the input number of analog baseband image signals, respectively, which will be described in detail later.

Further, the digital image data is supplied to the error correction circuit 24 and subjected to error correction processing and audio image separation processing. And the digital audio component is
After the voice DSP 20 has performed predetermined data processing,
It is taken out from the output terminal 21 and used for audio reproduction. Further, the digital image component is the variable length code decoding circuit 25.
At, the data rate of the bit stream is converted so as to have a certain amount of data in a certain period and is decoded, and then supplied to the video decoder DSP 23 for decoding processing.

Here, the video decoder DSP 23 is
The input analog baseband image signal is digitized, and the digitized image signal is output line 26.
Is supplied to the synchronous DSP 27 via. This synchronization D
The SP 17 extracts a synchronizing signal portion from the image signal, generates a horizontal synchronizing signal of the image signal and a sample clock signal synchronized with the horizontal synchronizing signal of the image signal from the phase information, and outputs the sample clock signal to the video decoder DSP 23 through the output line 28 and at the same time vertically. In the case of a transmission system using a color subcarrier such as a synchronizing signal or NTSC, the color subcarrier signal is reproduced and output to the video decoder DSP 23 via the output line 29.
The synchronous DSP 27 also generates a clamp control signal for digitally converting the analog baseband image signal input to the video decoder DSP 23 at an appropriate level, and outputs the video signal via the output line 30 to the video decoder DSP 2
It is output to 3.

In the video decoder DSP 23, for example, in the case of the NTSC signal, the luminance signal and the color signal are separated, the color signal is demodulated, the color density and the color tone are adjusted to restore the three primary colors. ing. For other transmission methods, perform signal processing according to each transmission method.
The primary colors are restored. The switching of these signal processing contents is realized by changing the contents of the program executed by the video decoder DSP 23, the details of which will be described later.

Thereafter, the image signal decoded by the video decoder DSP23 is subjected to frame synchronization processing, screen reduction / enlargement processing, fitting processing, etc. in the display DSP31 to be assembled into one screen, and output from the output terminal 32, for example. It is used for image display by a CRT (cathode ray tube) or a liquid crystal display (not shown).

The various programs provided to the video decoder DSP 23 are stored in the program memory 33.
A desired program is read from the program memory 33 by the program loader 34 and supplied to the video decoder DSP 23. Then, the program loader 34 includes a CPU (Central Processing Unit) 35
Controlled via port 36. Also, CP
The U 35 controls switching of the switch circuit 14 via the port 37.

The CPU 35 performs arithmetic processing using a RAM (random access memory) 39 on the basis of a program stored in a ROM (read only memory) 38, so that the image signal processing system. It controls the whole operation. In this case, CPU3
5, operation information from the user is supplied from the input terminal 40 through the port 41.
5 controls the program loader 34 and the switch circuit 14 based on the input operation information.

FIG. 2 shows the above video decoder DSP.
23 shows the internal structure of 23. That is, 421 in the figure
Input terminals 422, ..., 42n are supplied with a plurality of analog baseband image signals transmitted through the output line 22. This plurality of input terminals 42
, 422, ..., 42n are supplied to the clamp base circuits 431, 4 respectively.
After level control by 32, ..., 43n, A /
The signals are digitized by the D converters 441, 442, ..., 44n and supplied to the switch matrix circuit 45.

In this case, each clamp circuit 431, 43
2, ..., 43n are supplied with the clamp control signal output from the synchronous DSP 27 via the input terminal 46, so that the input analog baseband image signal is input to the A / D converter 441 of the next stage. The level is controlled so that it falls within the dynamic range of 442, ..., 44n. Further, each A / D converter 441, 442, ..., 44n is
Based on the sample clock signal output from the synchronous DSP 27 and supplied via the input terminal 47, A / D conversion processing of the analog baseband image signal is executed.

Further, the variable length code decoding circuit 25
The digital image data decrypted at is input terminal 48.
Is supplied to the switch matrix circuit 45 through. Further, each A / D converter 441, 442, ..., 44
digital image data output from n and the input terminal 48
The digital image data supplied to the sync. DSP is sent to the synchronous DSP 27 via the output terminal 49 and used for generating the horizontal sync signal, the vertical sync signal, the clamp control signal, the color subcarrier signal and the sample clock signal.
Then, the vertical synchronizing signal and the color subcarrier signal generated by the synchronizing DSP 27 are supplied to the switch matrix circuit 45 via the input terminal 50.

Further, the switch matrix circuit 45 includes
M (m <n) output RAMs 511, the details of which will be described later.
The digital image data output from 51m is supplied. Then, the switch matrix circuit 45
Are vertical synchronization signals and color subcarrier signals supplied via the input terminal 50, and the A / D converters 441 and 44.
2, ..., Digital image data output from 44n,
From the digital image data supplied to the input terminal 48 and the digital image data output from the output RAMs 511, ..., 51m, m data are selected and m shift registers 521, 522 ,. It supplies to 52m respectively.

These shift registers 521, 522, ...
, 52m can shift-input data for 1H (horizontal scanning) period based on the sample clock signal and the horizontal synchronizing signal output from the synchronous DSP 27 and supplied via the input terminal 47. That is,
When the switch matrix circuit 45 outputs the digital image data corresponding to the waveform for the 1H period as shown in FIG. 3A, the shift registers 521, 522 ,.
Digital image data corresponding to the direction of the waveform shown in FIG. 3B is sequentially input to 2 m from the left side to the right side in the figure.

Here, the shift registers 521, 522,
.., 52m each have a built-in latch circuit, and when digital image data for 1H period is accumulated,
At the timing when the data is based on the horizontal sync signal,
It is transferred to the latch circuit as shown in FIG. And
The digital image data for 1H period held in the latch circuit of each shift register 521, 522, ..., 52m is, as shown in FIG. 2 and FIG.
(Arismetic Logic Unit) 531,5
, 53p are supplied to the arithmetic unit 53 in a time division manner, and arithmetic operations for decoding the digital image data are performed.

That is, the arithmetic unit 53 time-divisionally captures 1H worth of digital image data held in the latch circuits of the shift registers 521, 522, ..., 52m, and the fetched 1H worth of digital image data. Are shared by a plurality of ALUs 531, 532, 533, ..., 53p and signal processing is executed within a 1H period. For this reason,
If only one pixel is calculated by one ALU, the total number of ALUs is 910, which is the number of horizontal pixels in the case of NTSC. If one ALU can calculate a plurality of pixel data, AL
The number of U's can be reduced accordingly.

Here, each of the ALUs 531 and 5 of the arithmetic unit 53 is
.., 53p execute arithmetic processing based on the program stored in the program memory 54, as shown in FIG. In the program memory 54, a necessary program is selectively read out by the program loader 34 from the various programs stored in the program memory 33 described above, and loaded through the input terminal 55. In this case, a maximum of m programs can be loaded in the program memory 54 to decode the m digital image data held in the latch circuits of the shift registers 521, 522, ..., 52m. These programs are time-divisionally shared by the ALUs 531, 532, 533 ,.
By being supplied to 3p, each digital image data is sequentially decoded.

Incidentally, each ALU 531, 532, 533
..., 53p have memories 551, 552, 5 respectively.
53, ..., 55p are connected to each ALU 53.
1, 532, 533, ..., 53p is the memory 55
The calculation result is held by using 1, 552, 553, ..., 55p.

The output data of the arithmetic unit 53 is
It is selectively supplied to the m shift registers 561, ..., 56m. That is, the data obtained by decoding the digital image data latched in the shift register 521 by the arithmetic unit 53 is supplied to the shift register 561, and the data obtained by decoding the digital image data latched in the shift register 522 by the arithmetic unit 53 is , And is supplied to the shift register 562.

This shift register 561, ..., 56m
Each has a built-in latch circuit.
When the output data from the arithmetic unit 53 is supplied as shown in (e), the data is latched by the latch circuit, and the shift register 561, as shown in FIG. …, Transferred to 56m.
The data transferred to the shift registers 561, ..., 56m are serially output based on the sample clock signal supplied via the input terminal 47.
511, ..., 51m are output.

The shift registers 561, ..., 56m
Have two types, one for image data and one for address, respectively. In the output RAMs 511, ..., 51m, the data output from the image data shift register is sequentially assigned to the address output from the address shift register. Written. And, in the output RAMs 511, ..., 51m,
Data is read by supplying an address that sequentially changes from 1 in sequence. The read data is added to the demultiplexer 57 to select the necessary data and is taken out from the output terminals 581, 582, ..., 58m. In the case of a multiplexed signal such as a color signal, the demultiplexer 57 demultiplexes the multiplexed signal as necessary to output the output terminals 581, 5
82, ..., 58m is output.

The data read address of the output RAMs 511, ..., 51m is set to 1 by programming.
It is given by any permutation, not just a value that monotonically increases from. This can be achieved by converting the address value using a ROM, RAM or the like for the output of the counter that outputs a value that monotonically increases from 1. If you do this,
It is possible to easily extend the time axis of the image in the horizontal direction. In addition, ALU531,532,533, ..., 53
Data of p can be exchanged with each other by a communication bus 59.

The read address given to the program memory 54 is generated from the program counter 60. Then, switching of the program read from the program memory 54 is realized by the branch control circuit 61 operating the program counter 60 based on the output of the interrupt vector generation circuit 62 and the horizontal synchronization signal. In this case, in order to temporarily hold the output address from the program counter 60, the stack register 63
Is provided.

Here, FIG. 4 shows the internal structure of the ALU 531. In addition, other ALU532,533,
.., 53p have the same configuration as that of the ALU 531 and therefore the description thereof is omitted. That is, 531 in the figure
Reference numeral a is an input terminal to which the program data read from the program memory 54 is supplied. The program data supplied to the input terminal 531a is input to the instruction decoder 531b and is decoded, whereby the address register 531c, the logical operation unit 531d, the A register 531e, the B register 531f, and the switch 531g.
Are controlled to perform desired arithmetic processing, that is, decoding processing.

The input terminal 531h receives the digital image data held in the latch circuits of the shift registers 521, 522, ..., 52m, and the input terminal 531h.
31i is connected to the communication bus 59. Further, the calculation result of the logical operation unit 531d is taken into the D register 531j, and then output to the shift registers 561, ..., 56m via the output terminal 531k and to the memory 551 via the output terminal 531l. To be done. During the operation of the logical operation unit 531d, a signal indicating that the operation is being performed is supplied to the branch control circuit 61 via the output terminal 531m.

Then, in the memory 551, as shown in FIG. 5, areas from addresses 0000 (hexadecimal) to 00FF (hexadecimal) where the data inputted from the shift registers 521, 522 ,. And 0100
Addresses from (hexadecimal) to 01FF (hexadecimal) are areas in which data to be output to the shift registers 561, ..., 56m are written, and 0200 (hexadecimal) to 02FF (16).
The area up to the address is the area in which the transfer data with the ALU on the right side and the ALU on the left side are written, and from 0300 (hexadecimal) to FFF
The area up to the address F (hexadecimal) is the area where the calculation result is written.

Here, the ALU 531 having the above-mentioned configuration
On the other hand, it will be described that various calculations and signal processing can be performed by switching the programs to be given. That is, FIG. 6 shows a flowchart for performing addition, subtraction and multiplication processing. First, when started (step S1), the instruction decoder 531b operates in step S
2, the shift registers 521, 522 and 522 of the memory 551
..... Read out two pieces of data to be processed from the writing area of the data input from 52 m, and
And B registers 531e and 531f.

Then, in step S3, the instruction decoder 531b controls the logical operation unit 531d so as to add, subtract or multiply the data stored in the A and B registers 531e and 531f, and outputs the operation result. D
It is stored in the register 531j. Then, in step S4, the instruction decoder 531b causes the data stored in the D register 531j to be written in the operation result writing area of the memory 551, and the operation processing ends there (step S4).
5) is done.

FIG. 7 shows a flow chart for performing the one pixel delay process. First, when started (step S6), the instruction decoder 531b reads the data before being delayed from the memory 551 and stores it in the D register 531j in step S7. afterwards,
The instruction decoder 531b, in step S8, the communication bus 5
The data stored in the D register in another adjacent ALU via 9 is read out and stored in the A register 531e. Then, the instruction decoder 531b, the step S9
To store the data stored in the A register 531e in the memory 5
The data is written in 51, and the one-pixel delay processing is ended here (step S10).

Further, FIG. 8 shows a flowchart for performing the 1H delay process. First, when started (step S11), the instruction decoder 531b reads data from the address secured for 1H delay in the memory 551 and stores it in the memory 551 in step S12. After that, the instruction decoder 531b determines in step S
At 13, the data to be delayed by 1H is read out from the memory 551 and written in the address secured for 1H delay in the memory 551, and the 1H delay processing ends there (step S
14) is done.

As described above, the ALUs 531 to 5p are capable of performing various arithmetic operations and signal processings by switching the programs to be given to the ALUs 531 to 53p.
It will be described how to make the 3p perform the NTSC decoding process. That is, FIG. 9 shows ALUs 531-53p.
Is a functional representation of the processing means for decoding a signal encoded in accordance with the NTSC format using.

Explaining with the flowchart shown in FIG. 10, first, when the operation is started (step S15), the AL
U531-53p wait in step S16 until 1H digital image data is accumulated in the shift registers 521, 522, ..., 52m, and then in step S17.
Then, 1H worth of digital image data is input from the shift registers 521, 522, ..., 52m through the input terminal 64a. Then, in step S18, the ALUs 531 to 53p pass the input digital image data through a BPF (band pass filter) 64b to extract high frequency components.

Thereafter, the ALUs 531 to 53p, in step S19, shift registers 521, 522 ,.
The color subcarrier signal is input from 2m via the input terminal 64c, and in step S20, the high frequency component output from the BPF 64b is multiplied by the color subcarrier signal in the multiplication circuit 64d to obtain the color signal 1. In addition, ALU53
In steps 1 to 53p, in step S21, the color subcarrier signal is multiplied by 90 ° by the phase shifter 64e and the high frequency component is multiplied by the multiplication circuit 64f to obtain the color signal 2.

Then, in step S22, the ALUs 531 to 53p perform a matrix operation on the two color signals 1 and 2 by the matrix circuit 64g to generate two color difference signals RY and BY, and in step S23. Then, through the output terminals 64h and 64i, the shift registers 561 ,.
Output to 56m. Next, ALU531-53p
In step S24, the subtraction circuit 6 subtracts the output of the BPF 64b from the digital image data supplied to the input terminal 64a.
The luminance signal Y is generated by the subtraction at 4j, and the shift register 5 is generated via the output terminal 64k at step S25.
After outputting to 61, ..., 56 m, the process is returned to the process of step S16, where the decoding process of the NTSC signal is performed.

In recent years, in order to improve the image quality of a received image, signal processing inside the television receiver has become complicated, such as a non-linear operation process and an image delay process. Therefore, in order to realize such complicated signal processing, the video decoder DSP 23 includes ALUs 531 to 53p in addition to the above-mentioned four arithmetic operations and pixel movement operations.
The conditional branch processing function for switching the program according to the condition of the operation result and the condition of the operation result by giving the operation result of the above to the branch control circuit 61 through the output terminal 531m. The ALUs 531 to 53p have a function of controlling whether or not to execute processing.

Next, according to the clear vision standard, a GCR (ghost reference signal waveform) signal is multiplexed in the vertical blanking period of the image signal, and the ghost is removed by referring to this GCR signal on the receiving side. There is. FIG. 11 shows the ghost removal processing with reference to the GCR signal as described above by the ALU5.
This is a functional representation of the processing means in the case of using 31 to 53p, and it constitutes a transversal filter in terms of the circuit.

That is, this delays the digital image data supplied to the input terminal IN by a plurality of delay lines T1, T2, T3, T4, ... Coefficient multipliers M0, M1, M2, M3, M4 are provided to the tap outputs of the lines T1 to Tn, respectively.
..., Mn-1, Mn tap coefficients k0, k1, k2
, kn-1, kn are multiplied, and the outputs of the respective coefficient units M0 to Mn are added by adders A1, A2, A3, A4 ,.
, An-1, An are convoluted to obtain the digital image data from which the distortion component due to the ghost is removed, from the output terminal OUT.

Therefore, for example, when receiving the NTSC signal, the ALUs 531 to 53 are displayed during the display period of the image signal.
A program for performing the decoding processing function of the NTSC signal shown in FIG. 9 is given to p, and during the non-display period of the image signal,
By providing the ALUs 531 to 53p with a program for performing the ghost removal processing function shown in FIG. 11, the same video decoder DSP23 can be used to execute the NTSC signal decoding processing and the ghost removal processing.

Next, the MUSE system will be described as a television system different from the NTSC system. That is, in the case of the MUSE system, as shown in FIG. 12, pixels indicated by white circles and pixels indicated by black circles are alternately transmitted for each frame, and in the case of a still image, these two frames are transmitted. The signals are combined and restored, and in the case of a moving image, the missing pixels are interpolated using only the pixel data of each frame. That is, in the case of the MUSE method, it is necessary to perform signal processing corresponding to each of the moving images and the still images while determining whether the moving image or the still image, and thus the signal processing becomes very complicated.

Therefore, in order to reduce the cost of the television receiver, it is considered that the image is reproduced only by the signal processing of the moving image and the structure is simplified. FIG. 13 shows such a simple MUSE signal processing as ALU531-53.
It is a functional representation of the processing means when performed using p.

That is, M supplied to the input terminal 65a
The data obtained by digitizing the USE image signal is input to the 1H delay lines 65b and 65c connected in series, and 1H
Delayed and delayed by 2H. Of these, input data and 2H
The delayed data means 1-pixel delay line 65d,
65e and after being delayed by one pixel, the coefficient unit 65
It is weighted with f and 65 g. Further, the data delayed by 1H is weighted by the coefficient unit 65h, and
After being supplied to the 1-pixel delay lines 65i and 65j and delayed by 2 pixels, the coefficients are weighted by the coefficient unit 65k. Then, the outputs of the coefficient units 65f, 65g, 65h, and 65k are added by the adder circuit 65l, so that the pixel interpolation processing as shown by the arrow in FIG. 12 is performed, and the output terminal 65m.
Taken from.

For this reason, the ALUs 531 to 53p are shown in FIG.
By applying the program for performing the decoding processing function of the NTSC signal shown in FIG. 9 and the program for performing the decoding processing function of the MUSE signal shown in FIG. 13 in a time division manner, the same video decoder DSP23 is used.
It is possible to selectively execute the decoding process of the TSC signal and the decoding process of the MUSE signal.

Next, referring to FIG. 2 again, description will be made on the time-division decoding processing of a plurality of input image signals by using the same video decoder DSP23. In this case, a particular problem is that a plurality of input image signals are not synchronized with each other. That is, the image signals supplied to the input terminals 421, 422, ..., 42n are clamp circuits 431, 432 ,.
n level adjustment processing and A / D converters 441, 44
After being digitized by 2, ..., 44n,
Selected by the switch matrix circuit 54 and led to the shift registers 521, 522, ..., 52m.

At this time, the A / D converters 441, 442,
.., 44n, A / D conversion processing is performed by each independent sample clock signal, and shift register 52
, 522, ..., 52m perform a shift operation based on an independent sample clock signal synchronized with each input digital image data, and have an independent horizontal synchronization synchronized with each input digital image data. Data is transferred to the latch circuit based on the signal. Further, the shift register 561, which is the output side, ...
The same operation is performed for 56m.

ALUs 531, 532, 533
.., 53p decodes the data input to the shift registers 521, 522, ..., 52m in a time division manner by selectively applying a plurality of programs stored in the program memory 54. For example, input terminals 421, 422, 423 have MUSE signals, NTSC
Signal and another NTSC signal are respectively supplied, that is, the tuner IF amplifier 12 makes one MUSE.
When a broadcast and two NTSC broadcasts are received, the program memory 54 stores 0000 (1
A program for decoding the MUSE signal supplied from the (hexadecimal) address to the input terminal 421 is stored, and 1
A program for decoding the NTSC signal supplied from the address 000 (hexadecimal) to the input terminal 422 is stored, and a program for decoding the NTSC signal supplied from the address 2000 (hexadecimal) to the input terminal 423. Are stored in the program memory 33 via the program loader 34 so that the three types of programs are written and selectively stored in the ALUs 531, 532.
533, ..., 53p will be supplied.

The control of which program is transferred from the program memory 33 to which address of the program memory 54 is performed by controlling the television broadcast selected by the user and the input terminal 42 of the video decoder DSP 23 whose broadcast reception signal is received.
1, 422, ..., 42n are supplied to the CPU
The determination is made by 35 and the program loader 34 is controlled. In the above case, the number of received programs, that is, two programs for decoding the NTSC signal is provided because the input / output registers used for decoding the two NTSC broadcasts and the addresses of the memories used are different. . That is, even when receiving a plurality of broadcasts of the same television system, it is necessary to transfer the programs for decoding each broadcast to the program memory 54.

By the way, the shift registers 521, 52
The digital image data for 1H input to 2, ..., 52m needs to be selectively supplied to the arithmetic unit 53 and arithmetically processed within the 1H period. Now, the input terminal 421,
As shown in FIGS. 15A, 15B, and 15C, the MUSE image signal 1 and the NTSC image signal 2 and 3 are input to 422 and 423 at arbitrary timings as shown in the drawing. It is assumed that In this case, as described above, the image signals 1, 2, and 3 are supplied to the synchronous DSP 27, the horizontal synchronous signal thereof is extracted, and are supplied to the branch control circuit 61. The 1H periods of the image signals 2 and 3 are the same, and the 1H period of the image signal 1 is 1 of the image signals 2 and 3.
It is about half of the H period.

First, when the horizontal synchronizing signal of the image signal 1 is applied to the branch control circuit 61 at time t1 in FIG. 15, the branch control circuit 61 causes the interrupt vector generation circuit 62 to output the MUSE signal in the program memory 54. Address where the decoding processing program of the above is stored (0000 in FIG. 14).
Address) will be given. Then, the branch control circuit 61 sets this start address in the program counter 60, and the program counter 60 starts the counting operation from this start address, so that the program memory 54 starts the MUS.
The E signal decoding processing program is read and ALU5
, 532, 533, ..., 53p, and the decoding processing of the image signal 1 is executed here as shown in FIG.

When the horizontal synchronizing signal of the image signal 2 is applied to the branch control circuit 61 before the time t2 when the decoding process of the image signal 1 is completed, the branch control circuit 61 is provided with an interrupt vector generating circuit. 62 to program memory 5
The leading address (1000 in FIG. 14) in which the decoding processing program of the NTSC signal in 4 is stored is given. In this case, the branch control circuit 61 includes an arithmetic unit 53.
Since a signal indicating that the ALUs 531, 532, 533, ..., 53p are in operation is supplied from the ALU 531, the branch control circuit 61 sets the start address to the program counter 6
Pending setting to 0.

After that, when the decoding process of the image signal 1 is completed at the time t2, the branch control circuit 61 causes the ALU 53 to operate.
Since the signal indicating that 1,532, 533, ..., 53p is in operation is not supplied, the head address given from the interrupt vector generating circuit 62 is set in the program counter 60, and the program counter 60 By starting the counting operation from the head address, the NTSC signal decoding processing program is read from the program memory 54 and the ALUs 531, 532, 533 ,.
3p, and the decoding process of the image signal 2 is executed here as shown in FIG. 15 (d).

Also, when the horizontal synchronizing signal of the image signal 3 is applied to the branch control circuit 61 before the time t3 when the decoding process of the image signal 2 is completed, the same as above.
In the branch control circuit 61, the head address (2 in FIG. 14) where the decoding processing program of the NTSC signal in the program memory 54 from the interrupt vector generation circuit 62 is stored.
000) is given to the branch control circuit 61,
From the arithmetic unit 53 to the ALUs 531, 532, 533, ...
Since the signal indicating that 53p is being calculated is supplied, the branch control circuit 61 suspends the setting of this head address in the program counter 60.

When the decoding process of the image signal 2 is completed at time t3, the branch control circuit 61 causes the ALU 53 to operate.
Since the signal indicating that 1,532, 533, ..., 53p is in operation is not supplied, the head address given from the interrupt vector generating circuit 62 is set in the program counter 60, and the program counter 60 By starting the counting operation from the head address, the NTSC signal decoding processing program is read from the program memory 54 and the ALUs 531, 532, 533 ,.
3p, and the decoding process of the image signal 3 is executed here as shown in FIG. 15 (d).

Then, as described above, the ALUs 531 and 5
32, 533, ..., 53p, by sequentially switching the programs given to the plurality of image signals 1, 2, 3
Can be decoded without interruption during each 1H period.

Here, in FIG. 16, a desired program is loaded from the program memory 33 into the program memory 54 of the video decoder DSP 23 in accordance with the received television broadcast.
7 is a flowchart showing an operation of loading the data into the memory. First,
When started (step S26), the CPU 35 fetches the operation information from the user supplied from the input terminal 40 through the port 41 in step S27, and then in step S27.
At 28, it is determined whether the signal processing system including the input terminal 421 of the video decoder DSP 23 is unused.

If unused (YES), CP
U35, in step S29, the tuner IF of a plurality of systems.
An unused one of the amplifiers 12 is used to receive a desired television broadcast. Then, in step S30, the CPU 35 controls the switch circuit 14 to supply the output of the VSB / FM demodulator 13 that demodulates the received television signal to the input terminal 421 of the video decoder DSP 23. Then, in step S31, the CPU 35 controls the program loader 34 to read the decoding processing program corresponding to the received television broadcasting system from the program memory 33, and set the address 0000 (hexadecimal) to the beginning in the program memory 54. The address is written, and the process returns to step S27.

In step S28, the video decoder D
When it is determined that the signal processing system including the input terminal 421 of the SP23 is unused (NO), the CPU 35 in step S32, the input terminal 42 of the video decoder DSP23.
It is determined whether or not the signal processing system including 2 is unused. Then, if it is unused (YES), the CPU 35 receives a desired television broadcast by using an unused one of the tuner IF amplifiers 12 of a plurality of systems in step S33. Then, in step S34, the CPU 35 controls the switch circuit 14 to supply the output of the VSB / FM demodulator 13 that demodulates the received television signal to the input terminal 422 of the video decoder DSP 23. And C
The PU 35 sends the program loader 34 in step S35.
Control unit to read the decoding processing program corresponding to the received television broadcasting system from the program memory 33, and store 1000 (16) in the program memory 54.
The advance address is written as the first address, and the process returns to step S27.

Further, when it is determined in step S32 that the signal processing system including the input terminal 421 of the video decoder DSP 23 is unused (NO), the CPU 35 determines in step S36 the input terminal 4 of the video decoder DSP 23.
It is determined whether the signal processing system including 23 is unused. If it is not used (YES), the CPU 35 receives a desired television broadcast by using an unused one of the tuner IF amplifiers 12 of a plurality of systems in step S37. After that, in step S38, the CPU 35 controls the switch circuit 14 to supply the output of the VSB / FM demodulator 13 that demodulates the received television signal to the input terminal 423 of the video decoder DSP 23. And
The CPU 35, in step S39, the program loader 3
4 to read the decoding processing program corresponding to the received television broadcasting system from the program memory 33, and the program memory 54 stores 2000 (16
The advance address is written as the first address, and the process returns to step S27.

By repeating the above processing, a plurality of television broadcasts are received and a decoding processing program corresponding to each received television broadcast is loaded into the program memory 54 of the video decoder DSP 23. Multiple video signals into one video decoder DSP
The decoding process can be performed at 23.

Next, before describing the case of receiving digital broadcasting, an outline of digital broadcasting will be briefly described. In digital broadcasting,
Images are encoded, the amount of information is compressed, and data is transmitted. FIG. 17 shows an encoder system for performing such image coding compression. That is, reference numeral 66a in the drawing is an input terminal, for example, digital image data obtained by converting an optical image of a subject photographed by a camera into an image signal by a CCD (charge coupled device) and A / D converting the image signal. Is being supplied.

The digital image data supplied to the input terminal 66a is the DCT (discrete cosine transform) circuit 66b.
Is normally supplied to the horizontal direction and the vertical direction is 8 pixels.
Orthogonal transformation using an orthogonal cosine function sequence is performed in units of pixel blocks of dimension. Then, the data after the orthogonal transformation is quantized by the quantization circuit 66c and the bit precision is lowered. In this case, the bit precision of the digital image data is not directly reduced, but the bit precision of the high-frequency component whose deterioration is less noticeable is reduced so that the deterioration of the image quality is less noticeable.

By thus reducing the bit precision of the high frequency component, the probability that 0 appears in the lower bit of the pixel data becomes very high. Utilizing this property, Huffman coding is performed in the variable length coding circuit 66d. In this Huffman coding, since a short code is assigned to a pattern with a high appearance probability, it is possible to reduce the number of bits. However, Huffman coding is a variable-length coding method in which the number of bits is reduced but the number of bits is unknown.Therefore, in order to keep the transmission bit rate on the transmission line constant, the output bits after Huffman coding are The quantization accuracy of the quantization circuit 66c is controlled according to the amount, and is controlled so that a fixed amount of code is output after Huffman coding. That is, the inside of the variable-length coding circuit 66d includes a Huffman coding circuit and a FIFO (first in first
Out)) bit rate conversion circuit.

Here, the code rate will be specifically described with reference to FIG. 18. The code rate of the digitized image signal is as shown in FIG. Then, the data rate after calculation becomes as shown in FIG. 18 (b), and at this point, D
The input data rate and the output data rate of the CT circuit 66b are the same. Then, when Huffman coding is applied to the output data of the DCT circuit 66b, the number of m data after DCT is reduced to n as shown in FIG. 18C. Thereafter, this reduced data is time-expanded and transmitted to a time similar to the period of the original m number of images by using the FIFO as shown in FIG. 18D, so that the data rate is lowered. I have to.

Then, the output of the variable length coding circuit 66d and the digital audio data supplied to the input terminal 66e are supplied to the error correction code adding circuit 66f to be added with the error correction code, and then the orthogonal carrier is added. It is QAM-modulated by the used amplitude modulation QAM modulation circuit 66g and taken out from the output terminal 66h.

Next, FIG. 19 shows a system for receiving digital broadcasting, that is, a decoder system for image coding and compression. That is, the QAM modulation signal supplied to the input terminal 67a is demodulated by the QAM demodulation circuit 67b,
The obtained bit string is subjected to error correction processing by the error correction circuit 67c, and then separated into digital audio data and digital image data. Of these, the digital audio data is supplied to the audio DSP 20 shown in FIG. 1, for example, via the output terminal 67d for data processing. Further, the digital image data is supplied to the variable length code decoding circuit 67e and is subjected to processing reverse to the processing by the variable length coding circuit 66d on the encoder side.

In this case, the variable length code decoding circuit 67e
Output data has the same clock rate as the digital image data supplied to the input terminal 66a on the encoder side. The output data of the variable length code decoding circuit 67e is restored to the original digital image data by the inverse DCT circuit 67f performing the inverse DCT operation, and is taken out from the output terminal 67g.

Here, the above-mentioned DCT operation and inverse DCT
The arithmetic processing can be configured by combining a multiplication circuit and a cumulative addition circuit. Further, since the input and output clock rates are the same, the operation is similar to that of a filter or the like in the processing of the NTSC signal. Is easy to share. That is, the video decoding DSP
Inverse DCT calculation can be performed by the 23 ALUs 531, 532, 533, ..., 53p.

FIG. 20 shows the inverse DCT operation performed by the ALU 531 to ALU 531.
This is a functional representation of the processing means when using 53p. That is, the data after the variable-length code decoding process supplied to the input terminal 68a is sequentially delayed by the seven 1H delay lines 691, ..., 697 connected in series, and the tap outputs of the respective 1H delay lines 691 to 697 are output. The cumulative adders 701, 702, ...
08, the coefficients are cumulatively added, and the cumulative adders 701 to 708 are added.
, 717 are used to convolve the output of the above-mentioned equation (7) with the result of the inverse DCT operation from the output terminal 68b.

Further, the cumulative adder 701 converts the input data into seven 1-pixel delay lines 721, ..., Which are connected in series.
721 sequentially delays, and the tap outputs of the 1-pixel delay lines 721 to 721 are respectively multiplied by multipliers 731 and 731.
..., 738 multiplies the coefficients k0v, ..., k7v, and the outputs of the multipliers 731 to 738 are adders 741, ..., 747.
Accumulation is performed by convolving with. In addition,
The other cumulative adders 702, ..., 708 have the same configuration as the cumulative adder 701, and therefore the description thereof is omitted.

The inverse DCT calculation is performed in the two-dimensional pixel block of 8 pixels in the horizontal direction and 8 pixels in the vertical direction in the DCT calculation.
This is performed for each pixel in column j row. Coefficient k0v, ..., k7v
For the calculation of the data of the i-th column and the j-th row in the block, kuv = [cos {(2i + 1) uπ / 16}] ・ [cos {(2j + 1) vπ / 16}] ・ Cu ・ Cv u = 0: Cu = ^{2-1 / 2} v = 0: Cv = ^{2-1 / 2} u> 0: Cu = 1 v> 0: Cv = 1.

Using the flowchart shown in FIG. 21, A
The inverse DCT calculation processing operation by the LUs 531 to 53p will be described. First, when started (step S40), the ALU
531 to 53p fetch the data of the 8 × 8 pixel block after the variable length code decoding processing accumulated in the shift registers 521, 522, ..., 52m in step S41, and in step S42, the contents of the D register 531j are read. 0
After that, in steps S43 and S44, v = 0 and u = 0
Set to.

Then, in step S45, the ALUs 531 to 53p convert the pixel data F (u, v) in the u-th column and the v-th row out of the 8 × 8 pixel block data subjected to the DCT operation to
Input to A register 531e, and in step S46, DC
Cu inverse conversion formula Cu · Cv · [cos {(2i + 1) uπ / 16}] · [cos {(2j + 1) vπ / 16}] is input to the B register 531f. After that, ALU5
31 to 53p are A registers 531 in step S47.
The content of D register 531j is added to the result of multiplying the content of e by the content of B register 531f, and the addition result is input to D register 531j.

Then, the ALUs 531 to 53p increment u by 1 in step S48 and determine whether u = 8 in step S49. If u = 8 (NO), step S4.
Returned to the processing of No. 5. If u = 8 (YE
S), the ALUs 531 to 53p are v in step S50.
Is incremented by 1, and in step S51, it is determined whether or not v = 8.
If v = 8 is not satisfied (NO), the process returns to step S44. Furthermore, if v = 8 (YES), ALU5
31 to 53p, in step S52, i = 0 to 7, j =
It is determined whether or not the inverse DCT calculation has been completed for all pixel data 0 to 7, and if not completed (NO), the process returns to step S43, and if completed (YE
S), the process returns to step S41, where 8 ×
Inverse DCT calculation processing is performed for each 8 pixel block.

Next, in the NTSC broadcasting using terrestrial waves, the clear vision broadcasting is being performed as described above. There are two types of signal processing items for clear vision broadcast receivers: three-dimensional signal processing and ghost removal processing.

FIG. 22 is a functional representation of means for performing three-dimensional signal processing using the ALUs 531 to 53p. The same parts as those in FIG. 9 are designated by the same reference numerals.
That is, reference numeral 75a in the drawing denotes an input terminal to which data obtained by digitizing an NTSC format image signal is supplied. The subtracter 75c calculates the difference between the digital image data supplied to the input terminal 75a and the data delayed by one frame by the frame memory 75b, and the LPF (low pass filter) 75d calculates a color signal from the calculation result. The motion detection signal is obtained by removing the component.

The digital image data supplied to the input terminal 75a and the data delayed by one frame by the frame memory 75b are added by the adder 75e. Therefore, in the case of a still image, the output data of the adder 75e does not include a color signal, and since it is a still image, the images of the two frames completely overlap. This image is not filtered horizontally or vertically, so
The resolution will be very high.

Further, the digital image data supplied to the input terminal 75a is supplied to the LPF 75f. Therefore, in the case of a moving image, the color signal is removed and the luminance signal Y is obtained. Then, the output data of the adder 75e and the LPF
75f output data and LPF by switch 75g
Switching based on the output of 75d, that is, depending on whether it is a still image or a moving image, data corresponding to each is selected and taken out from the output terminal 75h, and three-dimensional signal processing is performed there. Further, the subtracter 75i calculates the difference between the digital image data supplied to the input terminal 75a and the data guided by the switch 75g, and the calculation result is multiplied by the multiplication circuit 64.
By supplying the color difference signals R-Y,
It is used for the production of BY.

Regarding the three-dimensional signal processing, the image quality can be improved by the receiver side executing the above calculation even when the broadcast station side is not performing the clear vision broadcast. That is, if the receiver has a sufficient ability to perform three-dimensional signal processing, the amount of calculation will increase as compared with the basic processing of NTSC described above, but this three-dimensional signal processing is always required. It is better to do it. Note that FIG. 23 shows a state in which the basic decoding processing program and the three-dimensional decoding processing program of the NTSC signal are stored in the program memory 54.

Next, FIG. 24 shows the video decoder DSP 23.
28 GOPS (GigaOperation Per Secon)
It is a diagram schematically showing the relationship of the processing amount required in various signal decoding processes in the case of d). now,
NTSC broadcast is received and the video decoder DSP23
It is assumed that dimension decoding processing is being performed. Then, Figure 2
As indicated by A in FIG. 4, in the three-dimensional decoding process, the video decoder DSP 23 is forced to have a processing capability of 23 GOPS, and at this time, 82% of the processing capability of the video decoder DSP 23 is used.

When another NTSC broadcast is newly received in this state, the CPU 35 receives the newly received NSC broadcast.
An attempt is made to perform three-dimensional decoding processing for TSC broadcasting as well. However, if three-dimensional decoding processing is performed on two NTSC broadcasts, the total processing amount becomes 46 GOPS, which exceeds the maximum processing amount of 28 GOPS of the video decoder DSP 23. Therefore, as shown in B of FIG. 24, the CPU 35 performs the normal NTSC basic decoding process, not the three-dimensional decoding process, on the newly received NTSC broadcast, that is,
Try to deal with a program that has low processing load.

However, since the processing amount of NTSC basic decoding processing is 9 GOPS, the total processing amount is 32 GOPS when combined with the processing amount of three-dimensional decoding processing of 23 GOPS.
It becomes OPS, which exceeds 28 GOPS, which is the maximum processing amount of the video decoder DSP 23. Therefore,
As shown in C of FIG. 24, the CPU 35 handles the initially received NTSC broadcast not by the three-dimensional decoding process but by the normal NTSC basic decoding process, that is, with a small processing amount. Switch the program to. In this case, the total processing amount is 18 GOPS, which is the maximum processing amount of the video decoder DSP 23 of 28 GOPS.
Since it falls within the range of, it becomes possible to receive two NTSC broadcasts.

That is, the CPU 35 controls the video decoder D
Until the processing amount of SP23 exceeds the maximum processing amount, a decoding processing program capable of decoding the received television broadcast with high image quality even if the processing amount is large is selected. When the television broadcast to be received is added, first, the total processing amount of the video decoder DSP 23 when the added television broadcasting is decoded with high image quality is calculated, and the maximum processing amount is exceeded. In such a case, the added television broadcast is dealt with by a decoding process with a small processing amount. And
If the total processing amount of the video decoder DSP23 still exceeds the maximum processing amount, the decoding process for the already received television broadcast is switched to a program with a small processing amount so that a plurality of television broadcasts can be received. ing.

FIG. 25 is a flow chart summarizing the switching operation of the decoding processing program as described above. First, the CPU 35 takes in the operation information from the user supplied from the input terminal 40 through the port 41 in step S53, and determines in step S54 whether the reception channel is added or deleted. If it is addition, in step S55, the CPU 35 adds the current processing amount of the video decoder DSP 23 and the processing amount required for the decoding process of the added channel to obtain the video decoder D.
The total processing amount of SP23 is calculated, and it is determined in step S56 whether the total processing amount exceeds the maximum processing amount of the video decoder DSP23.

When it is determined that the number of channels is not exceeded (NO), the CPU 35 adds the new program required for the decoding process of the added channel to the program memory 54 in step S57, and returns to the process of step S53. Further, in step S56, the total processing amount is the video decoder D.
When it is determined that the maximum processing amount of SP23 is exceeded (YES), the CPU 35 determines in step S58 whether or not there is a program with a smaller processing amount among the programs required for the decoding process of the added channel. If so (YES), the process returns to step S55.

Furthermore, if it is determined in step S58 that there is no processing amount (NO), the CPU 35
In step S59, it is determined whether or not there is a program with a smaller processing amount among the programs currently being processed,
If not (NO), an error is returned to the process of step S53. When there is a program with a small processing amount (YES), the CPU 35 determines in step S60 that the total processing amount is the video decoder DS when the program is used.
It is determined whether or not the maximum processing amount of P23 is exceeded, and if it exceeds (YES), an error is returned to the processing of step S53.

When it is determined in step S60 that the total processing amount does not exceed the maximum processing amount of the video decoder DSP 23 (NO), the CPU 35 in step S61 changes the program currently being processed to a program with a small processing amount. It is changed and the process returns to step S53.

If deletion of the reception channel is requested in step S54, the CPU 35 deletes the decoding program of the reception channel requested to be deleted from the program memory 54 in step S62.
After that, in step S63, the CPU 35 searches for a program that can perform high-quality decoding processing even if the processing amount is large in the decoding processing of the remaining reception channels, and uses the searched program in step S64. It is determined whether or not the total processing amount exceeds the maximum processing amount of the video decoder DSP 23, and if it exceeds (YES), step S53.
Returned to the processing of. If it does not exceed (NO),
In step S65, the CPU 35 changes the program currently being processed to the program for high image quality decoding processing, and returns to the processing of step S53.

Therefore, when the receiving channels are deleted, the remaining receiving channels can be displayed in high quality. The operation of the flowchart shown in FIG. 25 is basically controlled by the CPU 35, but, for example, steps S56, S58, S59, S60,
The determination operation of S64 and the like may be performed by the program loader 34.

In the above description, three-dimensional decoding processing and N
Although the TSC basic decoding process is taken as an example, the present invention is not limited to this, and the same can be applied to, for example, the MUSE decoding process and the MUSE down-conversion process. Also, as the decoding processing programs having different processing amounts, there are a case of processing all the input image data, a case of processing a part of the input image data, that is, a spatial part of the screen, and a case of processing one of several fields. However, it may be realized by a combination of these. As a means for processing only a part of the input image data, if the image data is stored in the memory and then sequentially read and processed, the processing amount in the video decoder DSP 23 can be greatly reduced.

Further, in the above description, the switching of the decoding process is performed by loading the program in the program memory 54, but the switching of the decoding process can also be performed by the means shown in FIG. 26, for example. First, as shown in FIG. 27, the program memory 54 stores a basic decoding processing program and a three-dimensional decoding processing program for NTSC signals. Then, for example, when only one NTSC broadcast is being received, the address of the storage area of the three-dimensional decoding processing program of the program memory 54 from the program counter 60 is controlled by the control circuit 76a via the branch control circuit 61. Is generated. Therefore, the three-dimensional decoding processing program is read from the program memory 54 and is transmitted via the output terminal 76b to the ALUs 531, 532 and.
533, ..., 53p, and high-quality decoding processing is performed.

In such a state, when the user continues to receive the broadcast currently being received and does not receive another television broadcast, the user operates the input terminal 76c. It is supplied to the control circuit 76a through the control circuit 76a, and the control circuit 76a performs the processing amount determination operation as shown in FIG. Then, the sum of the processing amount required to decode the newly received television broadcast and the processing amount required to decode the already received television broadcast is the maximum processing amount of the video decoder DSP23. If the control circuit 76a determines to exceed the
The address of the storage area of the NTSC basic decoding processing program of the program memory 54 is generated from the program counter 60 via the branch control circuit 61.

Therefore, from the program memory 54,
The NTSC basic decoding processing program is read out and ALUs 531, 532, 533 are output through the output terminal 76b.
.., 53p, and decoding processing is switched here.

Next, FIG. 28 shows an example in which the embodiment shown in FIG. 1 is partially modified. That is, this is an image signal output from the switch circuit 14 to the video decoder DS.
The video decoder DSP23 from the program memory 33 by supplying it to P23 and guiding it to the signal judging circuit 77 for judging the magnitude of the ghost and controlling the program loader 34 according to the output of this signal judging circuit 77.
The program to be loaded is selected.

FIG. 29 shows a detailed structure of the signal judging circuit 77. That is, reference numeral 77a in the drawing is an input terminal to which the image signal output from the switch circuit 14 is supplied. With respect to the image signal supplied to the input terminal 77a, the timing at which the GCR signal is overlapped is detected by the GCR timing pulse generation circuit 77b. This GC
When the GCR signal is input, the R timing pulse generation circuit 77b generates ramp waveform data for 1H period and outputs it to the ROM 77c. The ROM 77c has a GC
Waveform data defined by the R standard is recorded, and this waveform data is read from the ROM 77c by inputting the ramp waveform data.

Then, the waveform data read from the ROM 77c and the image signal supplied to the input terminal 77a are subtracted by the subtractor 77d, the difference data is passed through the absolute value circuit 77e, and then the adder 77f is added. And 1H by being supplied to a cumulative adder 77h including a latch circuit 77g.
Cumulative over the period. In this case, the GCR timing pulse generation circuit 77b generates a pulse at the start timing of the line in which the GCR signal is overlapped, and this pulse resets the latch circuit 77g of the cumulative adder 77h. After that, the output of the cumulative adder 77h is compared with the comparison circuit 77h.
By being compared with the constant output from the constant generation circuit 77j by i, a ghost determination signal indicating whether or not the ghost has a predetermined amount or more is generated, and is output from the output terminal 77k.

Further, in the program memory 33, as shown in FIG. 30, an NTSC signal basic decoding processing program, a three-dimensional decoding processing program, and a 452
For taps (delay lines T1, T2, T3, T shown in FIG. 11)
4, ..., Tn tap number) ghost removal processing program and a ghost removal processing program for 100 taps having a smaller processing amount than this ghost removal processing program are stored.

Here, the program loader 34 reads out the program from the program memory 33 based on the flowchart shown in FIG.
The program memory 54 of P23 is loaded. First,
The program loader 34 waits for the user to change the receiving channel in step S66, that is, to request the program stored in the program memory 54 to be changed. When the receiving channel is changed, the program loader 34 proceeds to step S67. Then, based on the output of the signal determination circuit 77, it is determined whether the amount of ghost is large or small.

When the amount of ghost is large (YES), the program loader 34 puts the basic decoding process program of the NTSC signal and the 452 taps from the program memory 33 in step S68 in order to focus on the ghost removal process. And a ghost removal processing program for use in the program memory 54,
The processing is returned to the processing of 66. In this case, since the processing amount of the basic decoding process is 9 GOPS and the processing amount of the ghost removing process for 452 taps is 19 GOPS, the total processing amount is 28 GOPS, which does not exceed the maximum processing amount 28 GOPS of the video decoder DSP23. .

When the amount of ghost is small (NO), the program loader 34 puts the three-dimensional decoding processing program and 100 taps from the program memory 33 in step S69 in order to focus on high image quality. The ghost removal processing program is read and loaded into the program memory 54, and the processing returns to step S66.
In this case, the processing amount of the three-dimensional decoding processing is 23 GOPS.
Then, the processing amount of the ghost removal processing for 100 taps is 4.
Since it is 2 GOPS, the total processing amount is 27.2 GOP.
S, and the maximum processing amount of the video decoder DSP23 is 28G.
It never exceeds OPS.

By the way, in the operation of the above-mentioned flowchart, when the user changes the receiving channel, the amount of ghost is first determined, and then the necessary program is loaded into the program memory 54 and the decoding process is performed. It takes time from the change of the receiving channel to the image display.

Therefore, the operation shown in the flow chart of FIG. 32 may be performed. First, in step S70, the program loader 34 changes the reception channel by the user, that is, the program memory 54.
Wait for the change of the program stored in
When the receiving channel is changed, in step S71, the basic decoding processing program of the NTSC signal is unconditionally loaded from the program memory 33 into the program memory 54, and the video decoder DSP23 performs the decoding processing based on this basic decoding processing program. Let

Thereafter, in step S72, the program loader 34 determines whether the amount of ghost is large or small based on the output of the signal judging circuit 77. If the amount of ghost is large (YES), the ghost is removed. In order to focus on the processing, in step S73, the ghost removal processing program for 452 taps is read from the program memory 33 and loaded into the program memory 54, and in step S70.
Returned to the processing of. If the amount of ghost is small (NO), the program loader 34 puts emphasis on high image quality, and in step S74, the program loader 34 reads the three-dimensional decoding processing program from the program memory 33 and the ghost removal processing for 100 taps. The program and are read and loaded into the program memory 54, and the process returns to step S70.

According to the above operation, when the receiving channel is changed, the basic decoding processing program of the NTSC signal is unconditionally loaded and the video decoder DSP2
Since the decoding process is performed by No. 3, the image can be displayed even during the period when the ghost amount is being determined. The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

[0114]

As described above in detail, according to the present invention,
The image signal processing of various broadcasting media can be realized with a simple configuration, and it is possible to provide an extremely favorable image signal processing device which is economically advantageous.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of an image signal processing device according to the present invention.

FIG. 2 is a block configuration diagram showing details of a video decoder DSP of the embodiment.

FIG. 3 is a diagram for explaining an outline of the operation of the video decoder DSP.

FIG. 4 is a block configuration diagram showing details of an ALU of the video decoder DSP.

FIG. 5 is a diagram showing an internal map of a memory added to the same ALU.

FIG. 6 is a flowchart illustrating the four arithmetic operations performed by the same ALU.

FIG. 7 is a flowchart illustrating a one-pixel delay operation by the ALU.

FIG. 8 is a flowchart illustrating a 1H delay operation by the ALU.

FIG. 9 is a block diagram showing an NTSC signal decoding unit by the ALU.

FIG. 10 is a flowchart for explaining the operation of the decoding means.

FIG. 11 is a block configuration diagram showing a ghost removing means by the ALU.

FIG. 12 is a diagram for explaining a MUSE signal.

FIG. 13 is a block configuration diagram showing a decoding unit for a MUSE signal by the ALU.

FIG. 14 is a diagram showing an internal map of a program memory of the video decoder DSP.

FIG. 15 is a diagram for explaining a decoding processing order of the video decoder DSP.

FIG. 16 is a flowchart illustrating an operation of receiving a plurality of television broadcasts.

FIG. 17 is a block diagram showing the encoder side of digital broadcasting.

FIG. 18 is a diagram for explaining a code rate in the digital broadcast.

FIG. 19 is a block diagram showing the decoder side of the digital broadcast.

FIG. 20 is a block configuration diagram showing a digital broadcast decoding means by the ALU.

FIG. 21 is a flowchart for explaining the operation of the decoding means.

FIG. 22 is a block diagram showing a three-dimensional decoding processing unit by the ALU.

FIG. 23 is a diagram showing an internal map of a program memory of the video decoder DSP.

FIG. 24 is a diagram for explaining the processing capability of the video decoder DSP.

FIG. 25 is a flowchart illustrating a program selecting operation according to the processing capacity.

FIG. 26 is a block diagram showing another example of means for loading a program into the program memory of the video decoder DSP.

FIG. 27 is a diagram showing an internal map of a program memory of the video decoder DSP.

FIG. 28 is a block diagram showing another example of the ghost removing means of the embodiment.

FIG. 29 is a block configuration diagram showing a ghost size determination means in the same means.

FIG. 30 is a diagram showing an internal map of a program memory of the video decoder DSP.

FIG. 31 is a flowchart for explaining the operation of the ghost removing means.

FIG. 32 is a flowchart illustrating another example of the operation of the ghost removing means.

[Explanation of symbols]

11 ... Antenna, 12 ... Tuner IF amplifier, 13 ... V
SB / FM demodulator, 14 ... switch circuit, 15 ... QAM
Demodulator, 16, 17 ... Input terminal, 18 ... Output line, 19 ...
A / D converter, 20 ... Audio DSP, 21 ... Output terminal, 2
2 ... Output line, 23 ... Video decoder DSP, 24 ... Error correction circuit, 25 ... Variable length code decoding circuit, 26 ... Output line, 27 ... Synchronous DSP, 28-30 ... Output line, 31 ... Display DSP, 32 ... Output Terminal, 33 ... Program memory,
34 ... Program loader, 35 ... CPU, 36, 37 ...
Ports, 38 ... ROM, 39 ... RAM, 40 ... Input terminals, 41 ... Ports, 421-42n ... Input terminals, 431
... 43n ... Clamp circuit, 441-44n ... A / D converter, 45 ... Switch matrix circuit, 46-48 ... Input terminal, 49 ... Output terminal, 50 ... Input terminal, 511-51
m ... output RAM, 521 to 52m ... shift register,
53 ... Arithmetic unit, 54 ... Program memory, 551-55
p ... memory, 561 to 56m ... shift register, 57 ...
Demultiplexer, 581 to 58m ... Output terminal, 59 ...
Communication bus, 60 ... Program counter, 61 ... Branch control circuit, 62 ... Interrupt vector generation circuit, 63 ... Stack register, 691-697 ... 1H delay line, 701-708
... cumulative adders, 711-717 ... adders, 721-72
7 ... 1 pixel delay line, 731-738 ... Multiplier, 741-
747 ... Adder, 77 ... Signal determination circuit.

Claims (1)

[Claims] 1. An arithmetic means for performing arithmetic processing for decoding input image data based on a signal processing algorithm configured by combining a plurality of programs, and reception of the image data given to this arithmetic means. And a control means for selecting a combination of a plurality of programs to be given to the arithmetic means within a range that does not exceed the maximum signal processing capacity of the arithmetic means, based on the determination result of the determination means. An image signal processing device characterized by the following.