JPH0666843B2 - Common mode noise reduction circuit - Google Patents

Common mode noise reduction circuit

Info

Publication number
JPH0666843B2
JPH0666843B2 JP25189884A JP25189884A JPH0666843B2 JP H0666843 B2 JPH0666843 B2 JP H0666843B2 JP 25189884 A JP25189884 A JP 25189884A JP 25189884 A JP25189884 A JP 25189884A JP H0666843 B2 JPH0666843 B2 JP H0666843B2
Authority
JP
Japan
Prior art keywords
common
circuit
mode
amplifier
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP25189884A
Other languages
Japanese (ja)
Other versions
JPS61131663A (en
Inventor
純二郎 北野
一郎 大日方
敏夫 林
忠勝 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Nippon Telegraph and Telephone Corp filed Critical Hitachi Ltd
Priority to JP25189884A priority Critical patent/JPH0666843B2/en
Publication of JPS61131663A publication Critical patent/JPS61131663A/en
Publication of JPH0666843B2 publication Critical patent/JPH0666843B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04MTELEPHONIC COMMUNICATION
    • H04M3/00Automatic or semi-automatic exchanges
    • H04M3/18Automatic or semi-automatic exchanges with means for reducing interference or noise; with means for reducing effects due to line faults with means for protecting lines
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04MTELEPHONIC COMMUNICATION
    • H04M3/00Automatic or semi-automatic exchanges
    • H04M3/005Interface circuits for subscriber lines

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は電話交換機の加入者回路に用いられる電流供給
回路の同相雑音低減回路に係り、特に電流供給回路の半
導体集積回路化に好適な線路障害時の回路保護を考慮し
た構成の同相雑音低減回路に関する。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a common mode noise reduction circuit of a current supply circuit used in a subscriber circuit of a telephone exchange, and more particularly to a line fault suitable for a semiconductor integrated circuit of the current supply circuit. The present invention relates to a common-mode noise reduction circuit configured in consideration of circuit protection at the time.

〔発明の背景〕[Background of the Invention]

従来の電話交換機の加入者回路は局電源の−48Vから加
入者の電話機に20〜120mA程度の電流を供給する。した
がって電話機と直結する電流供給回路では高電圧・大電
流を扱うので、レターコイルなどの電磁部品が用いられ
ていて電子化が遅れていた。さらに電子化した場合も線
路に誘起する同相雑音電圧を十分抑圧するために電流供
給回路の同相インピーダンスを十分下げる必要がある。
このため線路障害時に電流供給回路に過大電流が流れて
回路の電力損失が増大することから半導体集積回路化し
にくい問題点があった。
The subscriber circuit of a conventional telephone exchange supplies current of about 20 to 120 mA to the subscriber's telephone from -48V of the station power supply. Therefore, since the current supply circuit directly connected to the telephone handles high voltage and large current, electromagnetic components such as a letter coil are used, and electronicization has been delayed. Further, in the case of electronization, it is necessary to sufficiently reduce the common mode impedance of the current supply circuit in order to sufficiently suppress the common mode noise voltage induced in the line.
For this reason, there is a problem that it is difficult to form a semiconductor integrated circuit because an excessive current flows in the current supply circuit at the time of line failure and the power loss of the circuit increases.

〔発明の目的〕[Object of the Invention]

本発明の目的は上記した従来技術の問題点を解決し、線
路障害時の電力損失を制限して半導体集積回路化を容易
にした電流供給回路の同相雑音低減回路を提供するにあ
る。
An object of the present invention is to provide a common mode noise reduction circuit for a current supply circuit that solves the above-mentioned problems of the prior art and limits the power loss at the time of line failure to facilitate the integration into a semiconductor integrated circuit.

〔発明の概要〕[Outline of Invention]

本発明は、通常は平衡線路の同相電圧を検出する同相電
圧検出器と同相電圧を増幅する同相増幅器と同相増幅器
で駆動される平衡出力増幅器の回路で十分な同相負帰還
をかけることにより同相モードインピーダンスを下げて
同相雑音を抑圧し、線路障害時には過大な同相入力信号
を同相入力保護回路でバイパスして同相増幅器の入力を
制限することにより平衡出力増幅器の出力電流を制限
し、さらに線路障害が著しくてさらに電流制限が必要な
場合には外部信号により制御される同相遮断回路で同相
増幅器の動作を停止するようにして、同相入力保護回路
と同相遮断回路の少なくとも一方により線路障害時の過
電流保護を行ない回路の電力損失を抑制して半導体集積
回路化可能にした電流供給回路の同相雑音低減回路であ
る。
In the present invention, a common-mode voltage detector for detecting a common-mode voltage of a balanced line, a common-mode amplifier for amplifying the common-mode voltage, and a circuit for a balanced output amplifier driven by the common-mode amplifier are used to perform a sufficient common-mode negative feedback to perform common-mode operation. The impedance is lowered to suppress common mode noise, and when a line fault occurs, an excessive common mode input signal is bypassed by the common mode input protection circuit to limit the input of the common mode amplifier to limit the output current of the balanced output amplifier. If a significant current limit is required, the common-mode cutoff circuit controlled by an external signal is used to stop the operation of the common-mode amplifier, and at least one of the common-mode input protection circuit and the common-mode cutoff circuit causes overcurrent at line fault. It is a common mode noise reduction circuit of a current supply circuit which is protected and suppresses power loss of the circuit and can be made into a semiconductor integrated circuit.

〔発明の実施例〕Example of Invention

以下に本発明の実施例を第1図ないし第3図により説明
する。第1図は本発明による電流供給回路の同相雑音低
減回路の一実施例を示す回路図である。
An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a circuit diagram showing an embodiment of a common mode noise reduction circuit of a current supply circuit according to the present invention.

第1図において、1は電流ソース形の増幅器でオペアン
プOPBとトランジスタQ1と抵抗R1〜R3よりなり、2は電
流シンク形の増幅器でオペアンプOPAとトランジスタQ2
と抵抗R6〜R8よりなり、該増幅器1,2で平衡出力増幅器
を構成して、平衡線路のB線側BとA線側Aに接続され
る電話機TELに信号電流を供給する。またA1,A2はそれぞ
れ2つの出力O1,O2を持ち入力電流に比例した電流出力
を出すカレントミラーで、第2図にカレントミラーA1,A
2の具体的な構成を示す詳細回路図を例示するように、A
1は電流ソース形でトランジスタQ11〜Q13と抵抗R12〜R1
4よりなり、A2は電流シンク形でトランジスタQ14〜Q16
と抵抗R15〜R17よりなり、かつB1,B2もそれぞれ1つの
出力を持つほかA1,A2と同様のカレントミラーであっ
て、上記B線側Bの電圧を抵抗R4と該カレントミラーA1
で検出しかつカレントミラーB1で電流反転し上記増幅器
1に加える負帰還回路を構成してB線側のインピーダン
スを定め、同様に上記A線側Aの電圧を抵抗R5とカレン
トミラーA2で検出しかつカレントミラーB1で電流反転し
上記増幅器2に加える負帰還回路を構成してA線側のイ
ンピーダンスを定める。
In FIG. 1, reference numeral 1 is a current source type amplifier, which includes an operational amplifier OPB, a transistor Q1, and resistors R1 to R3, and 2 is a current sink type amplifier, which is an operational amplifier OPA and a transistor Q2.
And the resistors R6 to R8, the amplifiers 1 and 2 constitute a balanced output amplifier, and supply a signal current to the telephone TEL connected to the B line side B and the A line side A of the balanced line. A1 and A2 are current mirrors that have two outputs O1 and O2, respectively, and output a current output proportional to the input current.
As illustrated in the detailed circuit diagram showing the specific configuration of 2, A
1 is a current source type and transistors Q11 to Q13 and resistors R12 to R1
4 and A2 is a current sink type transistor Q14 to Q16
A current mirror similar to A1 and A2 except that B1 and B2 each have one output, and the voltage on the B line side B is applied to the resistor R4 and the current mirror A1.
The negative feedback circuit which detects the current at the current mirror B1 and inverts the current at the current mirror B1 is added to the amplifier 1 to determine the impedance on the B line side. Similarly, the voltage on the A line side A is detected by the resistor R5 and the current mirror A2. Moreover, a current is inverted by the current mirror B1 to form a negative feedback circuit which is added to the amplifier 2 to determine the impedance on the A line side.

なおこのままの電流供給回路では同相インピーダンスが
差動インピーダンスと同じ値であって同相雑音が低減さ
れないため、同相信号を検出して同相信号に対してのみ
大量の負帰還をかけけ同相インピーダンスを大幅に低下
する同相雑音低減回路を付加する。すなわち平衡線路に
生じる同相電流icで差動電流idとすると、上記カレント
ミラーの機能によりカレントミラーA1,A2の出力O1には
第1図に示すように差動電流idは打ち消し合って同相電
流icは加算し合う向きに流れることから同相信号を検出
する同相電圧検出回路を構成し、この同相信号は同相増
幅器4に入力する。該同相増幅器4は電流シンク入力に
対し相補出力を平衡出力増幅器1,2に供給するトランジ
スタQ5,Q6、抵抗R10と電流ソース入力に対し相補出力を
平衡出力増幅器1,2に供給するトランジスタQ3,Q4、抵抗
R9とこれらのトランジスタQ3〜Q6に歪防止用のバイアス
電流を供給するダイオードD2〜D5、ツェナーダイオード
D1、抵抗R11、定電流源I1より構成される。また3は同
相入力保護回路でトランジスタQ7,Q8よりなり、該トラ
ンジスタQ7,Q8のベースは同相増幅器4のバイアス発生
用のダイオードD2〜D5の中点に接続されているため通常
動作時には遮断していて同相入力の過大時のみ動作する
ことにより、線路障害時に上記の同相電圧検出器に大き
な検出電流が発生して同相増幅器4でさらに増幅された
のち平衡出力増幅器1,2を過大に駆動して該増幅器1,2に
過大電流が流れ電力損失が異常に増加するのを電流制限
して回路保護する。さらに5は同相遮断回路でトランジ
スタQ9,Q10とこれを駆動するカレントミラーC1,C2と電
流源I2とスイッチSWよりなり、カレントミラーC1,C2は
上記カレントミラーB1,B2と同様に機能し、スイッチSW
は外部制御により当該同相遮断回路5を動作させる場合
にオンして、線路障害がさらに著しい場合に同相増幅器
4の動作を停止させより徹底した回路保護を行なうべく
構成される。
In the current supply circuit as it is, since the common mode impedance is the same value as the differential impedance and the common mode noise is not reduced, the common mode signal is detected and a large amount of negative feedback is applied only to the common mode signal to obtain the common mode impedance. Add a common-mode noise reduction circuit that significantly reduces it. That is, assuming that the differential current id is the in-phase current ic generated in the balanced line, the differential current id is canceled by the output O1 of the current mirrors A1 and A2 due to the function of the current mirror as shown in FIG. Flow in the direction of addition and form an in-phase voltage detection circuit that detects an in-phase signal, and this in-phase signal is input to the in-phase amplifier 4. The common-mode amplifier 4 includes transistors Q5 and Q6 which supply complementary outputs to the current sink inputs to the balanced output amplifiers 1 and 2, and a transistor Q3 which supplies complementary outputs to the balanced output amplifiers 1 and 2 to the resistor R10 and the current source input. Q4, resistance
Diodes D2 to D5 and Zener diode that supply bias current for distortion prevention to R9 and these transistors Q3 to Q6
It is composed of D1, resistor R11, and constant current source I1. Reference numeral 3 is an in-phase input protection circuit, which is composed of transistors Q7 and Q8. Since the bases of the transistors Q7 and Q8 are connected to the middle point of the bias generating diodes D2 to D5 of the in-phase amplifier 4, they are cut off during normal operation. By operating only when the common mode input is too large, a large detection current is generated in the above common mode voltage detector at the time of line failure and further amplified by the common mode amplifier 4, and then the balanced output amplifiers 1 and 2 are driven excessively. The circuit protection is performed by limiting the current that an excessive current flows through the amplifiers 1 and 2 to increase the power loss abnormally. Further, reference numeral 5 is an in-phase cutoff circuit comprising transistors Q9 and Q10, current mirrors C1 and C2 for driving them, a current source I2 and a switch SW. The current mirrors C1 and C2 function in the same manner as the current mirrors B1 and B2. SW
Is turned on when the common-mode cutoff circuit 5 is operated by external control, and is stopped to stop the operation of the common-mode amplifier 4 when the line fault is more serious, thereby performing more thorough circuit protection.

上記の構成で、通常動作時には上記同相電圧検出器で検
出された平衡線路の同相信号が同相増幅器4で十分に増
幅されて平衡出力増幅器1,2に大量の同相帰還がかけら
れることにより、同相インピーダンスが十分に低下して
同相雑音は十分に抑圧され高品質の信号伝達が行なわれ
る。しかし線路障害時たとえばA線地絡時にはカレント
ミラーA2の出力O1が過大出力になって同相増幅器4のト
ランジスタQ4,Q3のコレクタ電流が過大になり、抵抗R9
の電圧降下が同相入力保護回路3のトランジスタQ7の順
方向ベース・エミッタ間電圧VBE(VBE0.7V)より大き
くなるとトランジスタQ7が動作して、トランジスタQ3,Q
4のコレクタ電流をVBE/R9(ただしR9は抵抗R9の抵抗
値)以下に電流制限する。また線路障害時たとえばB線
の電池VBBに接触時には同様にして同相入力保護回路3
のトランジスタQ8の動作によりトランジスタQ5,Q6のコ
レクタ電流がVBE/R10以下に電流制限される。このよう
にして同相増幅器4の出力は一定値以下に制限されるの
で、平衡出力増幅器1,2の出力電流も対応する一定値以
下に電流制限されて電力損失が一定値以下に制限され回
路保護される。しかしながらさらに著しい線路障害時た
とえば線路の電力線との混触時には、同相遮断回路5の
スイッチSWを外部制御によりオンすることにより、トラ
ンジスタQ9,Q10がオンすると同相増幅器4のバイアス発
生用のダイオードD2,D3間とD4,D5間が短絡されるためト
ランジスタQ3〜Q6が遮断するとともに、通常時にトラン
ジスタQ3〜Q6を駆動していた同相入力信号が同相入力保
護回路3のトランジスタQ7またはQ8を流れるため、カレ
ントミラーA1,A2の出力O1が飽和することなく同相信号
を遮断してより徹底した回路保護が行なわれる。
With the above-mentioned configuration, in the normal operation, the common-mode signal of the balanced line detected by the common-mode voltage detector is sufficiently amplified by the common-mode amplifier 4 and a large amount of common-mode feedback is applied to the balanced output amplifiers 1 and 2, The common mode impedance is sufficiently reduced, common mode noise is sufficiently suppressed, and high quality signal transmission is performed. However, at the time of a line fault, for example, when the A line is grounded, the output O1 of the current mirror A2 becomes an excessive output, the collector currents of the transistors Q4 and Q3 of the common-mode amplifier 4 become excessive, and the resistor R9
When the voltage drop of V becomes larger than the forward base-emitter voltage V BE (V BE 0.7V) of the transistor Q7 of the common mode input protection circuit 3, the transistor Q7 operates and the transistors Q3, Q
Limit the collector current of 4 to V BE / R9 (where R9 is the resistance of resistor R9) or less. Also, in the case of a line failure, for example, when the battery V BB of the B line is contacted, the common mode input protection circuit 3 is similarly provided.
By the operation of the transistor Q8, the collector current of the transistors Q5 and Q6 is current limited to V BE / R10 or less. In this way, the output of the common-mode amplifier 4 is limited to a certain value or less, so that the output currents of the balanced output amplifiers 1 and 2 are also current-limited to the corresponding certain value or less and the power loss is limited to a certain value or less to protect the circuit. To be done. However, in the case of a more significant line failure, for example, when the lines are in contact with the power line, the switch SW of the common mode cutoff circuit 5 is turned on by an external control to turn on the transistors Q9 and Q10. And Q4 to D5 are short-circuited, the transistors Q3 to Q6 are cut off, and the in-phase input signal that normally drives the transistors Q3 to Q6 flows through the transistor Q7 or Q8 of the in-phase input protection circuit 3. The output O1 of the mirrors A1 and A2 is not saturated, and the in-phase signal is cut off to perform more thorough circuit protection.

なお上記実施例の第1図の各回路要素の構成において種
々の変形が可能である。たとえば第3図は第1図の同相
増幅器4および同相遮断回路5の他の実施例を示す回路
図である。第3図において、第1図と同一符号または記
号は同一または相当部分を示すものとし、Q′〜Q′
はダーリントン接続されたトランジスタ対、D′
D′は同じくダーリントン接続されたトランジスタ
対、I3,I4は電流源である。この構成で、同相増幅器4
の相補出力の相対精度を向上させるために第1図のトラ
ンジスタQ3〜Q6をダーリントン接続されたトランジスタ
対Q′〜Q′に効果的におきかえ、これとともに第
1図のバイアス発生用ダイオードD2〜D5もダーリントン
接続されたトランジスタ対D′〜D′で等価的にダ
イオード構成にするほか、同相遮断回路5のトランジス
タQ9,Q10の駆動を第1図の1つの定電流源I2によらずに
2つの定電流源I3,I4で別々に駆動するようにしてい
る。
Various modifications can be made to the configuration of each circuit element in FIG. 1 of the above embodiment. For example, FIG. 3 is a circuit diagram showing another embodiment of the in-phase amplifier 4 and the in-phase cutoff circuit 5 of FIG. In FIG. 3, the same symbols or symbols as in FIG. 1 indicate the same or corresponding portions, and Q ′ 3 to Q ′.
5 is a transistor pair connected in Darlington, D' 2 ~
D' 5 is also a Darlington-connected transistor pair, and I 3 and I 4 are current sources. With this configuration, the common-mode amplifier 4
Replaced with transistor pairs Q '3 ~Q' 6 that the transistor Q 3 to Q 6 of Figure 1 in Darlington connected in order to improve the relative accuracy of the complementary outputs of the effective, which together with the bias generator of Figure 1 The diodes D 2 to D 5 are also equivalently diode-configured by the Darlington-connected transistor pair D ′ 2 to D ′ 5 , and the transistors Q 9 and Q 10 of the common-mode cutoff circuit 5 are driven by one of the circuits shown in FIG. The two constant current sources I 3 and I 4 are separately driven instead of the constant current source I 2 .

以上のように上記実施例によれば、電流供給回路の同相
雑音低減回路に同相増幅器の入力過大時に入力同相信号
バイパス路を形成する同相入力保護回路および同相増幅
器の動作を外部制御により停止する同相遮断回路を付加
することにより、線路障害時に上記同相入力保護回路と
同相遮断回路の少なくとも一方により電流供給回路の平
衡出力増幅器が過大に駆動されるのを容易かつ正確に防
止できる。
As described above, according to the above embodiment, the operations of the common mode input protection circuit and the common mode amplifier that form the input common mode signal bypass path in the common mode noise reduction circuit of the current supply circuit when the input of the common mode amplifier is excessive are stopped by the external control. By adding the common mode cutoff circuit, it is possible to easily and accurately prevent the balanced output amplifier of the current supply circuit from being excessively driven by at least one of the common mode input protection circuit and the common mode cutoff circuit at the time of a line failure.

〔発明の効果〕〔The invention's effect〕

以上の説明にように本発明によれば、同相雑音低減回路
を電流供給回路に付加したことによる線路障害時の電力
損失の異常増加を防止できるので、高品質な伝送品質を
もつ電流供給回路を半導体集積回路化可能にする効果が
ある。
As described above, according to the present invention, it is possible to prevent an abnormal increase in power loss at the time of a line failure due to the addition of the common mode noise reduction circuit to the current supply circuit. This has the effect of enabling semiconductor integrated circuits.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明による電流供給回路の同相雑音低減回路
の一実施例を示す回路図、第2図は第1図のカレントミ
ラーA1,A2の詳細回路図、第3図は第1図の同相増幅器
および同相遮断器の他の実施例を示す回路図である。 1,2……平衡出力増幅器 3……同相入力保混回路、4……同相増幅器 5……同相遮断器 A1,A2,B1,B2,C1,C2……カレントミラー TEL……電話機、A……A線 B……B線、I1〜I4……定電流源 VBB……電池、Q1〜Q10……トランジスタ R1〜R11……抵抗、D1……ツェナーダイオード D2〜D5……ダイオード Q′〜Q′……ダーリントン接続されたトランジス
タ対 D′〜D′……ダイオード機能のダーリントン接続
されたトランジスタ対
FIG. 1 is a circuit diagram showing an embodiment of a common mode noise reduction circuit of a current supply circuit according to the present invention, FIG. 2 is a detailed circuit diagram of the current mirrors A1 and A2 of FIG. 1, and FIG. 3 is of FIG. It is a circuit diagram which shows another Example of an in-phase amplifier and an in-phase circuit breaker. 1,2 …… Balanced output amplifier 3 …… In-phase input mixing circuit 4 …… In-phase amplifier 5 …… In-phase circuit breaker A1, A2, B1, B2, C1, C2 …… Current mirror TEL …… Telephone, A… … A line B …… B line, I1 to I4 …… Constant current source V BB …… Battery, Q 1 to Q 10 …… Transistor R 1 to R 11 …… Resistance, D1 …… Zener diode D2 to D5 …… diode Q '3 ~Q' 6 ...... Darlington-connected transistor pair D '2 ~D' 5 Darlington-connected transistor pair ...... diode function

───────────────────────────────────────────────────── フロントページの続き (72)発明者 林 敏夫 神奈川県厚木市小野1839番地 日本電信電 話公社厚木電気通信研究所内 (72)発明者 木村 忠勝 神奈川県厚木市小野1839番地 日本電信電 話公社厚木電気通信研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshio Hayashi 1839 Ono, Atsugi City, Kanagawa Pref., Atsugi Electro-Communications Research Laboratories, Nippon Telegraph and Telephone Corp. Atsugi Research Institute of Electrical Communication

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】平衡線路に信号電流を供給する電流供給回
路において、上記平衡線路に誘起する同相電圧を検出す
る同相電圧検出器と、該同相電圧を入力し増幅する同相
増幅器と、該同相増幅器より駆動を受け上記平衡線路を
駆動する平衡出力増幅器と、上記同相増幅器の入力過大
時に所定値を起えると該入力同相信号をバイパスするバ
イパス路を形成する同相入力保護回路と、上記同相増幅
器の動作を外部制御により停止する同相遮断回路とを備
え、平衡線路の障害時に上記同相入力保護回路と同相遮
断回路の少なくとも一方により上記平衡出力増幅器が過
大に駆動されるのを防止するように構成したことを特徴
とする同相雑音低減回路。
1. A current supply circuit for supplying a signal current to a balanced line, a common-mode voltage detector for detecting a common-mode voltage induced in the balanced line, a common-mode amplifier for inputting and amplifying the common-mode voltage, and the common-mode amplifier. A balanced output amplifier which is driven to drive the balanced line; an in-phase input protection circuit which forms a bypass path for bypassing the input in-phase signal when a predetermined value is generated when the input of the in-phase amplifier is excessive; and the in-phase amplifier. And a common-mode cutoff circuit that stops the operation of the above-mentioned by external control, and is configured to prevent the balanced output amplifier from being excessively driven by at least one of the common-mode input protection circuit and the common-mode cutoff circuit when the balanced line fails. A common-mode noise reduction circuit characterized by the above.
JP25189884A 1984-11-30 1984-11-30 Common mode noise reduction circuit Expired - Lifetime JPH0666843B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25189884A JPH0666843B2 (en) 1984-11-30 1984-11-30 Common mode noise reduction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25189884A JPH0666843B2 (en) 1984-11-30 1984-11-30 Common mode noise reduction circuit

Publications (2)

Publication Number Publication Date
JPS61131663A JPS61131663A (en) 1986-06-19
JPH0666843B2 true JPH0666843B2 (en) 1994-08-24

Family

ID=17229591

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25189884A Expired - Lifetime JPH0666843B2 (en) 1984-11-30 1984-11-30 Common mode noise reduction circuit

Country Status (1)

Country Link
JP (1) JPH0666843B2 (en)

Also Published As

Publication number Publication date
JPS61131663A (en) 1986-06-19

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