JPH0666523B2 - Semiconductor optical memory - Google Patents

Semiconductor optical memory

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Publication number
JPH0666523B2
JPH0666523B2 JP62010815A JP1081587A JPH0666523B2 JP H0666523 B2 JPH0666523 B2 JP H0666523B2 JP 62010815 A JP62010815 A JP 62010815A JP 1081587 A JP1081587 A JP 1081587A JP H0666523 B2 JPH0666523 B2 JP H0666523B2
Authority
JP
Japan
Prior art keywords
semiconductor
type semiconductor
base
layer
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62010815A
Other languages
Japanese (ja)
Other versions
JPS63179318A (en
Inventor
健一 笠原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62010815A priority Critical patent/JPH0666523B2/en
Priority to DE8787118935T priority patent/DE3782232T2/en
Priority to EP87118935A priority patent/EP0273344B1/en
Priority to CA000554905A priority patent/CA1271549A/en
Priority to US07/136,588 priority patent/US4829357A/en
Publication of JPS63179318A publication Critical patent/JPS63179318A/en
Publication of JPH0666523B2 publication Critical patent/JPH0666523B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は画像処理や光コンピュータ等に必要とされる半
導体光メモリに関する。
The present invention relates to a semiconductor optical memory required for image processing, an optical computer, and the like.

(従来の技術とその問題点) 微少なトリガ光によってレーザ発振をおこし、トリガ光
が無くなった後でも発振し続ける機能を備えた、半導体
光メモリは、これからの光交換や、並列光情報処理シス
テムを構成する際に不可欠なキー・デバイスである。こ
の様な機能を有するデバイスとしては双安定半導体レー
ザが知られており、昭和60年通信学会総合全国大会886
などに詳細が報告されている。双安定半導体レーザの問
題点は〜数、100μw程度の比較的強い強度のトリガ光
が必要なことであった。双安定半導体レーザをトリガ光
でONさせるには、光をレンズを通してレーザ端面に照射
し、効率良く、非励起状態にある活性層に絞り込んでや
る必要がある。活性層の幅と厚みはそれぞれ約1μm,0.
1μmと狭く、効率良い光結合は困難であった。そのた
めに挿入損失が大きくなり、相対的にトリガ強度は高い
値が必要とされるようになる。また、光並列処理等への
応用を考えると、層厚方向にトリガ光を受けられるよう
な構造が望ましい。
(Prior art and its problems) The semiconductor optical memory, which has a function to oscillate a laser beam with a slight amount of trigger light and continue to oscillate even after the trigger light is exhausted, is designed for future optical switching and parallel optical information processing systems. It is an indispensable key device for configuration. A bistable semiconductor laser is known as a device having such a function.
Details have been reported. The problem with the bistable semiconductor laser is that it requires a relatively strong trigger light of about several to 100 μw. In order to turn on the bistable semiconductor laser with the trigger light, it is necessary to irradiate the laser end face with the light through the lens and efficiently narrow it down to the active layer in the non-excited state. The width and thickness of the active layer are approximately 1 μm and 0.
It was as narrow as 1 μm, and efficient optical coupling was difficult. Therefore, the insertion loss becomes large, and a relatively high trigger strength is required. Further, in consideration of application to optical parallel processing and the like, a structure capable of receiving trigger light in the layer thickness direction is desirable.

(問題点を解決するための手段) 前述の問題点を解決するために本発明が提供する半導体
光メモリは、pnpnサイリスタからなり、ベース用n型半
導体は第1の半導体層、第2の半導体層および第3の半
導体層を順に積層してなり、アノード用p型半導体およ
びカソード用n型半導体の禁制帯幅は前記第1および第
3の半導体層のいずれの禁制帯幅より大きく、前記第2
の半導体層の禁制帯幅は前記第1及び第3の半導体層の
禁制帯幅より狭く、順方向導通状態時に電子と正孔を前
記第2の半導体層中に緩和させ、その電子と正孔の誘導
放出過程によってレーザ発振を起こさせることを特徴と
する。
(Means for Solving Problems) A semiconductor optical memory provided by the present invention in order to solve the above problems comprises a pnpn thyristor, and the base n-type semiconductor is a first semiconductor layer and a second semiconductor layer. And a third semiconductor layer are sequentially stacked, and the forbidden band widths of the p-type semiconductor for anode and the n-type semiconductor for cathode are larger than the forbidden band width of either of the first and third semiconductor layers.
The band gap of the semiconductor layer is narrower than the band gaps of the first and third semiconductor layers, and electrons and holes are relaxed in the second semiconductor layer during the forward conduction state, and the electrons and holes are Laser oscillation is caused by the stimulated emission process of.

(発明の作用と原理) 第1図および第2図は本発明の原理を示すバンド図、第
3図は動作図である。
(Operation and Principle of the Invention) FIGS. 1 and 2 are band diagrams showing the principle of the present invention, and FIG. 3 is an operation diagram.

第1図(a)はバイアス電圧がかかっていない状態、同
図(b)は高インピーダンス状態、同図(c)はON状態
のバンド図である。簡単のためにヘテロ接合でのバンド
不連続等、本発明の本質に関わりないところは定性的に
近似を施して示した。第1図(a)に各層のキャリア濃
度と禁制帯エネルギーを示してある。アノード用p型半
導体,カソード用n型半導体の禁制帯幅はそれぞれE
とEで示されている(図ではE=E)。ベ
ース用のn型半導体層は禁制帯幅EがEとE
の2つの半導体から構成されている。このうちE
の層がレーザ動作用の活性層となる。禁制帯幅の
大小関係はE,E>E>Eとなるようにす
る。ベース用のn型半導体層のキャリア濃度(n
)は充分、低濃度にしておく。アノードに正,カ
ソードに負の電圧を印加していくと、始めのうちは電流
が殆ど流れない高インピーダンス状態となる(第1図
(a))。ベース用のn型半導体層が低濃度であるの
で、印加電圧は殆どベース領域のp−n接合にかかり、
空乏層はベース用n型半導体層中に伸びていく。アノー
ド用p型半導体中の正孔はベース,アノード間のp−n
接合に生じているポテンシャル障壁を越えられず、その
ために、電流が殆ど流れない高インピーダンス状態が生
じる。更に印加電圧を増大させていき、第3図(a)に
示したブレークオーバ電圧(VBO)を越えると、急に電
流が流れ始め、ON状態になる(第1図(c))。この辺
の動作メカニズムは通常のサイリスタと同じである。ON
状態でこの素子にかかる電圧は、実質的に1個のp−n
接合と同じになる。ベース用n型半導体中に禁制帯幅の
狭い半導体層(E=E)を設けておくと、電子と
正孔の一部はこのポテンシャルの窪みに落ち込む。外部
に反射鏡を置いておけば、利得が損失を上回ったところ
でレーザ発振が得られる。カソード用n型半導体とアノ
ード用p型半導体の禁制帯幅をベース用n型半導体のそ
れよりも大きくしておけば、ON状態のときにアノードに
流れ出す電子とカソードに流れ出す正孔の数を減らすこ
とができ、活性層中にキャリアを緩和させやすくなる。
従って発光効率を高めることができる。第3図(a)で
示したV=Vの点に電圧を設定しておき、適当な光
量の光を入射させ、これをベース用n型半導体で吸収さ
せる。そうすると正孔がベース用p型半導体に注入され
ることになる。注入された正孔はトランジスタ効果でこ
の層を通過する電子を増やす。この電子はベース用n型
半導体に生じているポテンシャルの傾きを緩やかにす
る。そうするとアノードからベースに注入される正孔が
増える。この正のフィードバック効果でこの素子を高イ
ンピーダンス状態からON状態に移行させることができ
る。即ち、第3図(b)で示した様に、トリガ光でこの
素子をレーザ発振させることができる。VをVBO
近づける程トリガ感度を高めることができる。E
の半導体層をわざわざ設けずに、始めからベース
用n型半導体層を一層として通常の半導体レーザの活性
層厚なみ(0.1μm)にして、禁制帯幅を小さくして
おけば良いと考えられるかもしれないが、それは駄目で
ある。何故ならば、トリガ光の吸収が0.1μm程度の厚
さでは小さいのでトリガ感度が低下してしまうからであ
る。
FIG. 1A is a band diagram in which no bias voltage is applied, FIG. 1B is a high impedance state, and FIG. 1C is an ON state band diagram. For simplification, the band discontinuity at the heterojunction and the like, which are not related to the essence of the present invention, are qualitatively approximated. FIG. 1 (a) shows the carrier concentration and the forbidden band energy of each layer. The forbidden band width of the p-type semiconductor for the anode and the n-type semiconductor for the cathode is E, respectively.
4 and E 1 (E 4 = E 1 in the figure). The n-type semiconductor layer for the base has a forbidden band width E g of E 3 and E a.
It is composed of two semiconductors. Of these, E g =
The layer of E a becomes the active layer for laser operation. The size of the forbidden band is set to E 4 , E 1 > E 3 > E a . The carrier concentration (n 2 and n a ) of the n-type semiconductor layer for the base is sufficiently low. When a positive voltage is applied to the anode and a negative voltage is applied to the cathode, a high impedance state in which almost no current flows is obtained at the beginning (FIG. 1 (a)). Since the n-type semiconductor layer for the base has a low concentration, the applied voltage is almost applied to the pn junction in the base region,
The depletion layer extends into the base n-type semiconductor layer. Holes in the p-type semiconductor for the anode are pn between the base and the anode.
The potential barrier occurring at the junction cannot be exceeded, which results in a high impedance state in which almost no current flows. When the applied voltage is further increased and the breakover voltage (V BO ) shown in FIG. 3 (a) is exceeded, a current suddenly starts to flow and it is turned on (FIG. 1 (c)). The operation mechanism of this side is the same as that of a normal thyristor. ON
In this state, the voltage applied to this element is substantially one pn
It becomes the same as joining. When a semiconductor layer having a narrow bandgap (E g = E a ) is provided in the base n-type semiconductor, some of the electrons and holes fall into the depression of this potential. If a reflector is placed outside, laser oscillation can be obtained when the gain exceeds the loss. If the forbidden band width of the cathode n-type semiconductor and the anode p-type semiconductor is made larger than that of the base n-type semiconductor, the number of electrons flowing out to the anode and holes flowing out to the cathode in the ON state is reduced. This makes it easier to relax the carriers in the active layer.
Therefore, the luminous efficiency can be improved. A voltage is set at the point of V = V X shown in FIG. 3 (a), an appropriate amount of light is made incident, and this is absorbed by the base n-type semiconductor. Then, holes will be injected into the p-type semiconductor for the base. The injected holes increase the number of electrons passing through this layer due to the transistor effect. These electrons moderate the slope of the potential generated in the base n-type semiconductor. Then, holes injected from the anode to the base increase. This positive feedback effect allows the device to transition from the high impedance state to the ON state. That is, as shown in FIG. 3B, this element can be oscillated by the trigger light. The trigger sensitivity can be increased as V X approaches V BO . E g =
Without providing the semiconductor layer of the E a trouble, in the active layer thickness comparable conventional semiconductor laser a n-type semiconductor layer for the base further and to from the beginning (0.1 [mu] m), considered it is sufficient to reduce the bandgap You may be able to, but it is useless. This is because the absorption of the trigger light is small at a thickness of about 0.1 μm, so that the trigger sensitivity is lowered.

第2図はトリガ感度を高めるために行なった改良素子の
バンド図である。第1図との違いはベース用p型半導体
の層厚を薄くしてあることである。この層厚を薄くし、
例えば外部からの印加電圧が零の状態で空乏化する程に
薄くしておく。そうすると、n(カソード)−p(ベー
ス)−n(ベース)トランジスタの光電流利得が一層、
高まりトリガ感度を高めるために好都合となる。
FIG. 2 is a band diagram of the improved element performed to enhance the trigger sensitivity. The difference from FIG. 1 is that the layer thickness of the base p-type semiconductor is thin. Make this layer thinner,
For example, it is made thin enough to be depleted when the voltage applied from the outside is zero. Then, the photocurrent gain of the n (cathode) -p (base) -n (base) transistor is further increased,
It is convenient to increase the trigger sensitivity.

ジャーナル・オブ・アプライド・フィジックス(J.App
l.Phys.59(2),pp.596〜600,1986)には、第2図の様
にp型ベース半導体の層厚を薄くした光サイリスタの報
告が成されている。この論文によれば〜数μwのトリガ
光で100mA以上の電流をONさせて流すことが可能であ
り、これだけの電流が活性層中に効率よく流れ込めば充
分レーザ発振が可能である。
Journal of Applied Physics (J.App
59 (2), pp. 596-600, 1986), an optical thyristor in which the layer thickness of the p-type base semiconductor is thin as shown in FIG. 2 is reported. According to this paper, it is possible to turn on and pass a current of 100 mA or more with a trigger light of ˜several μw, and if such a current efficiently flows into the active layer, sufficient laser oscillation is possible.

(実施例) 第4図は本発明の一実施例を示す斜視図である。InP系
半導体を用いた1μm帯用の光メモリである。n−InP
基板41にカソード側となるn−InP(厚さd=2μm,n=
2×1018cm−3)42、ベース用p型半導体となるp−In
GaAsP(λg=1.3μm,d=30Å,n=2×1018cm−3)4
3、ベース用n型半導体となるアンドープのn−InGaAsP
(λg=1.3μm,d=1μm,n=5×1015cm−3)44、ア
ンドープのn−In0.53Ga0.47As(d=0.1μm,n=5×10
15cm−3)45、アンドープのn−InGaAsP(λg=1.3μ
m,d=0.3μm,n=5×1015cm−3)46を成長させ、更に
アノードとなるp−InP(d=0.5μm,n=2×1018cm
−3)47とキャップ層用のp−InGaAsP(λg=1.15μ
m,d=0.5μm,n=2×1019cm−3)48とを成長させる。
層44,45,46が第1図(a)のn,n,nにそれぞ
れ対応する。n−InGaAs45が活性層となる。バンド図は
第2図とほぼ同じである。第4図で示したように幅1.5
μmでエッチング加工を施し、上部をストライプ状にす
る。その両側はポリイミド51でおおい、活性層とその両
脇との屈折率差を小さくすることによって横モードの制
御をする。ポリイミドコートはパッシベーションの役割
も果たす。へき開で共振面を形成する。共振器長は100
μmである。バイアス電圧を調整することにより、数10
μwのトリガ光でレーザ発振を起こさせ、数mwの出力を
得ることができた。
(Embodiment) FIG. 4 is a perspective view showing an embodiment of the present invention. It is an optical memory for 1 μm band using InP semiconductor. n-InP
N-InP on the substrate 41 on the cathode side (thickness d = 2 μm, n =
2 × 10 18 cm -3 ) 42, p-In used as p-type semiconductor for base
GaAsP (λg = 1.3μm, d = 30Å, n = 2 × 10 18 cm -3 ) 4
3. Undoped n-InGaAsP that will be the n-type semiconductor for the base
(Λg = 1.3 μm, d = 1 μm, n = 5 × 10 15 cm −3 ) 44, undoped n-In 0.53 Ga 0.47 As (d = 0.1 μm, n = 5 × 10 5
15 cm −3 ) 45, undoped n-InGaAsP (λg = 1.3 μ
m, d = 0.3 μm, n = 5 × 10 15 cm −3 ) 46 is grown, and p-InP (d = 0.5 μm, n = 2 × 10 18 cm) serving as an anode is further grown.
-3 ) 47 and p-InGaAsP for the cap layer (λg = 1.15μ
m, d = 0.5 μm, n = 2 × 10 19 cm −3 ) 48.
Layers 44, 45 and 46 correspond to n 2 , n a and n 2 of FIG. 1 (a), respectively. The n-InGaAs45 serves as an active layer. The band diagram is almost the same as in FIG. Width 1.5 as shown in Figure 4
Etching is performed with a thickness of μm to form a striped upper part. Both sides thereof are covered with polyimide 51, and the transverse mode is controlled by reducing the difference in refractive index between the active layer and both sides thereof. The polyimide coat also serves as passivation. A cleavage plane forms a resonance surface. Resonator length is 100
μm. By adjusting the bias voltage, the number 10
The laser oscillation was generated by the trigger light of μw, and the output of several mw could be obtained.

第5図は本発明の応用例である。本発明になる半導体光
メモリ52の外部に45゜ミラー53をエッチング加工で形成
し、共振面近くに配置しておけば、層厚方向に光がとり
出せる。並列光情報処理への応用で有用である。
FIG. 5 is an application example of the present invention. If a 45 ° mirror 53 is formed on the outside of the semiconductor optical memory 52 according to the present invention by etching and is arranged near the resonance surface, light can be extracted in the layer thickness direction. It is useful for application to parallel optical information processing.

(発明の効果) 以上のように本発明によれば、光を層厚方向に入射、吸
収させる構造となっているのでトリガ光感度の高い光メ
モリが実現できる。
(Effect of the Invention) As described above, according to the present invention, since the structure is such that light is incident and absorbed in the layer thickness direction, an optical memory with high trigger light sensitivity can be realized.

【図面の簡単な説明】[Brief description of drawings]

第1図および第2図は本発明の原理を示すバンド図、第
3図(a)は本発明による半導体メモリの特性図、第3
図(b)はその半導体メモリの入出力信号のタイミング
図、第4図は本発明の一実施例を示す斜視図、第5図は
本発明の一応用例を示す斜視図である。 図に於いて、41はn−InP基板、42はn−InP、43および
48はp−InGaAsP、44及び46はn−InGaAsP、45はn−In
GaAs、47はp−InP、49及び50は電極、51はポリイミ
ド、52は半導体光メモリ、53は45゜ミラーである。
1 and 2 are band diagrams showing the principle of the present invention, FIG. 3 (a) is a characteristic diagram of a semiconductor memory according to the present invention, and FIG.
FIG. 4B is a timing diagram of input / output signals of the semiconductor memory, FIG. 4 is a perspective view showing an embodiment of the present invention, and FIG. 5 is a perspective view showing an application example of the present invention. In the figure, 41 is an n-InP substrate, 42 is an n-InP, 43 and
48 is p-InGaAsP, 44 and 46 are n-InGaAsP, 45 is n-In
GaAs, 47 are p-InP, 49 and 50 are electrodes, 51 is polyimide, 52 is a semiconductor optical memory, and 53 is a 45 ° mirror.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】pnpnサイリスタに於いて、ベース用n型半
導体は第1の半導体層、第2の半導体層および第3の半
導体層を順に積層してなり、アノード用p型半導体およ
びカソード用n型半導体の禁制帯幅は前記第1及び第3
の半導体層のいずれの禁制帯幅より大きく、前記第2の
半導体層の禁制帯幅は前記第1及び第3の半導体層の禁
制帯幅より狭く、順方向導通状態時に電子と正孔を前記
第2の半導体層中に緩和させ、その電子と正孔の誘導放
出過程によってレーザ発振を起こさせることを特徴とす
る半導体光メモリ。
1. In a pnpn thyristor, an n-type semiconductor for a base is formed by laminating a first semiconductor layer, a second semiconductor layer and a third semiconductor layer in this order, and a p-type semiconductor for an anode and an n-type for a cathode. The forbidden band width of the type semiconductor is the above-mentioned first and third
Larger than any of the forbidden band widths of the semiconductor layers, the forbidden band width of the second semiconductor layer is narrower than the forbidden band widths of the first and third semiconductor layers, and the electrons and holes are absorbed in the forward conduction state. A semiconductor optical memory characterized by being relaxed in a second semiconductor layer and causing laser oscillation in the stimulated emission process of electrons and holes.
【請求項2】特許請求の範囲第1項記載の半導体光メモ
リに於いて、光を前記ベース用n型半導体に吸収させる
ことによって順方向導通状態を引き起こすことを特徴と
する半導体光メモリ。
2. The semiconductor optical memory according to claim 1, wherein a forward conduction state is caused by absorbing light in the base n-type semiconductor.
JP62010815A 1986-12-22 1987-01-20 Semiconductor optical memory Expired - Fee Related JPH0666523B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP62010815A JPH0666523B2 (en) 1987-01-20 1987-01-20 Semiconductor optical memory
DE8787118935T DE3782232T2 (en) 1986-12-22 1987-12-21 PNPN THYRISTOR.
EP87118935A EP0273344B1 (en) 1986-12-22 1987-12-21 A pnpn thyristor
CA000554905A CA1271549A (en) 1986-12-22 1987-12-21 Pnpn thyristor
US07/136,588 US4829357A (en) 1986-12-22 1987-12-22 PNPN thyristor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62010815A JPH0666523B2 (en) 1987-01-20 1987-01-20 Semiconductor optical memory

Publications (2)

Publication Number Publication Date
JPS63179318A JPS63179318A (en) 1988-07-23
JPH0666523B2 true JPH0666523B2 (en) 1994-08-24

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JP62010815A Expired - Fee Related JPH0666523B2 (en) 1986-12-22 1987-01-20 Semiconductor optical memory

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JP (1) JPH0666523B2 (en)

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JP2666418B2 (en) * 1988-10-25 1997-10-22 日本電気株式会社 Driving method of pnpn structure

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