JPH0666469B2 - MIS semiconductor device and manufacturing method thereof - Google Patents
MIS semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH0666469B2 JPH0666469B2 JP59086627A JP8662784A JPH0666469B2 JP H0666469 B2 JPH0666469 B2 JP H0666469B2 JP 59086627 A JP59086627 A JP 59086627A JP 8662784 A JP8662784 A JP 8662784A JP H0666469 B2 JPH0666469 B2 JP H0666469B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- impurity
- source
- source region
- channel side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000012535 impurity Substances 0.000 claims description 56
- 238000002513 implantation Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000000034 method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- 230000003213 activating effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 （ａ） 発明の技術分野 本発明は、MIS半導体装置およびその製法方法に係り、
特に、そのソース領域の構成およびその製造方法に関
す。TECHNICAL FIELD OF THE INVENTION The present invention relates to a MIS semiconductor device and a method for manufacturing the same,
In particular, it relates to the structure of the source region and the manufacturing method thereof.
（ｂ） 技術の背景 MIS半導体集積回路装置（IC）において、多くはMIS電界
効果トランジスタ（FET）のソース領域と該MISFETが配
設される半導体基板若しくはウエル領域とが配線層を介
して同電位に接続される。また、該ICが論理回路に使用
される場合には、該MISFETのスイッチング速度の速いこ
とが望まれる。(B) Background of technology In a MIS semiconductor integrated circuit device (IC), in many cases, the source region of a MIS field effect transistor (FET) and the semiconductor substrate or well region in which the MISFET is arranged have the same potential via a wiring layer. Connected to. Further, when the IC is used in a logic circuit, it is desired that the MISFET has a high switching speed.
（ｃ） 従来技術と問題点 第１図はMIS半導体装置の代表例であるCMOSの一般的な
構成の断面を模式的に示した図である。図示において、
1aはn-型シリコン基板、1bはp-型ウエル領域、２は素子
分離用のフィールド酸化膜、3a・3bはそれぞれ素子分離
用のn+型・p+型チャネルストッパ、４はゲート酸化膜、
５は多結晶シリコンゲート電極、6a・6bはそれぞれp+型
・n+型ソース領域、7a・7bはそれぞれp+型・n+型ドレイ
ン領域、8a・8bはそれぞれ基板1a・ウエル1bに電位を与
えるn+形・p+型接続領域、９は不純物ブロック用酸化
膜、10は燐珪酸ガラス（PSG）絶縁膜、11は各領域ない
し電極から導出し所定の接続（図にはソース領域6a、6b
と接続領域8a、8bとをそれぞれ接続しているのを示す）
をする金属配線をそれぞれ示し、基板1a上の領域SaにＰ
−MOSFETがまたウエル領域1b上の領域SbにＮ−MOSFETを
形成している。(C) Prior Art and Problems FIG. 1 is a diagram schematically showing a cross section of a general configuration of a CMOS which is a typical example of a MIS semiconductor device. In the figure,
1a is an n - type silicon substrate, 1b is a p - type well region, 2 is a field oxide film for element isolation, 3a and 3b are n + type and p + type channel stoppers for element isolation, respectively, and 4 is a gate oxide film. ,
5 is a polycrystalline silicon gate electrode, 6a and 6b are p + type and n + type source regions, 7a and 7b are p + type and n + type drain regions, and 8a and 8b are potentials on the substrate 1a and well 1b, respectively. N + type / p + type connection region for providing the impurity, 9 is an impurity blocking oxide film, 10 is a phosphosilicate glass (PSG) insulating film, 11 is a predetermined connection derived from each region or electrode (source region 6a in the figure). , 6b
And connecting areas 8a and 8b are shown respectively)
Showing the metal wirings that perform
The -MOSFET also forms an N-MOSFET in the region Sb on the well region 1b.
この構成をなすCMOSを使用した論理回路例であるインバ
ータの一般的な回路は第２図の如くである。図示におい
てTa・TbはそれぞれＰ−・Ｎ−MOSFET、Ｇはゲート、Ｓ
はソース、Ｄはドレイン、8a・8bはTa・Tbを形成する半
導体領域（それぞれ第１図における基板1a・ウエル領域
1b）、Rsa・RsbはそれぞれTa・Tbのソース抵抗、Rda・R
dbはそれぞれTa・Tbのドレイン抵抗、INは入力端子、OU
Tは出力端子、Vccは電源線、GNDは接地線をそれぞれ示
す。この回路において、論理演算速度を支配するスイッ
チング速度には、ソース抵抗Rsa、Rsb、ドレイン抵抗Rd
a、Rdbなどの抵抗値や、半導体領域Ba、BbとドレインＤ
間の接合容量値、半導体領域Ba、BbとゲートＧ間のゲー
ト容量値などが影響し、前記速度は、前記抵抗値も前記
容量値も小さい程速くなり大きい程遅くなる。そして、
一般に該速度を速くすることが望まれている。なお、半
導体領域Ba、BbはMOSFETTa、Tb内においてそれぞれソー
スＳに接続されている。A general circuit of an inverter, which is an example of a logic circuit using CMOS having this configuration, is as shown in FIG. In the figure, Ta and Tb are P- and N-MOSFETs respectively, G is a gate, and S is
Is a source, D is a drain, and 8a and 8b are semiconductor regions forming Ta and Tb (the substrate 1a and the well region in FIG. 1, respectively).
1b), Rsa / Rsb are the source resistance of Ta / Tb, Rda / R
db is Ta / Tb drain resistance, IN is input terminal, OU
T is an output terminal, Vcc is a power line, and GND is a ground line. In this circuit, the source resistances Rsa, Rsb, and the drain resistance Rd are the switching speeds that control the logical operation speed.
Resistance values such as a and Rdb, semiconductor regions Ba and Bb and drain D
Influenced by the junction capacitance value between them, the gate capacitance value between the semiconductor regions Ba and Bb and the gate G, etc., the speed becomes faster as the resistance value and the capacitance value become smaller, and becomes slower as it becomes larger. And
It is generally desired to increase the speed. The semiconductor regions Ba and Bb are connected to the source S in the MOSFETs Ta and Tb, respectively.
一方、第１図に図示する従来のCMOSにおいて、ソース抵
抗Rsa、Rsbとドレイン抵抗Rda、Rdbの抵抗値は、対応す
るソース領域6a、6bやドレイン領域7a、7bの不純物濃度
に主として支配され、該濃度が高い程該抵抗値が小さく
なる。しかしながら、ソース領域6a、6bとドレイン領域
7a、7bとを形成する際に該濃度を高くすべく不純物を多
く注入することは、該不純物活性化の際のショートチャ
ネル現象発生により制約され、また、接合深さが大きく
なって前記容量値が大きくなる問題がある。On the other hand, in the conventional CMOS shown in FIG. 1, the resistance values of the source resistances Rsa, Rsb and the drain resistances Rda, Rdb are mainly controlled by the impurity concentrations of the corresponding source regions 6a, 6b and drain regions 7a, 7b, The higher the concentration, the smaller the resistance value. However, the source regions 6a and 6b and the drain region
Injecting a large amount of impurities to increase the concentration when forming 7a and 7b is restricted by the occurrence of a short channel phenomenon at the time of activating the impurities, and the junction depth increases to increase the capacitance value. There is a problem that becomes large.
上述した事情は、その内容からして、単にCMOSに限定さ
れるものではなく、MIS半導体装置に共通したものであ
る。The above-mentioned circumstances are not limited to CMOS in terms of their contents, but are common to MIS semiconductor devices.
（ｄ） 発明の目的 本発明の目的は上記従来の問題に鑑み、スイッチング速
度が速く且つ製造においてショートチャネル現象発生の
ないMIS半導体装置の構成とその製造方法を提供するに
ある。(D) Object of the Invention In view of the above conventional problems, an object of the present invention is to provide a structure of a MIS semiconductor device which has a high switching speed and does not cause a short channel phenomenon in manufacturing, and a manufacturing method thereof.
（ｅ） 発明の構成 上記目的は、基板若しくはウエル領域よりなる半導体領
域に形成され該半導体領域と同電位に保持されるべきソ
ース領域の，チャネル側から離れた部分の該ソース領域
の不純物濃度が，チャネル側と接する部分の該ソース領
域の不純物濃度より高濃度であり，かつドレイン領域の
不純物濃度が前記ソース領域のチャネル側と接する部分
の不純物濃度と同程度であることを特徴とするMIS半導
体装置によって達成され、また、ソース形成領域とドレ
イン形成領域とに同時に不純物を注入する第一の不純物
注入工程と，該ソース形成領域のチャネル側部分を除い
た領域に該不純物と同一導電型不純物を，第一の不純物
注入と同じ程度の濃度で注入する第二の不純物注入工程
とを有して，該ソース領域のチャネル側から離れた部分
の不純物濃度が，該ソース領域のチャネル側部分の不純
物濃度より高濃度であるソース領域を形成することを特
徴とするMIS半導体装置の製造方法によって達成され
る。(E) Configuration of the Invention The above-mentioned object is to improve the impurity concentration of the source region at a portion distant from the channel side of the source region which is formed in the semiconductor region formed of the substrate or the well region and should be held at the same potential as the semiconductor region. A MIS semiconductor characterized by having a higher concentration than the impurity concentration of the source region in the portion in contact with the channel side, and having an impurity concentration in the drain region which is approximately the same as the impurity concentration in the portion in contact with the channel side of the source region. And a first impurity implantation step of implanting an impurity into a source formation region and a drain formation region at the same time, and an impurity of the same conductivity type as the impurity in a region of the source formation region excluding a channel side portion. , A portion of the source region away from the channel side, which has a second impurity implantation step of implanting at a concentration similar to that of the first impurity implantation. Impurity concentration, is achieved by the method for producing a MIS semiconductor device, and forming a source region is higher concentration than the impurity concentration of the channel portion of the source region.
前記ソース領域の不純物濃度が、前記ドレイン領域の不
純物濃度即ち従来のソース領域の不純物濃度より高濃度
であることから、当該ソース領域の抵抗値が低減して前
記MIS半導体装置のスイッチング速度が速くなり、然
も、当該ソース領域のチャネル側部分は第二の不純物注
入工程による不純物注入がないので、不純物の活性化に
際してショートチャネル現象を発生することはない。な
お、ソース領域の接合面積は増加するが、該増加は、ソ
ース領域が基板若しくはウエル領域と同電位に形成され
るため接合容量を増加させることがないので、前記スイ
ッチング速度を遅くする要因にならない。Since the impurity concentration of the source region is higher than the impurity concentration of the drain region, that is, the impurity concentration of the conventional source region, the resistance value of the source region is reduced and the switching speed of the MIS semiconductor device is increased. Of course, since no impurity is injected into the channel side portion of the source region by the second impurity injection step, the short channel phenomenon does not occur when the impurities are activated. Although the junction area of the source region increases, the increase does not increase the junction capacitance because the source region is formed at the same potential as the substrate or the well region, and therefore does not become a factor that slows the switching speed. .
（ｆ） 発明の実施例 以下本発明の実施例を図により説明する。全図を通じ同
一符号は同一対象物を示す。(F) Embodiments of the Invention Embodiments of the present invention will be described below with reference to the drawings. The same reference numerals denote the same objects throughout the drawings.
第３図はCMOSにおける本発明による実施例の構成の断面
を模式的に示した図、第４図は本発明によるソース領域
の製造方法を示した図で、6c、6dはソース領域、12はレ
ジスト膜、13は開孔、D1、D2は不純物をそれぞれ示す。FIG. 3 is a diagram schematically showing a cross section of a configuration of an embodiment according to the present invention in CMOS, and FIG. 4 is a diagram showing a method of manufacturing a source region according to the present invention. 6c and 6d are source regions and 12 is a source region. A resist film, 13 is an opening, and D1 and D2 are impurities.
第３図図示のCMOSは、第１図図示のCMOSと比較してソー
ス領域6a、6bがそれぞれソース領域6c、6dに変わったの
みで、その他は変わらない。即ち、ソース領域6c（6d）
は、従来のソース領域6a（6b）を形成する際の不純物注
入と同様な不純物注入を行う第一の不純物注入工程の
後、その注入領域のチャネル側部分を除いた領域に同一
導電型を与える不純物の追加注入を行う第二の不純物注
入工程を経て形成したものである。このことから、ソー
ス領域6c、6dにおいては、従来のソース領域6a、6bと比
較して、チャネル側部分以外の不純物濃度が高く且つ接
合深さが深くソース抵抗Rsa、Rsbの値が小さくなってい
ながら、該チャネル側部分の接合面形状は同形である。
従って、ソース領域6c、6dと基板1a、ウエル領域1bとの
間の両接合面積は従来より大きくなっている。しかしな
がら、ソース領域6c、6dと基板1a、ウエル領域1bとは金
属配線11の接続によりそれぞれ同電位にあるため、両容
量値は増加せずスイッチング速度には無関係である。こ
のことにより、本CMOSは、上記ソース抵抗Rsa、Rsbの値
の低減が作用して、第１図に図示した従来のCMOSよりス
イッチング速度が速くなる。一方、ドレイン領域では接
合面積の増加が接合容量の増加につながるので、本CMOS
におけるドレイン領域に上記容量値の増加によるスイッ
チング速度への影響を避けるため従来のドレイン領域7
a、7bから変えていない。The CMOS shown in FIG. 3 is different from the CMOS shown in FIG. 1 only in that the source regions 6a and 6b are changed to source regions 6c and 6d, respectively, and the others are not changed. That is, the source region 6c (6d)
Gives the same conductivity type to the region except the channel side part of the implanted region after the first impurity implantation step in which the same impurity implantation as the conventional source region 6a (6b) is performed. It is formed through a second impurity implantation step of additionally implanting impurities. From this, in the source regions 6c and 6d, the impurity concentration except the channel side portion is high and the junction depth is deep and the source resistances Rsa and Rsb are smaller than those in the conventional source regions 6a and 6b. However, the joint surface shape of the channel side portion is the same.
Therefore, the junction area between the source regions 6c and 6d and the substrate 1a and the well region 1b is larger than in the conventional case. However, since the source regions 6c and 6d and the substrate 1a and the well region 1b are at the same potential due to the connection of the metal wiring 11, both capacitance values do not increase and are independent of the switching speed. As a result, the present CMOS has a switching speed faster than that of the conventional CMOS shown in FIG. 1 due to the reduction of the values of the source resistances Rsa and Rsb. On the other hand, in the drain region, an increase in junction area leads to an increase in junction capacitance.
In order to avoid the influence of the increase of the capacitance value on the switching speed, the conventional drain region 7
Not changed from a and 7b.
このようなソース領域6c、6dを形成する製造方法は、6c
を例にして第４図に示す。前記第一の不純物注入工程ま
での工程は、従来のソース領域6aとドレイン領域7aとを
形成するために不純物例えば硼素（Ｂ）を両形成領域に
同時に注入する工程までの工程と同様で、該不純物が図
示D1である。この注入の際マスクにしたレジスト膜を除
去して第一の不純物注入工程を終えた後、前記第二の不
純物注入工程に移行し、図示のようにマスクにするレジ
スト膜12を通常の方法で形成する。レジスト膜12はソー
ス領域6c形成領域のチャネル側部分を除いた領域にのみ
開孔13を有し、その他の領域は全て遮蔽するようになっ
ている。但し開孔13はチャネル側と反対側のフィールド
酸化膜２側へ若干はみ出しても支障ない。続いて、不純
物D1と同一導電型を与える不純物D2例えばＢを不純物D1
と同程度の注入量例えば1015atm／cm2程度で注入し、レ
ジスト膜12を除去して第二の不純物注入工程を終わる。
以下は従来のソース領域6aとドレイン領域7aとを形成す
るための不純物注入工程の次の工程に移り、従来と同様
にする。不純物D1とD2の活性化は、従来のソース領域6a
とドレイン領域7aとを活性化させた工程で活性化され、
第３図図示のソース領域6cが形成される。云うまでもな
くドレイン形成領域は不純物D1のみが注入されているの
でドレイン領域7aが形成される。The manufacturing method for forming such source regions 6c and 6d is 6c.
Is shown as an example in FIG. The steps up to the first impurity implantation step are the same as the steps up to the step of implanting an impurity such as boron (B) into both the formation regions at the same time in order to form the source region 6a and the drain region 7a. Impurities are shown in D1. After the resist film masked during this implantation is removed and the first impurity implantation step is completed, the process proceeds to the second impurity implantation step, and the resist film 12 used as a mask as shown in the figure is formed by a usual method. Form. The resist film 12 has an opening 13 only in the region of the source region 6c forming region excluding the channel side portion, and shields all other regions. However, there is no problem even if the opening 13 slightly protrudes to the field oxide film 2 side opposite to the channel side. Then, an impurity D2 giving the same conductivity type as the impurity D1, for example B, is added to the impurity D1.
The second impurity implantation step is completed by implanting the same amount as the above, for example, about 10 15 atm / cm 2 and removing the resist film 12.
Hereinafter, the process proceeds to the next process of the conventional impurity implantation process for forming the source region 6a and the drain region 7a, and the same process as the conventional process is performed. The activation of the impurities D1 and D2 is performed by the conventional source region 6a.
Is activated in the process of activating the drain region 7a and
The source region 6c shown in FIG. 3 is formed. Needless to say, since only the impurity D1 is implanted in the drain forming region, the drain region 7a is formed.
ソース領域6dの場合は、不純物D1に例えば砒素（As）、
不純物D2に例えば燐（Ｐ）が使用されればよく、その注
入量はソース領域6cの場合と同様に例えば1015atm／cm2
程度でよい。In the case of the source region 6d, the impurity D1 may be arsenic (As),
For example, phosphorus (P) may be used as the impurity D2, and the implantation amount thereof is, for example, 10 15 atm / cm 2 as in the case of the source region 6c.
The degree is enough.
かくすることにより、ソース領域6c、6dのソース抵抗Rs
a、Rsbの値を従来のソース領域6a、6bの場合の約１／２
程度に低減させることが可能である。By doing so, the source resistance Rs of the source regions 6c and 6d is
The values of a and Rsb are about 1/2 of those of the conventional source regions 6a and 6b.
It can be reduced to a certain degree.
上述した事情は、その内容からして、単にCMOSに限定さ
れるものではなく、MIS半導体装置に共通したものであ
る。The above-mentioned circumstances are not limited to CMOS in terms of their contents, but are common to MIS semiconductor devices.
（ｇ） 発明の効果 以上に説明したように、本発明による構成によれば、ス
イッチング速度が速く且つ製造においてショートチャネ
ル現象発生のないMIS半導体装置の構成とその製造方法
を提供することが出来て、例えばインバータなどの論理
演算速度の高速化を可能にさせる効果がある。(G) Effects of the Invention As described above, according to the structure of the present invention, it is possible to provide a structure of a MIS semiconductor device which has a high switching speed and does not cause a short channel phenomenon in manufacturing, and a manufacturing method thereof. For example, there is an effect that it is possible to speed up the logical operation speed of an inverter or the like.
第１図はCMOSの一般的な構成の断面を模式的に示した
図、第２図はCMOSを使用したインバータの一般的な回路
図、第３図はCMOSにおける本発明による実施例の構成の
断面を模式的に示した図、第４図は本発明によるソース
領域の製造方法を示した図である。 図面において、1aは基板、1bはウエル領域、２はフィー
ルド酸化膜、3a、3bはチャネルストッパ、４はゲート酸
化膜、５はゲート電極、6a、6b、6c、6dはソース領域、
7a、7bはドレイン領域、8a、8bは接続領域、９はブロッ
ク酸化膜、10はPSG絶縁膜、11は金属配線、12はレジス
ト膜、13は開孔、Sa、SbはMOSFET形成領域、Ta、TbはMO
SFET、Ｇはゲート、Ｓはソース、Ｄはドレイン、Ba、Bb
はTa、Tbを形成する半導体領域、Rsa、Rsbはソース抵
抗、Rda、Rdbはドレイン抵抗、INは入力端子、OUTは出
力端子、Vccは電源線、GNDは接地線、D1、D2は不純物を
それぞれ示す。FIG. 1 is a diagram schematically showing a cross section of a general structure of CMOS, FIG. 2 is a general circuit diagram of an inverter using CMOS, and FIG. 3 is a structure of an embodiment according to the present invention in CMOS. FIG. 4 is a diagram schematically showing a cross section, and FIG. 4 is a diagram showing a method of manufacturing a source region according to the present invention. In the drawing, 1a is a substrate, 1b is a well region, 2 is a field oxide film, 3a and 3b are channel stoppers, 4 is a gate oxide film, 5 is a gate electrode, 6a, 6b, 6c and 6d are source regions,
7a and 7b are drain regions, 8a and 8b are connection regions, 9 is a block oxide film, 10 is a PSG insulating film, 11 is a metal wiring, 12 is a resist film, 13 is a hole, Sa and Sb are MOSFET formation regions, Ta , Tb is MO
SFET, G is gate, S is source, D is drain, Ba, Bb
Is a semiconductor region forming Ta and Tb, Rsa and Rsb are source resistances, Rda and Rdb are drain resistances, IN is an input terminal, OUT is an output terminal, Vcc is a power line, GND is a ground line, and D1 and D2 are impurities. Shown respectively.
Claims (2)
域に形成され該半導体領域と同電位に保持されるべきソ
ース領域の，チャネル側から離れた部分の該ソース領域
の不純物濃度が，チャネル側と接する部分の該ソース領
域の不純物濃度より高濃度であり，かつドレイン領域の
不純物濃度が前記ソース領域のチャネル側と接する部分
の不純物濃度と同程度であることを特徴とするMIS半導
体装置。1. An impurity concentration of a part of a source region, which is formed in a semiconductor region formed of a substrate or a well region and is to be held at the same potential as the semiconductor region, away from the channel side, contacts the channel side. An MIS semiconductor device, wherein the impurity concentration of the portion of the source region is higher than that of the source region, and the impurity concentration of the drain region is about the same as the impurity concentration of a portion of the source region in contact with the channel side.
時に不純物を注入する第一の不純物注入工程と，該ソー
ス形成領域のチャネル側部分を除いた領域に該不純物と
同一導電型不純物を，第一の不純物注入と同じ程度の濃
度で注入する第二の不純物注入工程とを有して，該ソー
ス領域のチャネル側から離れた部分の不純物濃度が，該
ソース領域のチャネル側部分の不純物濃度より高濃度で
あるソース領域を形成することを特徴とするMIS半導体
装置の製造方法。2. A first impurity implantation step of implanting an impurity into a source formation region and a drain formation region at the same time, and an impurity of the same conductivity type as the impurity in a region of the source formation region excluding a channel side portion. A second impurity implantation step of implanting the same impurity concentration as the first impurity implantation, and the impurity concentration of a portion of the source region away from the channel side is higher than that of the source region on the channel side. A method of manufacturing a MIS semiconductor device, which comprises forming a high-concentration source region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59086627A JPH0666469B2 (en) | 1984-04-28 | 1984-04-28 | MIS semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59086627A JPH0666469B2 (en) | 1984-04-28 | 1984-04-28 | MIS semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60231353A JPS60231353A (en) | 1985-11-16 |
| JPH0666469B2 true JPH0666469B2 (en) | 1994-08-24 |
Family
ID=13892263
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59086627A Expired - Lifetime JPH0666469B2 (en) | 1984-04-28 | 1984-04-28 | MIS semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0666469B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5939062A (en) * | 1982-08-27 | 1984-03-03 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5990952A (en) * | 1982-11-16 | 1984-05-25 | Matsushita Electronics Corp | Manufacture of semiconductor device |
-
1984
- 1984-04-28 JP JP59086627A patent/JPH0666469B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5939062A (en) * | 1982-08-27 | 1984-03-03 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5990952A (en) * | 1982-11-16 | 1984-05-25 | Matsushita Electronics Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60231353A (en) | 1985-11-16 |
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