JPH0666316B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a bipolar transistor and its manufacturing method.

2. Description of the Related Art A bipolar transistor formed by using a well-known bipolar integrated circuit manufacturing technique will be described with reference to FIG. This transistor has a P-type semiconductor substrate 1a and an N-type buried layer 2
a, N-type epitaxial layer 3a, P-type base region 4a, N-type emitter region 5a, and N-type collector region 6a.

In such a bipolar transistor, it is necessary to form the N-type buried layer 2a for the purpose of reducing collector series resistance. (For example, Hisayoshi Yanai, Minoru Nagata "Integrated Circuit Engineering (1)" (Sho 57, 5, 15) Corona Publishing Co., P150).

Problems to be Solved by the Invention Conventionally, in order to reduce the collector series resistance as described above, it is necessary to form the N-type buried layer 2a. However, N-type buried layer 2a is formed by heat treatment a number of times after epitaxial growth. The layer may diffuse into the inside of the epitaxial layer and the thickness of the epitaxial layer immediately below the base region may become thin, which may cause a problem that the breakdown voltage decreases.

An object of the present invention is to reduce the collector series resistance and to extremely reduce the element occupying area without using the N-type buried layer 2a having the above problems.

Means for Solving the Problems In order to solve this problem, the present invention forms an emitter region and a base region in a bipolar transistor on one side surface of a well formed on a surface of a semiconductor substrate and forms a collector contact region as described above. It is formed in a region near the one side surface other than the well.

Operation This structure shortens the distance between the active base region and the collector contact region, and because the wide bottom surface of the base region faces the collector contact region, carriers injected from the base region reach the collector electrode. Becomes shorter, resulting in a very small collector series resistance. Further, since the emitter region and the base region are formed in the direction perpendicular to the semiconductor substrate surface, the device surface area becomes extremely small.

Example An example in which the present invention is applied to a silicon semiconductor device will be described below with reference to the drawings.

First, in FIG. 2A, an N type epitaxial layer 1 is formed on a P type silicon semiconductor substrate by chemical vapor deposition.
To have a thickness of about 3 μm. Then, after forming an element isolation region (not shown) by a selective oxidation method or an impurity diffusion method, the thermal oxide film 2 is used as a mask in the transistor formation area to form a square opening with a side length of about 3 μm. A well 9 having a depth of about 1.5 μm is formed by the reactive ion etching method. Next, the thermal oxide film 2 used as a mask when forming the well 9 is removed by about 2 μm in the direction of one side of the opening of the well 9 (portion indicated by 10 in FIG. 2A).

Next, as shown in FIG. 2B, the thermal oxide film 2 is formed.
Using the as a mask, the boron impurities are diffused by the thermal diffusion method to form the P-type base region 3. At this time, the thermal oxide film 11 is formed on the entire surface of the opening simultaneously with the diffusion.

Next, as shown in FIG. 2 (c), a part of the thermal oxide film on the well side surface and the bottom surface of the well opposite to the direction in which the mask oxide film is diffused and opened at the time of forming the well 9 as described above and well formation A part of the thermal oxide film near the side surface of the well other than the above portion is opened by photolithography. Since the opening of the thermal oxide film other than the well forming portion is for forming the collector contact region, its position is determined in consideration of the distance from the P-type base region 3. After that, a polycrystalline silicon layer 6 is formed on the entire surface by a chemical vapor deposition method, and then a phosphorus (P) impurity is diffused from the polycrystalline silicon layer and a thermal oxide film opening portion by a thermal diffusion method to form an N-type emitter region 4. And an N-type collector contact region 5 are formed. Further, FIG. 2 (d)
As shown in Fig. 6, the polycrystalline silicon layer 6 in which phosphorus (P) is diffused
Are formed as lead electrodes 6 of the N-type emitter region 4 and the N-type collector contact region 5 by photolithography.

Next, a silicon nitride film 7 is deposited on the entire surface by plasma vapor deposition, and the silicon nitride film 7 on the extraction electrodes 6 of the N-type emitter region 4 and the N-type collector contact region 5 is deposited.
1 and the silicon nitride film 7 and the thermal oxide film 2 above the base region 3 extended to the silicon semiconductor substrate other than the well forming portion, and the aluminum electrode 8 is formed to form the aluminum electrode 8 as shown in FIG. Such a bipolar transistor is formed.

As described above, according to the present invention, since the collector contact region and the base layer can be formed close to each other, the collector resistance is reduced, and the high-concentration buried layer required in the conventional bipolar transistor is not necessary. Become. Moreover, since the well wall surface portion is used as the active region of the element, the area occupied by the element is extremely small, and high integration is possible. Further, since the film thickness and the variation of the epitaxial layer have nothing to do with the transistor characteristic, the manufacturing process becomes very easy.

[Brief description of drawings]

FIG. 1 is a partial sectional view of a silicon semiconductor device according to an embodiment of the present invention, and FIGS. And FIG. 3 is a sectional view of a conventional bipolar transistor. 1,3a …… N-type epitaxial layer, 2,7a …… thermal oxide film, 3,
4a ... P-type base region, 4,5a ... N-type emitter region, 5,
6a ... N-type collector contact region, 6 ... Polycrystal silicon extraction electrode, 7 ... Silicon nitride layer, 8,9a ... Aluminum electrode, 9 ... Element forming well, 10 ... Base contact diffusion opening , 11 ... Thermal oxide film on P-type base region,
1a ... P-type semiconductor substrate, 2a ... N-type buried layer, 8a ... P-type isolation region.

Claims (2)

[Claims] 1. A semiconductor in the vicinity of one side surface of the well in which a well is formed on a surface of a semiconductor substrate, a base region and an emitter region are formed on at least one side surface of the well, and a collector contact region is formed on the one side surface of the well. A semiconductor device formed on the surface of a substrate. 2. A step of forming a well in a predetermined portion on the surface of a semiconductor substrate using an insulating film as a mask, and a step of diffusing one conductivity type impurity using the insulating film as a mask to form an insulating film on the entire surface of the semiconductor substrate. And a step of forming an opening in the insulating film near the one side surface of the well and the one side surface other than the well, and a step of diffusing an impurity of opposite conductivity type from the opening.