JPH066346A - Reception method for burst transmission signal - Google Patents

Abstract

PURPOSE:To make the receiver small in size and to reduce the power consumption by eliminating the need for a circuit detecting the input of a preamble signal in the reception method for a burst state transmission signal in a mobile radio system for a cellular telephone system where the transmission of burst data is required on the way of transmission of a voice signal. CONSTITUTION:A synchronizing signal detection means 1 detects a synchronizing signal included in an input signal comprising plural frames. After the synchronizing signal detection means 1 detects a 1st synchronizing signal, reception processing of data inputted in succession to the 1st synchronizing signal is implemented and a bit number count means 2 counts number of bits of the input signal. When the bit number count means 2 counts the sum of a prescribed bit number of data and a bit number of the synchronizing signal, a confirmation means 3 confirms the input of a 2nd synchronizing signal. When the confirmation means 3 confirms the input of the 2nd synchronizing signal, a data reception processing means 4 continues the reception processing of data inputted in succession to the 2nd synchronizing signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burst transmission signal receiving method for receiving a signal transmitted in burst by connecting a predetermined number of frames each composed of a synchronization signal and a predetermined number of bits of data, and more particularly to a voice signal. The present invention relates to a method for receiving a burst-like transmission signal in a mobile radio system such as a car telephone, which is required to transmit data in bursts during signal transmission.

In a mobile radio system such as a car telephone, data for controlling the mobile device is sent from the base station to the mobile device during a call. Since such data is transmitted in bursts during the transmission of the voice signal, the mobile device needs to accurately receive the data by distinguishing the data from the voice signal, and the noise generated in the voice reproduction circuit at the time of the data transmission by the user. Need to be deaf.

[0003]

2. Description of the Related Art First, the format of a data transmission signal used in a mobile radio system will be described with reference to FIG. FIG. 4A shows a format of a data transmission signal (Forward Voice Channel Data) used in the AMPS system which is a communication system for car phones, mobile phones, etc. in North America.
Format) is shown. The data transmission signal is composed of 11 frames, and each frame includes a preamble signal portion 41a for bit synchronization, which is formed by repeating "1010 ...".
.About.44a, sync signal portions 41b to 44b for frame synchronization each having 11 bits, and data portions 41c to 44c each having 40 bits. In the preamble signal part, only the first frame has 101 bits, and the remaining frames each have 37 bits. Therefore,
There will be a sync signal every 88 bits. The code of each synchronization signal is the same. The data transmission signal is generated by the split phase code (Manchester code) method.

The structure of a conventional receiving apparatus for receiving a data transmission signal in such a format will be described with reference to FIG. First, the audio reproduction circuit 51 demodulates the received signal to reproduce the audio signal, and outputs the audio signal to the output circuit 53 that performs audio amplification and the like via the mute circuit 52. Mute circuit 52
The control signal from the processor 58 sends the output of the audio reproducing circuit 51 to the output circuit 53 when the receiving device does not receive the data transmitting signal, and outputs the output of the audio reproducing circuit 51 when the receiving device receives the data transmitting signal. The output is prohibited from being sent to the output circuit 53 (the audio path is muted).

The reception data reproducing circuit 54 shapes the waveform of the reception signal, extracts the data pulse signal, and outputs it to the serial input circuit 55. On the other hand, the reception clock generation circuit 56 extracts a clock component from the reception signal and outputs it to the serial input circuit 55 and the frequency divider 57. The serial input circuit 55 serially inputs the signal from the reception data reproduction circuit 54 based on the clock from the reception clock generation circuit 56, converts the signal into an n-bit (for example, n = 8) parallel signal, and outputs the parallel signal to the processor 58. . The frequency divider 57 is
The clock from the reception clock generation circuit 56 is divided by 1 / n and output to the switch 59. The cycle of the clock divided by 1 / n (hereinafter, referred to as “1 / n clock”) matches the output cycle of the parallel signal of the serial input circuit 55.

By the way, the preamble signal is "1,
Due to the repetition of "0", the signal has a frequency (for example, 5 kHz) that is half the bit rate (for example, 10 kb / s) of the data of the split phase coding method, and the band pass filter 60 changes the frequency (for example, 5 kHz). It is a filter with a pass band. Therefore, the bandpass filter 60 outputs a signal to the integrator 61 only when the preamble signal is input. The integrator 61 integrates it and the comparator 62 outputs the set signal to the switch 59 formed of a flip-flop when the integrated value exceeds a predetermined value. In the comparator 62, 50 to 50 out of 101 bits forming the first preamble signal
The predetermined value is set so that the set signal is output when 70% is input.

When the set signal is input, the switch 59 passes the 1 / n clock from the frequency divider 57 and outputs it as an interrupt signal IRQ to the processor 58. The processor 58 outputs a reset signal to the switch 59 when eleven frames of the data transmission signal have been input, and the switch 59 causes the switch 59 to pass the 1 / n clock from the frequency divider 57 to the processor 58. Stop things.

The processor 58 includes a CPU, a RAM and an RO.
It consists of M, I / O, etc., and the frequency divider 5 via the switch 59.
According to the interrupt signal IRQ of 1 / n clock input from 7, the sync signal search process and the data reception process are performed. That is, while the interrupt signal IRQ is not input,
No processing is performed on the output from the serial input circuit 55, an unmute control signal is sent to the mute circuit 52, and the output of the audio reproduction circuit 51 is passed to the output circuit 53. On the other hand, when the preamble signal is received and the interrupt signal IRQ is input, continuous search processing of the sync signal is performed, and when the first sync signal is detected, the mute circuit 52
A mute control signal to prohibit the passage of the output of the audio reproduction circuit 51 to the output circuit 53 [T1 in FIG. 4 (B)].
See timing]. Then, data reception processing is performed.
After that, while confirming that there is a next sync signal every 88 bits from the first sync signal [see FIG. 4 (A)], the reception processing of the data of each frame is performed. When the reception of the eleventh final frame is completed, an unmute control signal is sent to the mute circuit 52 (see T3 timing in FIG. 4B).

As described above, in order to prevent the voice signal from being erroneously received as a data transmission signal, conventionally, the preamble signal is detected and distinguished from the voice signal, and further, the synchronization signal indicating the start of the frame is detected. The data reception process was started.

[0010]

By the way, since the above-mentioned receiving device functions as a mobile device, such a receiving device is always required to be downsized and to reduce power consumption.

On the other hand, in order to distinguish the data transmission signal from the voice signal, a circuit for detecting the input of the preamble signal has been conventionally required. But,
If the data transmission signal can be distinguished from the voice signal without performing the identification of the preamble signal, there is a situation in which the above request can be met.

The present invention has been made in view of such circumstances, and a circuit for performing preamble signal identification and input detection is reduced to reduce the size of a receiving device and reduce power consumption. The purpose is to provide a receiving method.

[0013]

FIG. 1 is a diagram for explaining the principle of the present invention for achieving the above object. A receiving device to which the method for receiving a burst-like transmission signal of the present invention is applied receives a transmission signal composed of a plurality of frames. The transmission signal is a burst signal in which a frame composed of a preamble signal, a synchronization signal, and a predetermined number of bits of data is connected by a predetermined number of frames.

The configuration of the receiving apparatus is such that the synchronization signal detecting means 1 for detecting the synchronization signal included in the input signal and the first synchronization signal from the time when the synchronization signal detecting means 1 detects the first synchronization signal. The bit number counting means 2 for counting the number of input bits of the input signal and the bit number counting means 2 while receiving the data to be subsequently input,
When counting the sum of the predetermined number of bits of data and the number of bits of the synchronization signal, the confirmation means 3 for confirming that the second synchronization signal is input, and the confirmation means 3 confirm the input of the second synchronization signal. If confirmed, the data reception processing means 4 continues the reception processing of the data input subsequently to the second synchronization signal.

[0015]

With the above configuration, in FIG. 1, the sync signal detecting means 1 first detects the sync signal contained in the input signal composed of a plurality of frames. The bit number counting means 2 counts the number of input bits of the input signal while receiving the data to be input subsequently to the first synchronizing signal from the time when the first synchronizing signal is detected by the synchronizing signal detecting means 1. To do. When the bit number counting means 2 counts the sum of the predetermined number of bits of data and the number of bits of the synchronization signal, the confirmation means 3 confirms that the second synchronization signal is input. When the confirmation unit 3 confirms the input of the second synchronization signal, the data reception processing unit 4 continues the reception process of the data input subsequent to the second synchronization signal.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing the configuration of a receiving apparatus to which the present invention is applied. This receiver is a car phone,
A receiving device in a mobile radio system such as a mobile phone, which receives a data transmission signal in the format shown in FIG.

First, the audio reproduction circuit 21 demodulates the received signal to reproduce the audio signal and, via the mute circuit 22,
It is output to the output circuit 23 that performs audio amplification and the like. According to the control signal from the processor 28, the mute circuit 22 sends the output of the audio reproduction circuit 21 to the output circuit 23 when the receiving device does not receive the data transmission signal, and reproduces the audio when the data transmission signal is received. It is prohibited to send the output of the circuit 21 to the output circuit 23 (muting the audio path).

The received data reproducing circuit 24 shapes the waveform of the received signal, extracts the data pulse signal, and outputs it to the serial input circuit 25. On the other hand, the reception clock generation circuit 26 extracts a clock component from the reception signal and outputs it to the serial input circuit 25 and the frequency divider 27. The serial input circuit 25 serially inputs the signal from the reception data reproduction circuit 24 based on the clock from the reception clock generation circuit 26, converts the signal into an n-bit (eg, n = 8) parallel signal, and outputs the parallel signal to the processor 28. . The frequency divider 27 is
The clock from the reception clock generation circuit 26 is divided by 1 / n and output to the processor 28 as an interrupt signal IRQ. Therefore, the interrupt signal IRQ is always input to the processor 28 as long as the clock is detected.

Next, the reception processing of the processor 28 which is activated by the input of the interrupt signal IRQ will be described with reference to FIG. FIG. 3 is a flowchart showing the procedure of the reception process executed by the processor 28. In the figure, the number following S indicates a step number. [S1] The sync signal is continuously searched from the input signals. That is, the data that has entered the serial input circuit 25 is searched bit by bit until it matches the sync signal. [S2] It is determined whether or not the synchronization signal (FS) is detected. If detected, the process proceeds to step S3, and if not detected, the process returns to step S1. [S3] Reception processing of data following the detected synchronization signal (first synchronization signal) is performed, and counting of the number of input bits of the input signal is started from the time when the first synchronization signal is detected. At this stage, the audio path is not muted because there is still a possibility of detecting the false synchronization signal.

[S4] Wait until the count value of the count of the number of input bits started in step S3 reaches 88 bits (= 40 bits of data + 37 bits of next preamble signal + 11 bits of next synchronization signal), When it reaches 88 bits, the process proceeds to step S5. [S5] If a normal signal is input, the next synchronization signal (second synchronization signal) should have been input at this stage. In this step, the second synchronization signal (FS) is input.
It is determined whether or not is input. As a result, if it is input, the process proceeds to step S6. If it is not input, it is determined that the data transmission signal has not been received, the process returns to step S1, and the continuous search process is restarted. [S6] It is determined that the data transmission signal is received, and the audio path is muted [see T2 timing in FIG. 4 (C)].

[S7] Data reception processing is performed subsequent to the synchronization signal (second synchronization signal or a subsequent synchronization signal) for which the input is determined. [S8] It is determined whether or not the frame having the data subjected to the reception processing in step S7 is the eleventh final frame. If it is the last frame, step S12
If no, go to step S9. [S9] It waits until a signal for 88 bits is input after the previous synchronization signal (FS) is input. That is, the process waits until the count value of the count of the number of input bits started in step S3 reaches the product value of 88 bits and the number of input frames, and when that is reached, the process proceeds to step S10.

[S10] If a normal signal is input,
At this stage, the next sync signal (third sync signal or a subsequent sync signal) should have been input. In this step, it is determined whether or not the sync signal (FS) is input. To do. As a result, if it is input, the process proceeds to step S7, and the steps S7 to S10 are repeated. If it is not input, it is determined that the data transmission signal has an error, and the subsequent data reception process is performed. Cancel and proceed to step S11. [S11] Wait until the reception of the bits up to the data of the eleventh final frame is completed, and if completed, step S1
Go to 2. That is, after the input of the second synchronization signal,
When the input of the synchronization signal cannot be confirmed, the subsequent data receiving process is stopped, but the process returns to step S1 and the mute of the audio path is continued until the reception of the final frame is completed. [S12] Unmute the audio path [Fig. 4 (C)]
See the T3 timing of the above].

As described above, first, the synchronizing signal is continuously searched from the received signals, and when the first synchronizing signal is detected, the second synchronizing signal is located at a position separated by a predetermined number of bits. Confirm that there is. From this confirmation, it is determined that the data transmission signal is surely received, and the audio path is muted. If the confirmation cannot be made, it is determined that the data transmission signal has not been received, and the process returns to the first continuous search.

After determining that the data transmission signal is surely received, the synchronization signal of each frame is confirmed while counting the number of bits from the first synchronization signal, and the data reception processing is performed. If the sync signal cannot be confirmed, the data reception processing of the remaining frames is stopped, and the mute of the audio path is continued until the reception of all the remaining frames is completed.

In the above-mentioned embodiment, the description has been given by using the receiving apparatus for receiving the data transmission signal having the format of the AMPS system, but the format of the data transmission signal is not limited to this, and the synchronization signal and the predetermined bit are used. The present invention can be applied to any signal as long as it is a signal in which a predetermined number of frames composed of several pieces of data are concatenated and transmitted in a burst form. That is, the number of bits of the synchronization signal or data,
The present invention can be applied regardless of the number of frames.

[0026]

As described above, according to the present invention, the reception processing of the data input subsequently to the first synchronizing signal from the time when the first synchronizing signal is detected is performed, and the number of input bits of the input signal is changed. When the counted number of bits reaches the sum of the predetermined number of bits of data and the number of bits of the synchronization signal, it is confirmed that the second synchronization signal is input, and the second synchronization signal is input. If confirmed, it is configured to continue the reception process of the data input after the second synchronization signal. Therefore, the data transmission signal can be clearly distinguished from the audio signal, and the audio signal is not erroneously received as data, and it is possible to reduce the circuit for identifying the preamble signal and detecting the input. Therefore, it is possible to reduce the size of the receiving device and reduce the power consumption.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a configuration of a receiving device to which the present invention is applied.

FIG. 3 is a flowchart showing a procedure of a reception process executed by a processor.

FIG. 4 is a diagram showing a format of a data transmission signal.

FIG. 5 is a block diagram showing a configuration of a conventional receiving device.

[Explanation of symbols]

 1 sync signal detecting means 2 bit number counting means 3 confirming means 4 data reception processing means

Claims (6)

[Claims] 1. A method for receiving a burst-like transmission signal in which a frame composed of a synchronization signal and a predetermined number of bits of data is connected in a predetermined number of frames to receive a burst-like transmission signal, wherein a synchronization signal included in an input signal is used. Is detected, and the reception processing of the data input subsequently to the first synchronization signal is performed from the time when the first synchronization signal is detected, and
Counting the number of input bits of the input signal, when the bit number count value reaches the sum of the predetermined number of bits of data and the number of bits of the synchronization signal, confirm that the second synchronization signal is input, A method for receiving a burst-like transmission signal, characterized in that, when the input of the second synchronization signal is confirmed, the reception processing of the data input subsequently to the second synchronization signal is continued. 2. The method for receiving a burst-like transmission signal according to claim 1, wherein detection of a new synchronization signal included in the input signal is restarted if the input of the second synchronization signal cannot be confirmed. . 3. The method for receiving a burst-like transmission signal according to claim 1, wherein when the input of the second synchronization signal is confirmed, muting of the audio path is started. 4. Counting the number of frames that have been input since the first synchronization signal was detected, and when the count value of the number of frames reaches the predetermined number of frames, unmute the audio path. 4. The method according to claim 3,
A method for receiving a burst-like transmission signal as described. 5. The number of frames is checked even if the input of the subsequent synchronizing signal input after the input of the second synchronizing signal is confirmed based on the bit number count value, and the input of the subsequent synchronizing signal cannot be confirmed. The method of receiving a burst-like transmission signal according to claim 4, wherein the muting of the audio path is not canceled until the count value reaches the predetermined number of frames. 6. The input of the subsequent synchronization signal input after the input of the second synchronization signal is confirmed based on the bit number count value, and if the input of the subsequent synchronization signal cannot be confirmed, the data is immediately output. 2. The burst transmission signal receiving method according to claim 1, wherein the receiving process is stopped.