JPH0662064A - Digital communication equipment - Google Patents

Abstract

PURPOSE:To provide the equipment low in the error ratio of data even when the noise of a transmission line is added by loading information on the changes of encoded data of over two bits in the past and current data and encoding it. CONSTITUTION:A differential encoder 15 and a differential decoder 16 are respectively used for a transmission part 6 and a reception part 14. At the encoder 15, the information is loaded on the changes of the encoded data preceding for (n) bits and the current encoded data and encoded. Thus, even when there is noise in the transmission line and the demodulation error of one bit is generated at a demodulator 10, the output of the decoder 16 is prevented from being erroneous continuously for two bits, differentially decoded data are turned to random error, and the degradation of the error correcting ability of a viterbi decoder 12 can be reduced. Therefore, the error ratio of the reception side caused by the noise of the transmission line or the like is decreased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital communication device for transmitting and receiving digital data.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a conventional digital communication device. In the figure, 1 is an input terminal for inputting information data to be transmitted, and 2 is a folding as an error correction encoder for encoding the information data from the input terminal 1 into a data string capable of correcting a random error. It is a built-in encoder. 3 is not the digital data itself,
In order to put information on changes in the encoded data of the data string,
It is a differential encoder that encodes the data string from the convolutional encoder 2. Reference numeral 4 is a BPSK modulator as a modulator for performing two-phase phase shift keying (hereinafter referred to as BPSK) on the data string encoded by the differential encoder 3, and 5 is B
It is a transmitter that frequency-converts and amplifies the modulated signal from the PSK modulator 4. Reference numeral 6 denotes a transmitter formed by the convolutional encoder 2, the differential encoder 3, the modulator 4 and the transmitter 5.

Reference numeral 7 is an antenna for radiating the signal from the transmitter 6 as a radio wave into space and receiving the radio wave radiated by the other device, and 8 is a transmission signal to the antenna 7 and the antenna 7
It is a diplexer that separates the received signal from. Reference numeral 9 is a receiver that amplifies the received signal separated by the diplexer and frequency-converts it, and reference numeral 10 is a demodulator that performs reception signal synchronous detection of the receiver 9 to demodulate a data string. Reference numeral 11 is a differential decoder that restores information based on a change in received coded data of the data string demodulated by the demodulator 10, and 12 is a data string restored by the differential decoder 11. A Viterbi decoder as an error correction decoder for correcting a random error, and 13 is an output terminal from which the information data error-corrected by the Viterbi decoder 12 is output. Reference numeral 14 is a receiver formed by the receiver 9, demodulator 10, differential decoder 11 and Viterbi decoder 12.

Next, the operation will be described. In the transmission unit 6, the convolutional encoder 2 encodes the information data input from the input terminal 1 into a data string in which a random error can be corrected and sends the data string to the differential encoder 3. As shown in FIG. 6, the differential encoder 3 includes a modulo-2 adder 22 having one input port connected to the input terminal 21 and an output port connected to the output terminal 24, and the modulo-2 addition. The output signal of the device 22 is delayed by 1 bit and returned to the other input port of the modulo-2 adder 22. The D flip-flop 23 serves as a delay element and operates as follows.

That is, in FIG. 6, "0" is set as the initial value of the D flip-flop 23, and when the information data "1" is input from the convolutional encoder 2 to the input terminal 21, the output terminal is output. The encoded data “1” is output to 24, and the encoded data “1” is stored in the D flip-flop 23. Next, information data “0”
Similarly, the encoded data “1” is output to the output terminal 24, and the encoded data “1” is stored in the D flip-flop 23. After that, when the information data is sequentially input in the order of “0101100”,
“1001000” is obtained as encoded data. FIG. 7 is an explanatory diagram showing the correspondence between encoded data and information data in that case. As is apparent from FIG. 7, the coded data has no bit change (0 → 0, 1 → 1) when the information data is “0”, and the coded data when the information data is “1”. There is a bit change (0 → 1, 1 → 0). That is, the differentially encoded data has the same bit as the bit one symbol before when the information data is "0", and inverts the bit one symbol before when the information data is "1".

The data string differentially encoded by the differential encoder 3 is sent to the BPSK modulator 4 and BP.
After being SK-modulated, the transmitter 5 performs frequency conversion and high-power amplification, and radiates as a radio wave from the antenna 7 via the diplexer 8.

On the other hand, in the receiving section 14, the radio wave from the communication partner received by the antenna 7 is input to the receiver 9 via the diplexer 8 and low noise amplification and frequency conversion are performed. The frequency-converted received signal is sent to the demodulator 10, demodulated, and then input to the differential decoder 11. As shown in FIG. 8, the differential decoder 11 includes a modulo-2 adder 26 having one of its input ports connected to an input terminal 25 and an output port connected to an output terminal 28, and the modulo-2 adder. It is constituted by a D flip-flop 27 as a delay element, which delays the input signal to 26 by 1 bit and inputs it to the other of the modulo-2 adder 26 at the input port. The information is decoded based on the bit change. Since the operation is the reverse operation of the differential encoder 3, the description is omitted.

Here, in the demodulator 10, the carrier is regenerated to perform synchronous detection, but the phase of the regenerated carrier with respect to the transmission carrier may be either forward or reverse. Therefore, when the reproduction carrier is inverted, the demodulator 1
The data string output by 0 is inverted to “1” for “0” and “0” for “1” with respect to the data string differentially encoded on the transmission side. However, in the differentially encoded data string as described above, information is added to the change in the encoded bits, so that even if each bit of the input data string of the differential decoder 11 is inverted, The decoded data string is the same as the input data string of the original differential encoder 3 on the transmission side. The output data of the differential decoder 11 is finally corrected in error by the Viterbi decoder 12 and then output from the output terminal 13. In this way, the differential encoder 3 and the differential decoder 11
Plays a role in correcting the data inversion that occurs in the demodulator 10.

When a 1-bit error occurs in the data string input to the differential decoder 11 due to noise on the transmission line, as apparent from the above-mentioned differential encoding / decoding process, The data string output from the differential decoder 11 is erroneous for two consecutive bits. However, the Viterbi decoder 1
It is known that 2 has a high correction capability for a random error, but the error correction capability deteriorates for such a burst error in which two consecutive errors occur.

Documents describing the technology related to such a conventional digital communication apparatus are, for example, Japanese Patent Laid-Open No. 63-42549 and Japanese Patent Laid-Open No. 3-228441.
There is a bulletin, etc.

[0011]

Since the conventional digital communication apparatus is constructed as described above, noise is added to the transmission line, and a 1-bit error occurs in the output data string of the demodulator 10. In this case, the data string output from the differential decoder 11 is erroneous for two consecutive bits.
As a result, the error correction capability of the Viterbi decoder deteriorates.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a digital communication apparatus with little deterioration in error rate even if a differential encoding / decoding system is used. To do.

[0013]

According to a first aspect of the present invention, there is provided a digital communication apparatus, wherein n bits (n is an integer of 2 or more, the same applies hereinafter) between past coded data and present coded data are changed. A data encoder encoded so that random errors can be corrected is encoded by using a differential encoder that puts information on.

Further, the digital communication apparatus according to the invention of claim 2 uses a differential decoder which restores information based on a change between n-bit past reception coded data and the present reception coded data. , The data string demodulated by the demodulator is decoded and transferred to the error correction decoder.

According to the third aspect of the present invention, the digital communication device uses a delay detection demodulator for performing delay detection to combine a non-delayed reception signal and a reception signal delayed by n bits to obtain information. Is restored and transferred to the error correction decoder.

[0016]

According to the differential encoder of the invention described in claim 1, when encoding a data string encoded so that a random error can be corrected, n bits of past encoded data and present encoded data are encoded. By adding the information to the change of, it is possible to prevent the data string after differential decoding from being erroneous for two consecutive bits due to a one-bit error in the transmission path, and the error can be corrected by the error correction decoder on the receiving side. To do.

Further, in the differential decoder according to the second aspect of the present invention, when decoding the data sequence demodulated by the demodulator, the change between the reception coded data of n bits past and the current reception coded data is changed. By restoring the information based on the above, it is possible to prevent the data string after differential decoding from being erroneous for two consecutive bits due to a one-bit error in the transmission path, and to enable correction by the error correction decoder.

The differential detection demodulator according to the third aspect of the present invention synthesizes a non-delayed received signal and a received signal delayed by n bits, performs differential detection, and restores information to thereby obtain a transmission line. In order to prevent the data string after differential decoding from being erroneous for two consecutive bits,
Enables correction by an error correction decoder.

[0019]

EXAMPLES Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the invention described in claims 1 and 2. In the figure, 1
Is an input terminal, 2 is a convolutional encoder as an error correction encoder, 4 is a BPSK modulator as a modulator, 5 is a transmitter, 6 is a transmitter, 7 is an antenna, 8 is a diplexer,
Reference numeral 9 is a receiver, 10 is a demodulator, 12 is a Viterbi decoder as an error correction decoder, 13 is an output terminal, and 14 is a receiving unit, which are the same as or equivalent to those of the related art denoted by the same reference numerals in FIG. Since it is a part, detailed description is omitted. Also,
Reference numeral 15 indicates information on the change between the n-bit past coded data and the current coded data of the data string encoded into the data string in which the random error can be corrected by the convolutional encoder 2. It is a differential encoder that encodes and transfers it to the BPSK modulator 4. Reference numeral 16 is a differential decoding that restores information based on a change between the received coded data of the past n bits and the current received coded data of the data string demodulated by the demodulator 10 and transfers the information to the Viterbi decoder 12. It is a vessel.

FIG. 2 is a block diagram showing the configuration of the differential encoder 15, and FIG. 3 is a block diagram showing the configuration of the differential decoder 16. The differential encoder 15 shown in FIG. 2 outputs the output signal of the modulo-2 adder 22 in cascade
This is different from the one shown in FIG. 6 in that it is delayed by n bits by the individually connected D flip-flops 23 and is returned to one input port of the modulo-2 adder 22.
In the differential decoder 16 shown in FIG. 3, an input signal delayed by n bits by the D flip-flops 27 connected in cascade is input to one input port of the modulo-2 adder 26. It differs from that shown in FIG.

Next, the operation will be described. Here, since the basic operation is similar to the conventional case, the operation of the differential encoder 15 and the differential decoder 16 will be mainly described. First,
In the differential encoder shown in FIG. 2, if the input data series to the input terminal 21 is a _i and the output data to the output terminal 24 is b _i , the following equation holds. [+] In the equation represents addition of modulo 2.

B _i = a _i [+] b _in ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ (1)

From the above equation (1), when n = 1, it is the same as the conventional differential encoder 3 shown in FIG. 6, and when n> 1, the encoded data (b) n bits before is obtained. It is clear that the information a _i is added to the change between ( _in ) and the current encoded data b _i . The differential decoder 16 shown in FIG. 3 also operates similarly to the conventional differential decoder 11 shown in FIG. 8 when n = 1.

When such a differential encoder 15 and a differential decoder 16 are used in the transmitting unit 6 or the receiving unit 14 of the digital communication apparatus shown in FIG. Since information is added to the change between the encoded data and the current encoded data, even if there is a 1-bit demodulation error in the demodulator 10 due to noise on the transmission path, the output of the differential decoder 16 is 2 Therefore, if n is made sufficiently large, the decoding error due to the noise becomes a random error in the differential decoded data, and the deterioration of the error correction capability of the Viterbi decoder 12 can be reduced.

Example 2. In the first embodiment described above, the case where the receiving unit 14 includes the demodulator 10 for synchronous detection and the differential decoder 16 has been described, but they may be replaced with a demodulator for differential detection. FIG. 4 is a block diagram showing an embodiment of such an explanation described in claim 3. In the figure, reference numeral 17 is a delay detection demodulator that synthesizes a non-delayed reception signal and a reception signal delayed by n bits, and decodes information by delay detection.
Of these, 31 is a delay line for delaying the received signal by n bits, 3
Reference numeral 2 is a multiplier for synthesizing the reception signal delayed by the delay line 31 and the reception signal not delayed. The operation is the same as the operation of the differential decoder 16 shown in FIG. 3 in the intermediate frequency (IF) band, and the description thereof will be omitted.

Example 3. Further, in each of the above embodiments, the convolutional encoder 2 and the Viterbi decoder 12 are used for the correction of the random error, but another encoding / decoding method having a large random error correction capability is used. Of course, the same effect as that of the above-described embodiment can be obtained.

Example 4. Further, in the above-mentioned embodiment, the one using BPSK as the modulation method is shown, but other modulation methods such as 4-phase phase shift keying (QPSK) and frequency shift keying (FSK) may be used. It has the same effect as the example.

[0028]

As described above, according to the invention described in claim 1, by using the differential encoder which puts information on the change of the n-bit past encoded data and the present encoded data, Since the data string encoded so that the random error can be corrected is coded, the data string after differential decoding may be erroneous for two consecutive bits due to a one-bit error due to noise on the transmission line. It becomes possible to reduce the deterioration of the error correction capability in the error correction decoder on the receiving side,
There is an effect that a highly reliable digital communication device can be obtained.

According to the second aspect of the invention, n
It is configured to decode the data sequence demodulated by the demodulator using a differential decoder that restores information based on the changes in the received coded data in the past and the current received coded data. It is possible to prevent the data string after differential decoding from being mistaken for two consecutive bits due to a 1-bit error due to noise, etc., and it is possible to reduce the deterioration of the error correction capability in the error correction decoder, and to improve reliability. There is an effect that a high digital communication device can be obtained.

According to the third aspect of the invention, the information is restored by combining the non-delayed reception signal and the reception signal delayed by n bits by using the delay detection demodulator for performing the delay detection. Because it is configured as
It is possible to prevent a data string after differential decoding from being erroneous for two consecutive bits due to a bit error, and it is possible to reduce deterioration of error correction capability in an error correction decoder, and to provide a highly reliable digital communication device. There is an effect to be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a differential encoder in the above embodiment.

FIG. 3 is a block diagram showing a configuration of a differential decoder in the above embodiment.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a block diagram showing a conventional digital communication device.

FIG. 6 is a block diagram showing a configuration of a conventional differential encoder.

FIG. 7 is an explanatory diagram showing correspondence between encoded data and information data.

FIG. 8 is a block diagram showing a configuration of a conventional differential decoder.

[Explanation of symbols]

 2 Error Correction Encoder (Convolutional Encoder) 6 Transmitter 10 Demodulator 12 Error Correction Decoder (Viterbi Decoder) 14 Receiver 15 Differential Encoder 16 Differential Decoder 17 Delay Detection Demodulator

Claims (3)

[Claims] 1. An error correction encoder for encoding input information data into a data string capable of correcting a random error, and two or more bits of a data string encoded by the error correction encoder. A digital communication device having a transmission section including a differential encoder that encodes information based on changes in past encoded data and present encoded data. 2. A differential decoder that restores information based on a change in past coded data of 2 bits or more and a current coded reception data of a data string demodulated by a demodulator, and the differential decoder. A digital communication device having a receiving section provided with an error correction decoder for correcting a random error of a data string restored in step 1. 3. A delay detection demodulator that synthesizes a reception signal having no delay and a reception signal delayed by 2 bits or more, performs delay detection to restore information, and data restored by the delay detection demodulator. A digital communication device comprising a receiving unit having an error correction decoder for correcting a random error in a sequence.