JPH066177A - Electronic tuner - Google Patents

Abstract

PURPOSE:To obtain an electronic tuner with high reliability by preventing a PLL channel selection circuit from malfunctioning due to spurious waves generated by the saturation of a high frequency amplifier circuit even when a strong input signal is inputted from an antenna. CONSTITUTION:While a PLL channel selection circuit 7 is in tuning operation, a switching circuit is closed by a lock output signal introduced from a lock signal output terminal 11 of the PLL channel selection circuit 7 to divide an AGC voltage to a high frequency amplifier circuit 2 thereby decreasing the gain. Thus, the saturation of the high frequency amplifier 2 is prevented to suppress generation of spurious waves thereby preventing malfunction of the PLL channel selection circuit 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic tuner used for a television receiver, a VTR or the like.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram of an electronic tuner having a conventional PLL channel selection circuit. In FIG. 2, 1 is an input tuning circuit, 2 is a high frequency amplifier circuit, 3 is an interstage tuning circuit,
Reference numeral 4 is a mixing circuit, 5 is an intermediate frequency tuning circuit, 6 is a local oscillation circuit, and 7 is a PLL tuning circuit.
A tuning voltage 13, which is an output signal from the input circuit, is guided to the input tuning circuit 1, the interstage tuning circuit 3, and the local oscillation circuit 6.

Reference numeral 8 is an antenna input terminal, 9 is an intermediate frequency amplifier circuit, 10 is an output terminal, 11 is an input terminal for inputting a tuning signal from a microcomputer (not shown) or the like to the PLL tuning circuit 7, and 12 is a terminal. The PLL circuit 7 outputs a lock signal output terminal for outputting a lock signal during a channel selection operation, and 14 is supplied from the intermediate frequency amplifier circuit 9 to the high frequency amplifier circuit 2.
This is a GC voltage, and a block 14 surrounded by a chain line shows an electronic tuner body.

In the electronic tuner having the above structure, when a tuning signal from a microcomputer or the like is input to the input terminal 11,
Since a part of the signal of the local oscillation circuit 6 is input to the PLL channel selection circuit 7, the P frequency is adjusted so that the tuning frequency of each stage is adjusted to the frequency based on the input data from the microcomputer.
The tuning voltage 13 is derived from the LL tuning circuit 7.

This tuning voltage 13 is applied to the input tuning circuit 1, the inter-stage tuning circuit 3 and the local tuning circuit 6, and the target frequency is selected from the signals input from the antenna input terminal 8. , High-frequency amplifier circuit 2, interstage tuning circuit 3
In the mixing circuit 4, the signal is mixed with the signal of the local oscillation frequency supplied from the local oscillation circuit 6 and converted into an intermediate frequency.

The tuning signal converted to the intermediate frequency is selected by the intermediate frequency tuning circuit 5, then guided to the intermediate frequency amplifier circuit 9, amplified and detected, and then derived from the output terminal 10.
Further, the horizontal synchronizing signal detected by the intermediate frequency amplifier circuit 9 is taken out, and the smoothed AGC voltage 14 is supplied to the high frequency amplifier circuit 2 so that the input level to the intermediate frequency amplifier circuit 9 becomes constant. The amplification degree of the high frequency amplifier circuit 2 is adjusted so as to correspond to the input signal level of the antenna input terminal 8 and control is performed so that the input signal is not saturated.

[0007]

In the above conventional apparatus, when a very strong input signal arrives at the antenna input terminal, if a PLL tuning circuit tries to tune it, during the tuning period, Since no signal is input to the intermediate frequency amplifier circuit, the AGC voltage corresponding to the input signal level is not output, and the high frequency amplifier circuit operates in the maximum amplification state,
This state continues until the tuning operation is completed.

However, near the end of the tuning operation by the PLL tuning circuit, the tuning frequency of each tuning circuit approaches the target frequency and is slightly displaced from the tuning point, but the target signal is high frequency. Since the high frequency amplifier circuit is applied as a strong input and the high frequency amplifier circuit operates in the maximum sensitivity state, the saturation state occurs and a so-called AGC lock phenomenon occurs.

When the high frequency amplifying circuit is saturated, spurious of the input signal is generated and the level thereof becomes very large. Therefore, the spurious is interstage tuning circuit, mixing circuit,
It is input to the PLL tuning circuit via a local oscillation circuit or the like. As a result, the PLL tuning circuit cannot distinguish it from the regular local oscillation signal, and the spurious signal is mistakenly recognized as the regular local oscillation signal, causing a problem that the PLL tuning circuit malfunctions.

[0010]

In order to solve the above problems, the present invention provides an electronic tuner including a high frequency amplifier circuit, a local oscillator circuit, a mixing circuit, and a PLL tuning circuit, in which the selection of the PLL tuning circuit is performed. A gain adjusting circuit for lowering the gain of the high frequency amplifying circuit is provided during the station operation period so as to prevent malfunction of the PLL channel selecting circuit with respect to a strong input signal from the antenna.

[0011]

According to the above configuration, the gain adjusting circuit keeps the gain of the high frequency amplifier circuit lowered during the period in which the PLL tuning circuit is performing the tuning operation. Even if a signal is applied, the high frequency amplifier circuit can be operated so as not to be saturated, spurious due to strong input can be prevented, and malfunction of the PLL channel selection circuit can be prevented.

[0012]

1 is a block diagram of an embodiment of the present invention.
The portion surrounded by the alternate long and short dash line has the same configuration as that of the conventional example shown in FIG. 2, and the corresponding portions are designated by the same reference numerals and the description thereof is omitted. In FIG. 1, a portion surrounded by a dotted line is a circuit forming a main part of the present invention. A parallel circuit of a resistor R ₅ and a capacitor C ₁ is connected between the lock signal output terminal 12 of the PLL tuning circuit 7 and the ground, and the lock signal output terminal 12 is connected.
A resistor R ₄ is connected between the base of a transistor Q ₂ whose emitter is grounded.

Further, the transistor Q is between _second collector and the transistor Q ₁ based connecting a resistor R _2, Between the collector and ground the transistor Q ₁ is connected to resistor R _3, the transistor Q ₁ A resistor R ₁ is connected between the base and the emitter, and the emitter of the transistor Q ₁ is supplied with the AGC voltage 13 to the high frequency amplifier circuit 2
Connect to the control terminal of.

Lock signal output terminal 1 of PLL tuning circuit 7
The lock output signal derived from 2 is the PLL tuning circuit 7
There becomes "H" in channel selection period, and turns on transistor Q _2, via the AGC line resistance R _1, R ₂ which AGC voltage 14 is supplied, a current flows through the transistor Q _2. At this time, due to the voltage divided by the resistors R ₁ and R ₂ ,
A bias voltage is applied to the base of the transistor Q ₁ ,
A current flows from the AGC line through the transistor Q ₁ and the resistor R ₃ .

As a result, the AGC voltage divided by the impedance Z _{0 of the} AGC line and the resistor R ₃ is applied to the high frequency amplification circuit 2 and acts to reduce the amplification degree (gain) of the high frequency amplification circuit 2. The reduction degree of the amplification factor of the high frequency amplifier circuit 2 is determined by the impedance Z _{0 of the} AGC line.
And the resistance R ₃ can be determined.

The parallel circuit of the resistor R ₅ and the capacitor C ₁ connected to the lock signal output terminal 12 of the PLL channel selection circuit 7 continues even after the channel selection is completed and the lock output signal becomes "L". This is for continuing the switching operation of the transistor Q _{2 for} a certain period of time, and may be added as necessary.

[0017]

Since the present invention has the above-mentioned structure, even when a strong input signal is received as an antenna input, the high frequency amplifier circuit is prevented from being saturated and spurious is suppressed from occurring.
A malfunction of the LL tuning circuit can be prevented, and a highly reliable electronic tuner can be provided.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional example.

[Explanation of symbols]

2 ... High frequency amplifier circuit 4 ... Mixing circuit 6 ... Local oscillation circuit 7 ... PLL tuning circuit 12 ... Lock signal output terminal 14 ... ·· AGC voltage Q _1, Q ₂ ····· transistor R ₃ ····· resistance

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] November 9, 1992

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 2

[Correction method] Change

[Correction content]

[Fig. 2]

Claims (1)

[Claims] 1. An electronic tuner comprising a high frequency amplifier circuit, a local oscillator circuit, a mixing circuit, and a PLL tuning circuit, wherein the gain of the high frequency amplifier circuit is adjusted during a tuning operation of the PLL tuning circuit. An electronic tuner characterized in that a gain adjusting circuit for lowering is provided so as to prevent a malfunction of the PLL tuning circuit with respect to a strong input signal from an antenna.