JPH05153511A - Television receiver - Google Patents

Television receiver

Info

Publication number
JPH05153511A
JPH05153511A JP3341902A JP34190291A JPH05153511A JP H05153511 A JPH05153511 A JP H05153511A JP 3341902 A JP3341902 A JP 3341902A JP 34190291 A JP34190291 A JP 34190291A JP H05153511 A JPH05153511 A JP H05153511A
Authority
JP
Japan
Prior art keywords
circuit
intermediate frequency
frequency signal
signal
tuner
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3341902A
Other languages
Japanese (ja)
Inventor
Yoshihiko Naito
嘉彦 内藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP3341902A priority Critical patent/JPH05153511A/en
Publication of JPH05153511A publication Critical patent/JPH05153511A/en
Pending legal-status Critical Current

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  • Picture Signal Circuits (AREA)
  • Television Receiver Circuits (AREA)

Abstract

PURPOSE:To improve the reception performance of a television broadcast. CONSTITUTION:This television receiver composed of a tuner circuit and an intermediate frequency processing circuit is provided with a detection circuit 4 detecting the presence of an adjacent channel signal and a signal level as a DC voltage level based on an intermediate frequency signal conveted by a tuner circuit 2 and the tuner circuit 2 and the intermediate frequency signal processing circuit 3 are controlled in response to a DC voltage level detected by the detection circuit 4.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明はチューナ回路と中間周
波信号処理回路を備えたテレビジョン受信装置、特にテ
レビやビデオ等の中間周波信号処理を改善するテレビジ
ョン受信装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television receiving device provided with a tuner circuit and an intermediate frequency signal processing circuit, and more particularly to a television receiving device for improving intermediate frequency signal processing for televisions and video.

【0002】[0002]

【従来の技術】図3は従来のテレビジョン受信装置の電
気的構成を示すブロック図、図4はその各部の特性図で
ある。テレビジョン受信装置100はチューナ回路10
1と中間周波信号処理回路108を備える。
2. Description of the Related Art FIG. 3 is a block diagram showing an electrical configuration of a conventional television receiver, and FIG. 4 is a characteristic diagram of each part thereof. The television receiver 100 includes a tuner circuit 10
1 and an intermediate frequency signal processing circuit 108.

【0003】チューナ回路101は入力回路103、高
周波増幅回路104、段間複同調回路105、周波数変
換回路106、および局部発振回路107から構成され
る。また、中間周波信号処理回路108はトラップ回路
109、弾性表面波を利用したバンドパスフィルタ(以
下、SAWフィルタと称する)110、中間周波増幅回
路111、検波回路112、中間周波AGC回路(以
下、IF・AGC回路と称する)113、および高周波
AGC回路(以下、RF・AGC回路と称する)114
から構成する。
The tuner circuit 101 comprises an input circuit 103, a high frequency amplifier circuit 104, an interstage double tuning circuit 105, a frequency conversion circuit 106, and a local oscillation circuit 107. Further, the intermediate frequency signal processing circuit 108 includes a trap circuit 109, a bandpass filter (hereinafter referred to as SAW filter) 110 using a surface acoustic wave, an intermediate frequency amplification circuit 111, a detection circuit 112, an intermediate frequency AGC circuit (hereinafter, IF). -AGC circuit) 113 and high-frequency AGC circuit (hereinafter referred to as RF-AGC circuit) 114
It consists of.

【0004】チューナ回路101は受信アンテナ102
で受信したテレビジョン信号から希望するチャンネルの
高周波信号f1を選び出し、選局された信号を局部発振
回路107で作られた局部発振信号f2と混合して中間
周波信号f3に変換して中間周波信号処理回路108へ
出力し、ここで中間周波信号f3を受像管(図示せず)
に必要な大きさまで増幅する。このとき、中間周波信号
f3はチューナ回路101の入力回路103と段間複同
調回路105を含む高周波増幅回路104の周波数特性
によって定まる選択度特性により隣接チャンネル信号よ
り外側の帯域は大きく減衰する。
The tuner circuit 101 includes a receiving antenna 102.
The high-frequency signal f1 of a desired channel is selected from the television signal received in step 1, and the selected signal is mixed with the local oscillation signal f2 generated by the local oscillation circuit 107 to be converted into the intermediate frequency signal f3 to obtain the intermediate frequency signal. The intermediate frequency signal f3 is output to the processing circuit 108, where a picture tube (not shown)
Amplify to the required size. At this time, the intermediate frequency signal f3 is greatly attenuated in the band outside the adjacent channel signal due to the selectivity characteristic determined by the frequency characteristic of the input circuit 103 of the tuner circuit 101 and the frequency characteristic of the high frequency amplifier circuit 104 including the interstage double tuning circuit 105.

【0005】しかし、この隣接チャンネル信号の周波数
は中間周波信号として希望チャンネル信号とともに中間
周波信号処理回路108に入力するので、それらの信号
が互いに干渉するのを防ぐためトラップ回路109やS
AWフィルタ110を用い隣接チャンネル信号を40〜
50dB減衰させ、その後中間周波信号処理を行ってい
た。
However, since the frequency of the adjacent channel signal is input to the intermediate frequency signal processing circuit 108 as an intermediate frequency signal together with the desired channel signal, the trap circuit 109 and the S circuit are provided to prevent these signals from interfering with each other.
Adjacent channel signals of 40 to 40 using the AW filter 110
It was attenuated by 50 dB, and then intermediate frequency signal processing was performed.

【0006】[0006]

【発明が解決しようとする課題】しかし、この従来の中
間周波信号処理回路は、隣接チャンネル信号の有無およ
び信号レベルを検知していないので、現在のVHF帯の
チャンネルのように殆ど隣接チャンネル信号がないとき
にもトラップ回路自身によるによる雑音指数の劣化を生
じ、また、高周波増幅回路の利得は隣接チャンネル信号
がある条件のもとに余裕を持って低めに設定しているこ
とから十分な雑音指数(NF)が得られない等の問題が
あった。
However, since the conventional intermediate frequency signal processing circuit does not detect the presence or absence of the adjacent channel signal and the signal level, almost no adjacent channel signal such as the current VHF band channel is detected. Even when there is no noise, the noise figure deteriorates due to the trap circuit itself, and the gain of the high-frequency amplifier circuit is set to a low value with a margin under certain conditions of the adjacent channel signal. There was a problem that (NF) could not be obtained.

【0007】この発明はこのような問題を解決するため
なされたもので、その目的はチャンネル間におけるトラ
ップ回路等の不要となる回路のスルー化およびチューナ
回路のAGCレベルの最適化を図ってテレビジョン放送
の受信性能を向上させたテレビジョン受信装置を提供す
ることにある。
The present invention has been made to solve the above problems, and its purpose is to make unnecessary circuits such as a trap circuit between channels unnecessary and to optimize the AGC level of a tuner circuit in a television. It is an object of the present invention to provide a television receiver having improved broadcast reception performance.

【0008】[0008]

【課題を解決するための手段】ところで、受信機の雑音
指数(受信機の出力端におけるSN比を入力端における
SN比で除した値)をNT、各段の雑音指数をN1,N
2,…Nn、各段の利得をG1,G2,…Gnとしたと
き、受信機の雑音指数NTは数1で表される。
By the way, the noise figure of the receiver (the value obtained by dividing the SN ratio at the output end of the receiver by the SN ratio at the input end) is NT, and the noise figure at each stage is N1, N.
2, ... Nn, and the gain of each stage is G1, G2, ... Gn, the noise figure NT of the receiver is expressed by Equation 1.

【0009】[0009]

【数1】 [Equation 1]

【0010】数1から利得G1が大きいほど後段の影響
を受け難いことがわかる。本発明はこの事実に鑑みて高
い利得を有する増幅器を設けることができるようにした
ものであって、前記課題を解決するため請求項1に係る
テレビジョン受信装置は、チューナ回路から出力された
中間周波信号に基いて隣接チャンネル信号の有無を検出
する検波回路を新たに設け、隣接チャンネル信号の有無
に応じてトラップ回路を使用する中間周波信号処理回路
とするか否かを決める。
It can be seen from Equation 1 that the larger the gain G1 is, the less affected the latter stage is. In view of this fact, the present invention is to provide an amplifier having a high gain. In order to solve the above problems, the television receiving apparatus according to the first aspect of the present invention is an intermediate circuit output from a tuner circuit. A detection circuit for detecting the presence or absence of the adjacent channel signal based on the frequency signal is newly provided, and it is determined whether or not the intermediate frequency signal processing circuit using the trap circuit is used according to the presence or absence of the adjacent channel signal.

【0011】また、前記課題を解決するため請求項2に
係るテレビジョン受信装置は、チューナ回路から出力さ
れた中間周波信号に基いて隣接チャンネル信号の信号レ
ベルを検出する検波回路を新たに設け、隣接チャンネル
信号レベルに応じた電圧でチューナ回路内の高周波増幅
回路の利得を制御する。
In order to solve the above-mentioned problems, a television receiver according to a second aspect of the present invention is further provided with a detection circuit for detecting the signal level of the adjacent channel signal based on the intermediate frequency signal output from the tuner circuit. The gain of the high frequency amplifier circuit in the tuner circuit is controlled by the voltage according to the adjacent channel signal level.

【0012】[0012]

【作用】本発明に係るテレビジョン受信装置は、予め増
幅回路の利得を高めに設定しておき、隣接チャンネル信
号の有無および信号レベルをDC電圧レベルとして検出
し、この検出信号レベルにしたがって高周波増幅回路お
よび中間周波増幅回路の利得を制御する。
In the television receiving apparatus according to the present invention, the gain of the amplifier circuit is set high in advance, the presence or absence of the adjacent channel signal and the signal level are detected as the DC voltage level, and the high frequency amplification is performed according to the detected signal level. Controls the gain of the circuit and the intermediate frequency amplifier circuit.

【0013】[0013]

【実施例】以下、本発明の実施例を添付図面に基いて説
明する。図1は本発明の第1実施例に係るテレビジョン
受信装置の電気的構成を示すブロック図である。
Embodiments of the present invention will be described below with reference to the accompanying drawings. 1 is a block diagram showing an electrical configuration of a television receiving apparatus according to a first embodiment of the present invention.

【0014】テレビジョン受信装置1は、チューナ回路
2、中間周波信号処理回路3、検波回路4、および切替
回路5を備える。チューナ回路2は入力回路6、高周波
増幅回路7、段間複同調回路8、周波数変換回路9、お
よび局部発振回路10からなる。
The television receiver 1 includes a tuner circuit 2, an intermediate frequency signal processing circuit 3, a detection circuit 4, and a switching circuit 5. The tuner circuit 2 includes an input circuit 6, a high frequency amplifier circuit 7, an interstage double tuning circuit 8, a frequency conversion circuit 9, and a local oscillation circuit 10.

【0015】アンテナ11で受信したテレビ高周波信号
を入力回路6で入力インピーダンスを整合させると共に
妨害となる不要な信号を排除した後、高周波増幅回路7
および段間複同調回路8で希望チャンネル信号を選択・
増幅して雑音指数(NF)を良くする。さらに、周波数
変換回路9において高周波増幅回路7で増幅した希望チ
ャンネル信号と局部発振回路10で作られた局部発振信
号を混合して中間周波信号に変換する。
After the television high frequency signal received by the antenna 11 is matched with the input impedance by the input circuit 6 and unnecessary unnecessary signals are eliminated, the high frequency amplifier circuit 7 is provided.
And a desired channel signal is selected by the interstage double tuning circuit 8.
Amplify to improve noise figure (NF). Further, in the frequency conversion circuit 9, the desired channel signal amplified by the high frequency amplification circuit 7 and the local oscillation signal generated by the local oscillation circuit 10 are mixed and converted into an intermediate frequency signal.

【0016】中間周波信号処理回路3は、トラップ回路
12、プリアンプ13、SAWフィルタ14、中間周波
増幅回路15、および検波回路16からなる。チューナ
回路2から入力された中間周波信号は、トラップ回路1
2で60.25MHz成分(国内チャンネルの場合)を
減衰させ、プリアンプ13で増幅し、SAWフィルタ1
4で帯域特性を決めた後、中間周波増幅回路15で増幅
する。この増幅した中間周波信号は検波回路16で検波
した後、その検波出力をテレビジョン信号として取り出
す。
The intermediate frequency signal processing circuit 3 comprises a trap circuit 12, a preamplifier 13, a SAW filter 14, an intermediate frequency amplification circuit 15 and a detection circuit 16. The intermediate frequency signal input from the tuner circuit 2 is transferred to the trap circuit 1
60.25MHz component (in case of domestic channel) is attenuated by 2 and amplified by preamplifier 13 and SAW filter 1
After determining the band characteristic in 4, the intermediate frequency amplifier circuit 15 amplifies the band characteristic. The amplified intermediate frequency signal is detected by the detection circuit 16, and the detected output is taken out as a television signal.

【0017】検波回路4は、帯域フィルタ(BPF)1
7、包絡線検波器18、低域フィルタ(LPF)19、
および検知回路20からなる。BPF17で中心周波数
を60.25MHzとした所定の帯域幅の中間周波成分
の信号を取り出し、包絡線検波器18でダイオードによ
る整流を行い、さらにLPF19で検波出力に残ってい
る高周波成分を減衰させて中間周波成分のみとして検知
回路20に出力する。
The detection circuit 4 includes a bandpass filter (BPF) 1
7, envelope detector 18, low-pass filter (LPF) 19,
And a detection circuit 20. The BPF 17 takes out the signal of the intermediate frequency component of the predetermined bandwidth with the center frequency of 60.25 MHz, the envelope detector 18 rectifies it by the diode, and further the LPF 19 attenuates the high frequency component remaining in the detection output. Only the intermediate frequency component is output to the detection circuit 20.

【0018】検知回路20は、コレクタを負荷抵抗21
および22を介して電源に接続し、エミッタ同士を相互
に接続したnpnトランジスタQ1およびnpnトラン
ジスタQ2のそれぞれのベースをLPF19および抵抗
23を介して電源に接続すると共に、エミッタを抵抗2
4を介して電源に接続したpnpトランジスタQ3のベ
ースおよびコレクタをトランジスタQ1のコレクタおよ
び後述する切替回路5にそれぞれ接続して構成する。こ
こで、25,26,27は、それぞれ抵抗を示す。
The detection circuit 20 has a collector connected to a load resistor 21.
And npn transistor Q1 and npn transistor Q2 whose emitters are connected to each other are connected to the power source via LPF 19 and resistor 23, and the emitter is connected to resistor 2
The base and collector of the pnp transistor Q3 connected to the power supply via 4 are connected to the collector of the transistor Q1 and the switching circuit 5 described later, respectively. Here, 25, 26, and 27 respectively show resistance.

【0019】この検知回路20は、トランジスタQ1の
ベースには、入力信号としてLPF19からの信号が加
わり、トランジスタQ3のベースには抵抗21を介して
電源電圧Vccが加えられている。トランジスタQ1お
よびQ2の差動回路で増幅された電流はトランジスタQ
3のベースに加えられている。したがって、トランジス
タQ3のコレクタ電圧は、トランジスタQ1がオフのと
きにはアース電位(Lレベル)となり、トランジスタQ
1がオンのときには抵抗24,25で分圧された電源電
圧Vcc(Hレベル)となり切替回路5に供給される。
In the detection circuit 20, the signal from the LPF 19 is applied as an input signal to the base of the transistor Q1, and the power supply voltage Vcc is applied to the base of the transistor Q3 via the resistor 21. The current amplified by the differential circuit of the transistors Q1 and Q2 is
Added to the base of 3. Therefore, the collector voltage of the transistor Q3 becomes the ground potential (L level) when the transistor Q1 is off,
When 1 is ON, the power supply voltage Vcc (H level) divided by the resistors 24 and 25 is supplied to the switching circuit 5.

【0020】切替回路5は、検知回路20の検知出力に
したがって中間周波信号処理回路3のトラップ回路12
を使用するか使用しないかのいずれか一方の回路を択一
的に選択するよう構成している。具体的には、検知出力
がLレベルのときにはトラップ回路12を使用しない回
路とし、検知出力がHレベルのときにはトラップ回路1
2を使用する回路とし、常時はこのトラップ回路12を
使用する回路としている。
The switching circuit 5 has a trap circuit 12 of the intermediate frequency signal processing circuit 3 according to the detection output of the detection circuit 20.
It is configured to selectively select either one of the circuits using or not using. Specifically, the trap circuit 12 is not used when the detection output is at the L level, and the trap circuit 1 is used when the detection output is at the H level.
2 is used as the circuit, and the trap circuit 12 is always used as the circuit.

【0021】このように構成されたテレビジョン受信装
置は、テレビジョン信号をチューナ回路2によって中間
周波信号に変換し、検波回路4および切替回路5に出力
する。このとき、検波回路4に入力した中間周波信号に
隣接チャンネル信号がない場合には検知回路20から出
力される信号はLレベルとなるので、トラップ回路12
を使用しない回路に切替わる。この不要回路(トラップ
回路12)のスルー化によって、このトラップ回路12
における信号の減衰をなくすことができ雑音指数(N
F)の劣化を防止できる。
The television receiver thus constructed converts the television signal into an intermediate frequency signal by the tuner circuit 2 and outputs it to the detection circuit 4 and the switching circuit 5. At this time, if there is no adjacent channel signal in the intermediate frequency signal input to the detection circuit 4, the signal output from the detection circuit 20 becomes L level, so the trap circuit 12
Switch to a circuit that does not use. By making this unnecessary circuit (trap circuit 12) through, the trap circuit 12
The noise figure (N
It is possible to prevent the deterioration of F).

【0022】図2は本発明の第2実施例に係るテレビジ
ョン受信装置の電気的構成を示すブロック図であり、同
一部分には同一符号を付す。テレビジョン受信装置1
は、チューナ回路2、中間周波信号処理回路3、および
検波回路40を備える。
FIG. 2 is a block diagram showing the electrical construction of a television receiving apparatus according to the second embodiment of the present invention. The same parts are designated by the same reference numerals. Television receiver 1
Includes a tuner circuit 2, an intermediate frequency signal processing circuit 3, and a detection circuit 40.

【0023】チューナ回路2は高周波増幅回路7の利得
を制御するようにしたこと以外は第1実施例と同じ構成
であるのでその説明を省略する。
The tuner circuit 2 has the same configuration as that of the first embodiment except that the gain of the high frequency amplifier circuit 7 is controlled, and the description thereof will be omitted.

【0024】中間周波信号処理回路3は、トラップ回路
12、プリアンプ13、SAWフィルタ14、中間周波
増幅回路15、検波回路16からなる第1実施例の構成
に加えIF・AGC回路28およびRF・AGC回路2
9を設けた。
The intermediate frequency signal processing circuit 3 has an IF / AGC circuit 28 and an RF / AGC circuit in addition to the configuration of the first embodiment which comprises a trap circuit 12, a preamplifier 13, a SAW filter 14, an intermediate frequency amplification circuit 15 and a detection circuit 16. Circuit 2
9 was provided.

【0025】この中間周波信号処理回路3は、検波回路
16で検波されたテレビジョン信号を利用して入力電波
の強弱に応じた電圧を発生させ、その電圧に応じて高周
波増幅回路7および中間周波増幅回路15の利得を制御
する。すなわち、入力電波が強い場合には高周波増幅回
路7および中間周波増幅回路15の利得を下げ、入力電
波が弱いときには利得を上げるようにし、チャンネルの
切替え時等において利得が変化し感度が変わるのを防ぐ
ようにしている。
The intermediate frequency signal processing circuit 3 uses the television signal detected by the detection circuit 16 to generate a voltage according to the strength of the input radio wave, and the high frequency amplifier circuit 7 and the intermediate frequency signal according to the voltage. The gain of the amplifier circuit 15 is controlled. That is, when the input radio wave is strong, the gains of the high frequency amplification circuit 7 and the intermediate frequency amplification circuit 15 are decreased, and when the input radio wave is weak, the gains are increased so that the gain is changed and the sensitivity is changed when the channel is switched. I try to prevent it.

【0026】さらに、RF・AGC回路29は、後述す
る検知回路20の出力電圧が下がったときには高周波増
幅回路7の利得を下げるよう制御する。
Further, the RF / AGC circuit 29 controls so that the gain of the high frequency amplifier circuit 7 is lowered when the output voltage of the detection circuit 20 described later is lowered.

【0027】検波回路40は、BPF17a,17b、
包絡線検波器18a,18b、LPF19a,19bお
よび検知回路20からなる。すなわち、2つの中心周波
数(54.25MHzおよび60.25MHz)につい
て所定の帯域幅の中間周波成分を取り出し、それぞれ包
絡線検波器18aおよびLPF19a、包絡線検波器1
8bおよびLPF19bを介して検知回路20へ出力す
る。
The detection circuit 40 includes BPFs 17a, 17b,
It is composed of envelope detectors 18a and 18b, LPFs 19a and 19b, and a detection circuit 20. That is, intermediate frequency components having a predetermined bandwidth are extracted with respect to the two center frequencies (54.25 MHz and 60.25 MHz), and the envelope detector 18a, the LPF 19a, and the envelope detector 1 are respectively extracted.
It outputs to the detection circuit 20 via 8b and LPF19b.

【0028】この実施例における検知回路20は、相互
に接続したコレクタの接続点に接続した可変抵抗器30
を介して電源に接続し、エミッタ同士を相互に接続した
npnトランジスタQ4およびnpnトランジスタQ5
のベースをLPF19a,19bの出力にそれぞれ接続
すると共に、エミッタをトランジスタQ4およびトラン
ジスタQ5のエミッタに接続し、コレクタを電源に接続
したnpnトランジスタQ6のベースに抵抗31を介し
て電源に接続して構成する。ここで、32,33,3
4,35は抵抗を示す。
The detection circuit 20 in this embodiment includes a variable resistor 30 connected to a connection point of collectors connected to each other.
Npn transistor Q4 and npn transistor Q5 connected to the power supply via the
Is connected to the outputs of the LPFs 19a and 19b, the emitters are connected to the emitters of the transistors Q4 and Q5, and the collectors are connected to the power supply via the resistor 31 to the base of the npn transistor Q6. To do. Where 32, 33, 3
Reference numerals 4 and 35 represent resistances.

【0029】この検知回路20は、トランジスタQ4,
Q5のそれぞれのベースには、入力信号としてLPF1
9a,19bからの信号が加わり、トランジスタQ6の
ベースには抵抗31,32で分圧された電源電圧Vcc
が加えられている。トランジスタQ4,Q5の少なくと
も一方がオンした場合には、コレクタ電流が流れ、可変
抵抗30と抵抗33または/および34で決まる分圧比
にしたがったコレクタ電圧を出力する。したがって、ト
ランジスタQ4,Q5のいずれもがオフのときには電源
電圧VccがRF・AGC回路29に供給され、それ以
外のときには分圧比にしたがったレベルの電圧がRF・
AGC回路29に供給される。
The detection circuit 20 includes transistors Q4 and Q4.
LPF1 as an input signal is connected to each base of Q5.
Signals from 9a and 19b are added to the base of the transistor Q6 and the power supply voltage Vcc divided by the resistors 31 and 32 is applied.
Has been added. When at least one of the transistors Q4 and Q5 is turned on, a collector current flows, and a collector voltage according to the voltage division ratio determined by the variable resistor 30 and the resistors 33 and / or 34 is output. Therefore, the power supply voltage Vcc is supplied to the RF / AGC circuit 29 when both the transistors Q4 and Q5 are off, and otherwise the voltage at the level according to the voltage division ratio is RF.
It is supplied to the AGC circuit 29.

【0030】このように構成されたテレビジョン受信装
置は、テレビジョン信号をチューナ回路2によって中間
周波信号に変換し、検波回路40および中間周波信号処
理回路3に出力する。このとき、検波回路40に入力し
た中間周波信号に隣接チャンネル信号があった場合、検
知回路20から出力される電圧レベルは下がるので、そ
れに応じてRF・AGC回路29はAGC電圧レベルを
下げて高周波増幅回路7の利得を最適とする。
The television receiver thus constructed converts the television signal into the intermediate frequency signal by the tuner circuit 2 and outputs it to the detection circuit 40 and the intermediate frequency signal processing circuit 3. At this time, if there is an adjacent channel signal in the intermediate frequency signal input to the detection circuit 40, the voltage level output from the detection circuit 20 decreases, and accordingly, the RF / AGC circuit 29 lowers the AGC voltage level and increases the high frequency. The gain of the amplifier circuit 7 is optimized.

【0031】[0031]

【発明の効果】本発明に係るテレビジョン受信装置は、
隣接チャンネル信号の有無および信号レベルをDC電圧
レベルとして検出し、この検出信号にしたがって高周波
増幅回路および中間周波増幅回路を制御し増幅するよう
にしたので、不要回路となるトラップ回路をスルー化で
きるとともに、高周波増幅回路のAGCレベルの最適化
を図ることができるようになり、隣接チャンネル信号が
無い場合には画質の向上が図れる等テレビジョン放送の
受信性能が向上する。
The television receiver according to the present invention is
Since the presence or absence of the adjacent channel signal and the signal level are detected as a DC voltage level and the high frequency amplifier circuit and the intermediate frequency amplifier circuit are controlled and amplified in accordance with the detected signal, the trap circuit, which is an unnecessary circuit, can be made through. Thus, the AGC level of the high frequency amplifier circuit can be optimized, and when there is no adjacent channel signal, the image quality is improved and the reception performance of television broadcasting is improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1実施例に係るテレビジョン受信装
置の電気的構成を示すブロック図
FIG. 1 is a block diagram showing an electrical configuration of a television receiving apparatus according to a first embodiment of the present invention.

【図2】本発明の第2実施例に係るテレビジョン受信装
置の電気的構成を示すブロック図
FIG. 2 is a block diagram showing an electrical configuration of a television receiver according to a second embodiment of the present invention.

【図3】従来のテレビジョン受信装置の電気的構成を示
すブロック図
FIG. 3 is a block diagram showing an electrical configuration of a conventional television receiving device.

【図4】従来のテレビジョン受信装置の各部の特性図FIG. 4 is a characteristic diagram of each part of a conventional television receiving device.

【符号の説明】[Explanation of symbols]

1…テレビジョン受信装置、2…チューナ回路、3…中
間周波信号処理回路、4,40…検波回路、5…切替回
路、6…入力回路、7…高周波増幅回路、8…段間複同
調回路、9…周波数変換回路、10…局部発振回路、1
1…アンテナ、12…トラップ回路、13…プリアン
プ、14…SAWフィルタ、15…中間周波増幅回路、
16…検波回路、17,17a,17b…帯域フィルタ
(BPF)、18,18a,18b…包絡線検波器、1
9,19a,19b…低域フィルタ(LPF)、20…
検知回路、21〜27,30〜35…抵抗、28…中間
周波AGC回路(IF・AGC回路)、29…高周波A
GC回路(RF・AGC回路)、Q1〜Q6…トランジ
スタ。
DESCRIPTION OF SYMBOLS 1 ... Television receiving device, 2 ... Tuner circuit, 3 ... Intermediate frequency signal processing circuit, 4,40 ... Detection circuit, 5 ... Switching circuit, 6 ... Input circuit, 7 ... High frequency amplification circuit, 8 ... Interstage double tuning circuit , 9 ... Frequency conversion circuit, 10 ... Local oscillation circuit, 1
1 ... Antenna, 12 ... Trap circuit, 13 ... Preamplifier, 14 ... SAW filter, 15 ... Intermediate frequency amplification circuit,
16 ... Detection circuit, 17, 17a, 17b ... Bandpass filter (BPF), 18, 18a, 18b ... Envelope detector, 1
9, 19a, 19b ... Low-pass filter (LPF), 20 ...
Detection circuit 21-27, 30-35 ... Resistance, 28 ... Intermediate frequency AGC circuit (IF / AGC circuit), 29 ... High frequency A
GC circuit (RF / AGC circuit), Q1 to Q6 ... Transistors.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 チューナ回路と中間周波信号処理回路を
備えたテレビジョン受信装置において、上記中間周波信
号処理回路はチューナ回路から出力された中間周波信号
に基いて隣接チャンネル信号の有無を検出する検波回路
を新たに設け、隣接チャンネル信号の有無に応じてトラ
ップ回路を使用する中間周波信号処理回路とするか否か
を決めることを特徴とするテレビジョン受信装置。
1. A television receiver including a tuner circuit and an intermediate frequency signal processing circuit, wherein the intermediate frequency signal processing circuit detects the presence or absence of an adjacent channel signal based on the intermediate frequency signal output from the tuner circuit. A television receiver characterized in that a circuit is newly provided, and whether or not the circuit is an intermediate frequency signal processing circuit using a trap circuit is determined according to the presence or absence of an adjacent channel signal.
【請求項2】 チューナ回路と中間周波信号処理回路を
備えたテレビジョン受信装置において、上記中間周波信
号処理回路はチューナ回路から出力された中間周波信号
に基いて隣接チャンネル信号の信号レベルを検出する検
波回路を新たに設け、隣接チャンネル信号レベルに応じ
た電圧でチューナ回路内の高周波増幅回路の利得を制御
することを特徴とするテレビジョン受信装置。
2. In a television receiver including a tuner circuit and an intermediate frequency signal processing circuit, the intermediate frequency signal processing circuit detects a signal level of an adjacent channel signal based on the intermediate frequency signal output from the tuner circuit. A television receiver characterized in that a detection circuit is newly provided to control the gain of a high frequency amplifier circuit in a tuner circuit with a voltage according to an adjacent channel signal level.
JP3341902A 1991-11-29 1991-11-29 Television receiver Pending JPH05153511A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3341902A JPH05153511A (en) 1991-11-29 1991-11-29 Television receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3341902A JPH05153511A (en) 1991-11-29 1991-11-29 Television receiver

Publications (1)

Publication Number Publication Date
JPH05153511A true JPH05153511A (en) 1993-06-18

Family

ID=18349632

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3341902A Pending JPH05153511A (en) 1991-11-29 1991-11-29 Television receiver

Country Status (1)

Country Link
JP (1) JPH05153511A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0946614A (en) * 1995-07-27 1997-02-14 Nec Corp Automatic gain control circuit and receiving front end device using the circuit
JP2006203603A (en) * 2005-01-21 2006-08-03 Funai Electric Co Ltd Television and receiver

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0946614A (en) * 1995-07-27 1997-02-14 Nec Corp Automatic gain control circuit and receiving front end device using the circuit
JP2006203603A (en) * 2005-01-21 2006-08-03 Funai Electric Co Ltd Television and receiver

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