JPH0661341A - Analog array mode integrated circuit - Google Patents

Abstract

PURPOSE:To enable the freedom on the layout of element connection layout in wiring step to be enhanced furthermore, the isolated potential to be picked-up in arbitrary positions. CONSTITUTION:Within the analog array mode integrated circuit, a diffused part 4 for isolated potential contact is laid out in the whose region of isolated parts 1 between elements 2 in a chip. Through these procedures, any more complicated wirings than those of conventional ones can be eliminated thereby enabling the delivery time cut down for the layout design.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog array type integrated circuit in which element isolation potential contacts are provided by diffusion portions.

[0002]

2. Description of the Related Art FIG. 2 is a plan view showing a layout on a chip used in a manufacturing process of a conventional analog array type integrated circuit. In the figure, 2 is an element such as a bipolar transistor and a resistor, and 3 is an element 2. Surrounding epi part (epitaxial part), 1 is a separation part for separating the elements 2, 5 is a wiring part provided in the separation part 1, 4 is a diffusion part for a separation potential contact provided in the separation part 1, and 6 is a diffusion This is a contact hole portion for the separation potential provided in the portion 4.

Next, the operation will be described. According to the conventional layout design method, the element 2 which sends out a current for element isolation and the element 2 which causes a problem when the potential of the element isolation adjacent to each other fluctuates in the diffusion section 4 for the isolation potential contact which is laid out in advance. It has been limited to a place adjacent to and in which the layout of the wiring portion 5 is possible.

[0004]

Since the conventional analog array type integrated circuit is constructed as described above, when the layout is designed, the element isolation and the wiring for obtaining the isolation potential are contacted. It is possible to
Diffusion part 4 for separation potential contact which is laid out in advance
However, if the number of such elements 2 increases in the circuit design, it becomes difficult to deal with the layout prepared in advance.
There is a problem that the number of elements 2 that cannot be used increases on the layout prepared in advance. In addition, there is a problem that the layout is likely to be restricted even in the wiring process for taking the potential of the diffusion portion 4 for the separated potential contact which is laid out in advance.

The present invention has been made in order to solve the above-mentioned problems, and improves the degree of freedom in layout of elements or the like which must have isolation potentials adjacent to each other,
Another object of the present invention is to obtain an analog array integrated circuit capable of taking a separation potential at any place.

[0006]

In the analog array integrated circuit according to the present invention, a diffusion portion for element isolation potential contact is laid out on element isolation over the entire area of the chip.

[0007]

In the analog array integrated circuit according to the present invention, the degree of freedom in the layout of elements or the like that must be separated adjacent to each other is improved, and the separated potential can be taken at any place. Therefore, the elements can be effectively used when connecting the elements prepared in advance in the wiring step, and the layout of the wiring portion for taking the separation potential becomes extremely easy.

[0008]

EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 to 6 are the same as those in the conventional layout of FIG. The difference from FIG. 1 is that a diffusion portion 4 for isolation potential contact is laid out as shown by hatching in the entire area of the isolation portion 1.

Next, the operation will be described. 1 is shown in FIG.
The diffusion portion 4 for the separation potential contact is laid out in the entire area of the separation portion 1 described in 1. Thus, when a circuit is formed by connecting the element 2 to the wafer in the master step in which transistors and resistors are laid out in advance in the master step by the layout in the slicing step of the wiring portion 5 and the like, an element for sending out a current for element isolation. Even if the number of elements that become defective when the potential of separation between adjacent elements changes, the degree of freedom in layout of these elements increases, and the utilization rate of the master element used in the master process is improved. Furthermore, since the separation potential can be taken at any place, the layout of the wiring section 5 can be facilitated.

[0010]

As described above, according to the present invention, since the diffusion portion for the element isolation potential contact is provided in the element isolation portion over the entire area of the chip, the isolation potential must be taken adjacently. Since the degree of freedom in the layout of elements that cannot be used is increased, the utilization rate of the master element is improved. Further, since it is possible to take the separation potential at an arbitrary place, there is an effect that the layout of the wiring portion is easy.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of the present invention.

FIG. 2 is a plan view showing a layout in a manufacturing process of a conventional analog array integrated circuit.

[Explanation of symbols]

 1 Separation part 2 element 4 Diffusion part

Claims (1)

[Claims] 1. An analog array integrated circuit in which a plurality of elements are arranged on a chip via a separation section, and a diffusion section for a separation potential contact for taking a separation potential between elements is provided in the entire area on the chip. An analog array integrated circuit provided in the separation section.