JPH0660203A - Microprocessor - Google Patents

Abstract

PURPOSE:To make it unnecessary to provide an operation start control circuit for controlling an operation start of an internal control circuit, as an external circuit, and also, to suppress a delay time to the operation start of the internal control circuit to the absolute minimum, in the case of constituting a system by using plural microprocessors formed by containing a clock generating circuit. CONSTITUTION:After a power source is turned on or after it is reset, whether an internal generation clock is stabilized by synchronizing with a reference clock or not is monitored, and until the internal generation clock is stabilized by synchronizing with the reference clock, an nMOS transistor 44 is turned on, and in the case the internal generation clock is stabilized by synchronizing with the reference clock, the nMOS transistor 44 is turned off, and also, in the case an external terminal 36 becomes a high level from a low level, inhibition of an operation start to an internal control circuit 43 of an operation start control circuit 48 is released.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor having a clock generation circuit for generating a clock synchronized with a reference clock supplied from the outside.

[0002]

2. Description of the Related Art In recent years, in order to perform an operation synchronized with a high speed clock, an internal clock generation circuit for generating a clock synchronized with an externally supplied reference clock is built in,
An increasing number of microprocessors are configured to operate in synchronization with the clock generated by this clock generation circuit.

Here, as the clock generation circuit, a PL
Although an L (phase locked loop) circuit or the like is used, in a conventional microprocessor configured to incorporate such a clock generation circuit, when the internal clock is synchronized with the reference clock after power-on or reset. There was no way to know if it was stable.

Therefore, when a system is constructed by using a plurality of conventional microprocessors each having a built-in clock generation circuit, the clocks generated in these microprocessors are sufficiently synchronized with the reference clock. It is necessary to configure the system so that the internal control circuit (MPU unit, CPU unit) of the microprocessor operates after the lapse of the period assumed to be stable.

FIG. 16 is a block diagram showing a main part of an example of such a system. In the figure, 1 is a reference clock generation circuit for generating a reference clock, 2-4 are conventional microprocessors having a built-in clock generation circuit, and 5 is an operation start control for controlling the operation start of the internal control circuits of the microprocessors 2-4. A circuit, 6 is a memory shared by the microprocessors 2 to 4, and 7 is a bus line.

In such a system, as shown in FIG. 17A, when the power is turned on and the power is stabilized,
As shown in B, the reference clock generation circuit 1 generates a reference clock, which is supplied to the microprocessors 2 to 4.

As a result, in each of the microprocessors 2 to 4, a clock is generated by the built-in clock generation circuit as shown in FIGS. 17C to 17E. In general, the microprocessors 2 to 4 are stable with time variations even when the microprocessors 2 to 4 have different standards, and even when the microprocessors have the same standard.

Here, for example, first, at time T1, the internally generated clock of the microprocessor 3 stabilizes in synchronization with the reference clock, and then at time T2, the internally generated clock of the microprocessor 2 synchronizes with the reference clock. Then, an example is shown in which the internally generated clock of the microprocessor 4 stabilizes in synchronization with the reference clock at time T3.

In this system, there is no way to know this even though all the internally generated clocks of the microprocessors 2 to 4 become stable in synchronization with the reference clock at time T3.

Therefore, in consideration of a sufficient margin, before the period in which the internally generated clocks of the microprocessors 2 to 4 are assumed to be sufficiently stable has elapsed, the operation start control circuit 5 outputs an operation inhibition signal to the microprocessor. Processor 2
To 4 to suppress the start of operation of the internal control circuits of the microprocessors 2 to 4,
At time T4 when the period in which it is assumed that the internally generated clock of 4 is sufficiently stable has elapsed, the supply of the operation suppression signal is stopped,
The control for releasing the inhibition of the operation start to the internal control circuits of the microprocessors 2 to 4 has been performed.

[0011]

As described above, when a system is constructed by using a plurality of conventional microprocessors each having a built-in clock generation circuit, it is necessary to stabilize the internally generated clock among the plurality of microprocessors. The longest period must be considered to determine the valid period of the operation suppression signal, which complicates the system design and the minimum delay required before the internal control circuit starts operating. Useless delay period Δ exceeding time ΔDT1
There was a problem that DT2 had to be set.

In view of the above points, the present invention provides a system using a plurality of microprocessors each having a built-in clock generation circuit.
It is not necessary to provide an operation start control circuit that controls the operation start of the internal control circuit as an external circuit, and the system design can be simplified accordingly, and the delay time until the operation start of the internal control circuit is required. It is an object of the present invention to provide a microprocessor which can be suppressed to the limit and whose system rise time can be shortened accordingly.

[0013]

FIG. 1 is a diagram for explaining the principle of the present invention, in which 8 is a microprocessor main body and 9-1.
Reference numeral 1 is an external terminal, and 12 is a clock generation circuit for generating an internally generated clock synchronized with a reference clock supplied from the outside via the external terminal 9.

Reference numeral 13 is a switch element. One end 13A of the switch element 13 is connected to the external terminal 10 and the other end 13B is connected to a low level power source, for example, a ground line.

Further, 14 monitors whether or not the internally generated clock is stable in synchronization with the reference clock after the clock generation circuit 12 starts or restarts the generation of the internally generated clock, and the internally generated clock becomes the reference clock. The switching element 13 is kept in the ON (conducting) state until it becomes stable in synchronization, and when the internally generated clock is stable in synchronization with the reference clock, the switching element 13 is kept in the OFF (non-conducting) state. It is a monitoring circuit.

Reference numeral 15 is an internal control circuit to which an internally generated clock is supplied, and 16 is an internal control circuit when the external terminal 11 is at a low level when the clock generation circuit 12 starts or restarts the generation of the internally generated clock. This is an operation start control circuit that suppresses the operation start of the control circuit 15 and releases the operation start suppression for the internal control circuit 15 when the external terminal 11 is set to the high level.

[0017]

When a system is constructed by using a plurality of, for example, two microprocessors of the present invention, they are connected as shown in FIG. In the figure, 17 and 18 are microprocessors of the present invention, 19 and 20 are external terminals corresponding to the external terminal 9, and 21 and 22 are external terminals corresponding to the external terminal 10.

Further, 23 and 24 are external terminals corresponding to the external terminal 11, 25 and 26 are switch elements corresponding to the switch element 13, 27 and 28 are operation start control circuits corresponding to the operation start control circuit 16, and 29 is A power supply line for supplying the power supply voltage Vcc, 30 is a resistor, and 31 is a bus line.

In such a connection, when the clock generation circuit (not shown) of the microprocessors 17 and 18 starts or restarts the generation of the internally generated clock in response to the supply of the reference clock, both internally generated clocks are generated. In a state where the switch elements 25 and 26 are not stable in synchronization with the reference clock, the switch elements 25 and 26 are turned on.

As a result, the external terminals 21 to 24 become low level, and the operation start control circuits 27 and 28 respectively
The start of operation of the internal control circuits of the microprocessors 17 and 18 will be suppressed.

After that, when either one of the internally generated clocks of the microprocessors 17 and 18 becomes stable in synchronization with the reference clock and the other becomes unstable in synchronization with the reference clock, the switch element 25 , 26, one of them is turned off, while the other is kept on.

As a result, the external terminals 21 to 24 maintain the low level, and the operation start control circuits 27 and 28 maintain the inhibition of the operation start of the internal control circuits of the microprocessors 17 and 18, respectively.

After that, the microprocessor 1
When both the internally generated clocks of 7 and 18 become stable in synchronization with the reference clock, the switch elements 25 and 26
Is turned off.

As a result, the external terminals 21 to 24 become high level, and the operation start control circuits 27 and 28 respectively
The suppression of the start of the operation of the internal control circuits of the microprocessors 17 and 18 is released.

In this way, when a system is constructed using a plurality of microprocessors each having a built-in clock generation circuit, when the microprocessor of the present invention is used, the generation of the internally generated clock is started or When restarted, the operations of the internal control circuits of all the microprocessors can be started at the same time when the internally generated clocks of all the microprocessors are in a stable state in synchronization with the reference clock.

Therefore, of the plurality of microprocessors used, the one in which the internally generated clock takes the longest period to stabilize in synchronization with the reference clock is examined, and the operation start control circuit adapted to this is considered as an external circuit. Since it is not necessary to provide it, the design of the system can be facilitated accordingly.

Further, since the operation of the internal control circuit can be started when the internally generated clocks of all the microprocessors are both in a stable state in synchronization with the reference clock, an extra delay in consideration of a margin can be made. There is no need to set the time, and the delay time until the start of the operation of the internal control circuit can be suppressed to the necessary minimum, and the rise time of the system can be shortened accordingly.

As shown in FIG. 3, the input terminal 16A of the operation start control circuit 16 may be connected to the external terminal 10 instead of being connected to the external terminal 11.
In this case, the external terminal 11 becomes unnecessary,
The number of external terminals can be reduced.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first and second embodiments of the present invention will be described below with reference to FIGS.

First Embodiment FIG. 4 to FIG. 14 FIG. 4 is a block diagram showing an essential part of the first embodiment of the present invention, in which 33 is a microprocessor main body and 34 to 36.
Is an external terminal, and 37 is a phase difference detection circuit that receives a reference clock supplied from the outside and detects a phase difference between the reference clock and an internally generated clock.

Reference numeral 38 denotes a shift register to which the phase difference detection signal output from the phase difference detection circuit 37 is input, and 3
Reference numeral 9 denotes a digital variable oscillation circuit that outputs a clock having a frequency corresponding to the phase difference detection signal input to the shift register 38.

Reference numeral 40 is a frequency dividing circuit for dividing the clock output from the digital variable oscillating circuit 39. In the present embodiment, these phase difference detecting circuit 37, shift register 38, digital variable oscillating circuit 39, Frequency divider circuit 40
The clock generation circuit is composed of a PLL circuit that generates an internally generated clock synchronized with the reference clock.

Further, 41 is a four-phase clock generation circuit for converting the internally generated clock output from the frequency dividing circuit 40 into four-phase clocks, 42 is a buffer provided on the output side of the four-phase clock generation circuit 41, and 43 is It is an internal control circuit to which an internally generated clock converted into a four-phase clock is supplied.

Further, 44 is an nMOS forming a switching element
The transistor 45 monitors the phase difference detection circuit 37,
When generation of the internally generated clock is started or restarted by power-on or reset, it is determined whether the internally generated clock is stable in synchronization with the reference clock and until the internally generated clock is stable in synchronization with the reference clock. Is a stable display signal output circuit that outputs a low level signal and outputs a stable display signal of high level when the internally generated clock is stable in synchronization with the reference clock.

A switch control circuit 46 supplies a signal obtained by inverting the signal supplied from the stable display signal output circuit 45 to the nMOS transistor 44 and controls ON / OFF thereof.

The switch control circuit 46 is, for example, D
A flip-flop is used, a clock output from the buffer 42 is input to its clock input terminal, a stable display signal is data input in synchronization with this clock, and its inverted output is given to the nMOS transistor 44. .

Reference numeral 47 is an input circuit for internally taking in the data input to the external terminal 36. The input circuit 47 synchronizes the data input to the external terminal 36 with the clock output from the buffer 42. Configured to latch.

Reference numeral 48 inhibits the operation start of the internal control circuit 43 when the external terminal 36 is set to the low level when the generation of the internally generated clock is started or restarted by power-on or reset. Terminal 3
When 6 is at a high level, the operation start control circuit releases the inhibition of the operation start to the internal control circuit 43.

Here, the phase difference detection circuit 37 is specifically constructed, for example, as shown in FIG. 49 in the figure
Is a reference clock input terminal to which a reference clock is input, 5
Reference numeral 0 is an internally generated clock input terminal to which an internally generated clock is input, and 51 is a reset signal input terminal to which a reset signal / RESET is input.

Reference numeral 52 is a reference clock rising edge detection circuit for detecting the rising edge of the reference clock, and 53 is an internally generated clock rising edge detection circuit for detecting the rising edge of the internally generated clock.

Reference numeral 54 is a circuit for detecting the phase difference between the reference clock rise detection signal obtained at the node 55 and the internally generated clock rise detection signal obtained at the node 56, and 57 is the phase difference for outputting the phase difference detection signal. This is a detection signal output terminal.

The shift register 38 is specifically constructed as shown in FIGS. 6 and 7, for example. In the figure, 58 is a phase difference detection signal input terminal to which a phase difference detection signal is input, 59 is a clock input terminal to which a clock CLK is input, and 60 is a reset signal input terminal to which a reset signal / RESET is input.

61 _n , 61 _n-1 , 61 ₁ , 61 ₀ are output terminals for outputting output signals Q _n , Q _n-1 , Q ₁ , Q ₀ , 6
Reference numeral 2 is a repeating unit, and each stage between the output terminal 61 _n-1 and the output terminal 61 ₁ is configured by repeating the circuit portion indicated by reference numeral 62.

The digital variable oscillation circuit 39 is specifically constructed as shown in FIG. 8, for example. In the figure,
63 _n , 63 _n-1 , 63 ₄ , 63 ₃ , 63 ₂ , 63 ₁ , 63 ₀
Are signals Q _n , Q _n−1 output from the shift register 38,
Q ₄ , Q ₃ , Q ₂ , Q ₁ , and Q ₀ are input signals I _n , I _n-1 , I ₄ ,
Input terminals I ₃ , I ₂ , I ₁ , and I ₀ are input, and 64 is a clock output terminal to which the clock CLK is output.

9 and 10 are logic circuit diagrams showing the operation of the digital variable oscillation circuit 39. In FIG. 9, I _n =
0, I _n-1 = 0, I ₄ = 0, I ₃ = 0, I ₂ = 0, I ₁ =
0 and I ₀ = 1 show the state where the oscillation frequency is maximized, and the thick solid line 65 indicates the activated portion.

Further, FIG. 10 shows that I _n = 1, I _n-1 = 0, I ₄
= 0, I ₃ = 0, I ₂ = 0, I ₁ = 0, I ₀ = 0, the oscillation frequency is set to the minimum, and the portion indicated by the thick solid line 66 is the activated portion. .

Further, the stable display signal output circuit 45 is specifically constructed, for example, as shown in FIG. In the figure, 67 is a reference clock rising edge detection signal input terminal for inputting a reference clock rising edge detection signal obtained at the node 55 of the reference clock rising edge detection circuit 52 of the phase difference detection circuit 37.

Reference numeral 68 denotes an internally generated clock rising edge detection signal input terminal for inputting an internally generated clock rising edge detection signal obtained at the node 56 of the internally generated clock rising edge detection circuit 53 of the phase difference detection circuit 37, and 69 and 7.
Reference numeral 0 is an integrating circuit, and 71 and 72 are hysteresis inverters.

FIG. 12 is a waveform diagram for explaining the operation of the stable display signal output circuit 45, and FIG. 12A shows the reference clock input to the reference clock input terminal 49 of the phase difference detection circuit 37. FIG. 12B is a waveform diagram showing an internally generated clock input to the internally generated clock input terminal 50.

FIG. 12C is a waveform diagram showing the reference clock rising edge detection signal obtained at the node 55 of the reference clock rising edge detection circuit 52, and FIG. 12D is the internally generated clock rising edge obtained at the node 56 of the internally generated clock rising edge detection circuit 53. It is a wave form diagram which shows a detection signal.

Further, FIG. 12E shows a stable display signal output circuit 4
12 is a waveform diagram showing a signal obtained at node 73 of FIG.
6 is a waveform diagram showing a signal obtained at a node 74 of the stable display signal output circuit 45. FIG.

12G is a waveform diagram showing the output signal of the integrating circuit 69, FIG. 12H is a waveform diagram showing the output signal of the integrating circuit 70, a waveform diagram showing the output signal of the hysteresis inverter 71, and FIG. Inverter 72
FIG. 12K is a waveform diagram showing a stable display signal output from the stable display signal output circuit 45.

When a system is constructed by using a plurality of, for example, three microprocessors of this embodiment, they are connected as shown in FIG. 13, for example. 7 in the figure
Reference numeral 5 is a reference clock generation circuit for generating a reference clock.

Reference numerals 76 to 78 are microprocessors of this embodiment, 79 to 81 are external terminals corresponding to the external terminals 34 (see FIG. 4), and 82 to 84 are external terminals corresponding to the external terminals 35 (see FIG. 4). It is a terminal.

Further, 85 to 87 are external terminals corresponding to the external terminal 36 (see FIG. 4), and 88 to 90 are nMOS transistors corresponding to the nMOS transistor 44 (see FIG. 4).

Further, 91 to 93 are operation start control circuits 48.
(See FIG. 4), 94 is a power supply line for supplying the power supply voltage Vcc, 95 is a resistor, 96 is a memory shared by the microprocessors 76 to 78, 9
7 is a bus line.

FIG. 14 is a waveform diagram for explaining the operation of the system shown in FIG. 13, FIG. 14A is a waveform diagram showing the power supply voltage Vcc, and FIG. 14B is a reference output from the reference clock generation circuit 75. It is a wave form diagram which shows a clock.

Further, FIG. 14C shows a microprocessor 76.
14D is a waveform diagram showing an internally generated clock of FIG. 14D, and FIG. 14D is a waveform diagram showing a stable display signal output from a stable display signal output circuit (not shown) of the microprocessor 76.

FIG. 14E shows the microprocessor 77.
14F is a waveform diagram showing the internally generated clock of FIG. 14F, and FIG. 14F is a waveform diagram showing the stable display signal output from the stable display signal output circuit (not shown) of the microprocessor 77.

Further, FIG. 14G shows a microprocessor 78.
14H is a waveform diagram showing the internally generated clock, FIG. 14H is a waveform diagram showing the stable display signal output from the stable display signal output circuit (not shown) of the microprocessor 78, and FIG. 14I is the level of the external terminals 82-87. It is a waveform diagram.

In such a system, as shown in FIG. 14A, when the power is turned on and the power supply voltage is stabilized, the reference clock generation circuit 75 generates a reference clock as shown in FIG. 14B, which is the microprocessor 76. ~ 78.

As a result, in response to the reference clock, the microprocessors 76 to 78 start to generate internally generated clocks, as shown in FIGS. 14C, 14E and 14G, respectively.

In the state where the internally generated clocks of the microprocessors 76 to 78 are not stable in synchronization with the reference clock, the nMOS transistors 88 to 90 are provided.
Is turned on.

As a result, as shown in FIG. 14I, the external terminals 82 to 87 become low level, and the operation start control circuit 9
1 to 93 are microprocessors 76 to 78, respectively.
The operation start of the internal control circuit of is suppressed.

If, for example, at time T1, the internally generated clock of the microprocessor 77 is stable in synchronization with the reference clock, as shown in FIG. 14F, a stable display signal output circuit (not shown) in the microprocessor 77. The stable display signal having a high level is output from (d).

Then, in response to this, a switch control circuit (not shown) in the microprocessor 77 supplies a low level signal obtained by inverting the stable display signal of high level to the nMOS transistor 89, and the nMOS transistor 89. 89 is turned from ON to OFF.

In this case, the microprocessors 76, 78
Since the nMOS transistors 88 and 89 are still in the ON state, as shown in FIG.
87 maintains a low level, and operation start control circuits 91 to 9
3 maintains the inhibition of the operation start to the internal control circuits of the microprocessors 76 to 78, respectively.

Thereafter, for example, at time T2, assuming that the internally generated clock of the microprocessor 76 is stable in synchronization with the reference clock, as shown in FIG. 14D, a stable display signal output circuit (not shown) in the microprocessor 76 is provided. The stable display signal having a high level is output from (d).

Then, in response to this, a switch control circuit (not shown) in the microprocessor 76 supplies a low level signal obtained by inverting the stable display signal of high level to the nMOS transistor 88, and the nMOS transistor 88. Change 88 from ON to OFF.

Even in this case, since the nMOS transistor 90 of the microprocessor 78 is still in the ON state, the external terminals 82 to 8 as shown in FIG. 14I.
7 maintains a low level, and operation start control circuits 91 to 93
Maintain the inhibition of the operation start to the internal control circuits of the microprocessors 76 to 78, respectively.

Thereafter, for example, assuming that the internally generated clock of the microprocessor 78 becomes stable in synchronization with the reference clock at time T3, as shown in FIG. 14H, a stable display signal output circuit (not shown) in the microprocessor 78 is provided. )
Outputs a stable display signal of high level.

Then, in response to this, a switch control circuit (not shown) in the microprocessor 78 supplies a low level signal obtained by inverting the stable display signal of high level to the nMOS transistor 90, and the nMOS transistor 90. Turn 90 from ON to OFF.

Here, nMOS transistors 88 to 90 are provided.
Are all turned off, the external terminals 82-87
Becomes high level, and the operation start control circuits 91 to 93
The inhibition of the start of operation of the internal control circuits of the microprocessors 76 to 78 is released.

As described above, in the case where a system is constructed using a plurality of microprocessors each having a built-in clock generation circuit, when the microprocessor of the first embodiment is used, the internally generated clock is generated. When is started or restarted, the operation of the internal control circuits of all the microprocessors can be started at the same time when the internally generated clocks of all the microprocessors become stable in synchronization with the reference clock. .

Therefore, of the plurality of microprocessors to be used, the one in which the internally generated clock has the longest period until it stabilizes in synchronization with the reference clock is examined, and the operation start control circuit adapted to this is considered as an external circuit. Since it is not necessary to provide it, the design of the system can be facilitated accordingly.

Further, when the internally generated clocks of all the microprocessors are both in a stable state in synchronization with the reference clock, the operation of the internal control circuits of all the microprocessors can be started, so that the margin is increased. There is no need to set an extra delay time that is expected, and the delay time until the start of the operation of the internal control circuit can be suppressed to the necessary minimum, and the rise time of the system can be shortened accordingly.

Second Embodiment FIG. 15 FIG. 15 is a block diagram showing the essential parts of a second embodiment of the present invention. In the second embodiment, an input terminal 47A of an input circuit 47 is used.
Is connected to the external terminal 35, and the other parts are configured similarly to the first embodiment.

According to the second embodiment, when a system is constructed by using a plurality of microprocessors each having a built-in clock generation circuit, the external terminals corresponding to the external terminals 35 are connected by wiring, and By supplying a high-level power source to this wiring via a resistor, the same effect and advantage as in the case of using the first embodiment can be obtained, and the external terminal 36 shown in FIG. The number of can be reduced by one.

[0079]

When a system is constructed using a plurality of microprocessors each having a built-in clock generation circuit, when the microprocessor of the present invention is used, the generation of the internally generated clock is started or restarted. In this case, the operation of the internal control circuits of all microprocessors can be started at the same time when the internally generated clocks of all microprocessors are both in a stable state in synchronization with the reference clock. Among the microprocessors of, the one with the longest period until the internally generated clock stabilizes in synchronization with the reference clock is considered, and it is not necessary to provide an operation start control circuit matching this, as an external circuit. The system design can be simplified and an extra delay time is set in consideration of the margin. It is not necessary, it is possible to suppress the delay time until the start of operation of the internal control circuit to a minimum, which makes it possible to shorten the rise time of the system.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a usage example of the microprocessor of the present invention.

FIG. 3 is a diagram illustrating the principle of the present invention.

FIG. 4 is a block diagram showing a main part of the first embodiment of the present invention.

FIG. 5 is a logic circuit diagram showing a phase difference detection circuit which constitutes a first embodiment of the present invention.

FIG. 6 is a logic circuit diagram showing a part of a shift register which constitutes a first embodiment of the present invention.

FIG. 7 is a logic circuit diagram showing a part of a shift register which constitutes a first embodiment of the present invention.

FIG. 8 is a logic circuit diagram showing a digital variable oscillating circuit which constitutes a first embodiment of the present invention.

FIG. 9 is a logic circuit diagram showing a case where the digital variable oscillating circuit constituting the first embodiment of the present invention outputs the highest frequency.

FIG. 10 is a logic circuit diagram showing a case where the digital variable oscillating circuit constituting the first embodiment of the present invention outputs the lowest frequency.

FIG. 11 is a circuit diagram showing a stable display signal output circuit that constitutes the first embodiment of the present invention.

FIG. 12 is a waveform chart for explaining the operation of the stable display signal output circuit that constitutes the first embodiment of the present invention.

FIG. 13 is a block diagram showing an example of use of the first embodiment of the present invention.

FIG. 14 is a waveform chart for explaining the operation of the system shown in FIG.

FIG. 15 is a block diagram showing a main part of a second embodiment of the present invention.

FIG. 16 is a block diagram showing a usage example of a conventional microprocessor including a clock generation circuit.

FIG. 17 is a waveform diagram for explaining the operation of the system shown in FIG.

[Explanation of symbols]

 8 Microprocessor Main Body 9-11 External Terminal 12 Clock Generation Circuit 13 Switch Element 14 Synchronous Monitoring Circuit 15 Internal Control Circuit 16 Operation Start Control Circuit

Claims (4)

[Claims] 1. A clock generation circuit (12) for generating an internally generated clock synchronized with a reference clock supplied from the outside through a first external terminal (9), and one end (13A).
To the second external terminal (10) and the other end (13B)
Switch element connected to a low-level power supply (13)
Then, after the clock generation circuit (12) starts or restarts the generation of the internally generated clock, it is monitored whether the internally generated clock is stable in synchronization with the reference clock, and the internally generated clock is checked. The switch element (13) is turned on until it stabilizes in synchronization with the reference clock, and the switch element (13) is turned off when the internally generated clock stabilizes in synchronization with the reference clock. And a clock generation circuit (12) connected to the synchronization monitoring circuit (14) and a third external terminal (11).
After starting or restarting the generation of the internally generated clock,
When the third external terminal (11) is set to the low level, the operation start of the internal control circuit (15) to which the internally generated clock is supplied is suppressed, and the third external terminal (1)
1) is set to a high level, the microprocessor is characterized by including an operation start control circuit (16) for releasing the inhibition of the operation start to the internal control circuit (15). . 2. A clock generation circuit (12) for generating an internally generated clock synchronized with a reference clock supplied from the outside through a first external terminal (9), and one end (13A).
To the second external terminal (10) and the other end (13B)
Switch element connected to a low-level power supply (13)
Then, after the clock generation circuit (12) starts or restarts the generation of the internally generated clock, it is monitored whether the internally generated clock is stable in synchronization with the reference clock, and the internally generated clock is checked. The switch element (13) is turned on until it stabilizes in synchronization with the reference clock, and the switch element (13) is turned off when the internally generated clock stabilizes in synchronization with the reference clock. And the clock generation circuit (1) connected to the synchronization monitoring circuit (14) and the second external terminal (10).
When the second external terminal (10) is set to the low level after 2) starts or restarts the generation of the internally generated clock, the operation of the internal control circuit (15) to which the internally generated clock is supplied. When the start is suppressed and the second external terminal (10) is set to the high level, an operation start control circuit (16) for releasing the suppression of the operation start to the internal control circuit (15) is incorporated. A microprocessor characterized by being configured as follows. 3. The internal clock generation circuit (12) detects at least a phase difference between the reference clock and the internally generated clock, and a phase difference detection output from the phase difference detection circuit. 2. A shift register to which a signal is input, and a digital variable oscillation circuit that outputs a clock having a frequency corresponding to the phase difference detection signal input to the shift register are provided. Or the microprocessor according to 2. 4. The switch element (13) is composed of an nMOS transistor, its drain is connected to the second external terminal (10), its source is grounded, and its gate voltage is the synchronous monitoring circuit (14). The microprocessor according to claim 1, 2 or 3, wherein the microprocessor is configured to be controlled by (1).