JPH0659888A - Information processing unit having branched history table - Google Patents

Abstract

PURPOSE:To quicken branching for a restoration processing by indexing a branch history table with a value of a stack pointer as a key so as to use the branching history table. CONSTITUTION:An output of an instruction counter adder 232 for instruction advance fetch is selected at the time of the instruction advance fetch after an instruction counter represented by an instruction advance fetch instruction counter 231. The output of a selector 233 is fed to selectors 230, 240. The selector 230 is an input selector of the instruction advance fetch instruction counter 231 and selects either the initial value sent from an operation execution device or a revised value of the instruction fetch instruction counter 231 being an output of the selector 233. The selector 240 is a selector selecting an index address of a branching history table 24 and selects an output of a stack pointer 222 or an output of the selector 233. The output of the stack pointer 222 is selected at the time of the processing of a sub routine return instruction processing and instruction fetch address information being the output of the selector 233 is selected in the other case.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a branch history table, and more particularly to registering a branch history table and index processing for reading and returning a subroutine.

[0002]

2. Description of the Related Art Conventionally, some information processing apparatuses of this type have a branch history table for processing branch instructions at high speed. For the branch history table, see "Branch predi
ctionstrategies and Branch Target Buffer Design ''
J. K. F. Lee, A .; J. Smitl IEEE
It is described in COMPUTER 1984 Jan. Further, as a method of accelerating the read / restore instruction of the subroutine, there is a method of providing a small capacity stack in the processor. "32-bit MPU GMICR with improved pipeline processing efficiency by adopting the preceding jump processing
O / 100 ”Yoshida et al., Nikkei Electronics 1989.
Described in 7.10 as a PC stack.

[0003]

A conventional branch history table is provided with a table for storing an address in which a branch instruction is stored and a branch destination address of the branch instruction as a pair, and the table is indexed when the instruction is read. The predicted value of is output. However, since the return instruction from the subroutine branches to the instruction next to the subroutine read instruction that has read the subroutine, the return address from the shared subroutine called from several places will always be different, and the past branch history is used. The branch history table didn't help.

There is also a processor such as GMICRO / 100 in which a dedicated PC stack is provided in the processor to accelerate the return processing of the subroutine. However, there is a drawback that the amount of hardware (HW) increases because it is necessary to prepare a dedicated stack only for speeding up the subroutine return instruction. Further, there is a drawback that it is not effective for reading a subroutine having a deeper nest than the size of the dedicated stack.

[0005]

An information processing apparatus of the present invention comprises a stack pointer and an instruction set including a subroutine call instruction and a subroutine return instruction using the stack pointer, as a mechanism for supporting the use of the subroutine. In an information processing apparatus having a branch history table that stores a branch instruction address and a branch destination address of the branch instruction as a pair, an instruction decoding means for detecting the subroutine call instruction and the subroutine return instruction, and an output of the instruction decoding means In response to the instruction fetch address, the first selector means for switching the output of the stack pointer and the instruction execution, when the instruction being executed is a predetermined branch instruction, the address where the branch instruction is stored, The instruction being executed is the same as the subroutine call instruction. Second selector means for selecting the output of the stack pointer updated by the subroutine call instruction, and third selector means for switching the branch destination address of the branch instruction and the return address from the subroutine call by the subroutine call instruction. When,
The branch history table means uses the output of the first selector means as an index key, the output of the second sector means as a registration key, and the output of the third selector means as registration data.

Further, the information processing apparatus of the present invention, as a mechanism for supporting the use of a subroutine, a plurality of stack pointers, mode information indicating the number of the stack pointer currently valid, a subroutine call instruction using the stack pointer, and In the information processing device having an instruction set including a sub routine return instruction, and having a branch history table for storing a branch instruction address and a branch destination address of the branch instruction as a pair, the subroutine read instruction and the subroutine return instruction are detected. Instruction decoding means, first selector means for switching the instruction fetch address and the output of the stack pointer in response to the output of the instruction decoding means, and the second selector for selecting the stack pointer number included in the mode information. Means and lives being executed when executing instructions Is a predetermined branch instruction, the address in which the branch instruction was stored, and when the instruction being executed is the subroutine read instruction, the output of the stack pointer updated by the subroutine read instruction is selected. Selector means, a fourth selector means for selecting the stack pointer number of the stack pointer selected by the third selector means, a branch destination address of the branch instruction and a return address from the subroutine read by the subroutine call instruction. The output of the fifth and selector means for switching between the first and second selector means is an index key, the outputs of the third and fourth selector means are registration keys, and the output of the fifth selector means is registered. It has the branch history table means for data.

Furthermore, the information processing apparatus of the present invention is provided with a subroutine read instruction and a subroutine return instruction using a general-purpose register without using a dedicated stack pointer as a mechanism for supporting the use of the subroutine, and the address of the branch instruction. In an information processing device having a branch history table for storing a branch destination address of the branch instruction as a pair, in response to an output of the instruction decoding means for detecting the subroutine read instruction and the subroutine return instruction, and an output of the instruction decoding means. First selector means for switching the instruction fetch address and the address generated by the subroutine return instruction, and second sector means for selecting the register number of the general-purpose register used in place of the stack pointer when generating the address. When executing an instruction, the instruction being executed is Third selector means for selecting the address in which the branch instruction was stored when the branch instruction was determined, and the return address stored by the subroutine read instruction when the instruction being executed was the subroutine read instruction , Fourth selector means for selecting a register number of a general-purpose register used in place of a stack pointer in generating a store address by the subroutine read instruction, a branch destination address of the branch instruction, and a return stored by the subroutine read instruction The fifth selector means for switching addresses and the outputs of the first and second selector means are used as index keys, the outputs of the third and fourth selector means are used as registration keys, and the output of the fifth selector means is used as an index key. It has the branch history table means used as registration data.

[0008]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an information processing apparatus having a branch history table which is a first embodiment of the present invention. First
The information processing apparatus of this embodiment has a preceding control apparatus 10, a storage control apparatus 11, and a calculation execution apparatus 12. In the instruction read operation, the preceding control device 10 outputs the instruction prefetch address and the read access request to the storage control device 11 via the signal line 1. In response to this address and the access request, the storage control device 11 reads an instruction from the buffer storage or the main storage and sends it to the preceding control device 10 via the signal line 3. The preceding control device 10 decodes the instruction, generates an operand address if the instruction needs to read an operand from the memory, and outputs the operand address and the read access request to the storage control device 11 via the signal line 1. In response to the address and the access request, the storage control device 11 reads out the operand from the buffer storage or the main storage and sends it to the operation execution device 12 via the signal line 4. The preceding control device 10 sends the decode information obtained by decoding the instruction, the generated address and the like to the arithmetic execution device 12 via the signal line 5. The operation result of the operation instructed by the decode information is the operation execution device 12
Is sent to the preceding control device 10 and the storage control device 11 via the signal lines 6 and 7, and the contents of the general-purpose address calculation register and the storage device are updated.

FIG. 2 shows a part of the internal configuration of the advance control apparatus 10. The instruction sent from the storage controller via the signal line L201 is set in the instruction register 201. This instruction is decoded by the instruction decode 202. The instruction decoding information output here is set in the register 203 and also used for controlling the registers, selectors, etc. included in the preceding control device 10. The instruction decoding information set in the register 203 is sent to the arithmetic execution unit 12 via the signal line L20.
Sent via 8. As a result of decoding by the instruction decode 202, for an instruction that requires address generation, the page address and the intex address are read from the general-purpose register file 205, and these values are stored in the register 206 together with the displacement directly specified by the instruction.
Is set to 208. Furthermore, registers 206 to 20
The outputs of 8 are added by the address adder 209 and used as an operand address and a branch address. The output of the address adder 209 is sent to the arithmetic execution unit through the signal line L210 and also to the selectors 210 and 233. The selector 210 is a selector that selects an operand address or the like, and switches the outputs of the address adder 209 and the stack pointer 222 to change the signal line L206.
The address information is supplied to the storage control device 11 via the.

The selector 233 is a selector for selecting an instruction read address and the like, and includes an address adder 209, a register 244, and an instruction prefetch instruction counter adder 232.
Output is switched and address information is supplied to the storage control device 11 via the signal line L207. Address adder 2
The output of 09 is selected when the branch destination address is generated in the branch instruction processing. The output of the register 244 is selected when a hit signal is output as a result of indexing the branch history table. Instruction prefetch instruction counter adder 2
The output of 32 is selected at the time of instruction prefetch after the instruction counter indicated by the instruction prefetch instruction counter 231. The output of the selector 233 is sent to the selectors 230 and 240. The selector 230 is an input selector of the instruction prefetch instruction counter 231, and selects the initial value sent from the arithmetic execution unit 12 and the updated value of the instruction prefetch instruction counter 231 output from the selector 233. The selector 240 is a selector that selects the index address of the branch history table 242, and selects the output of the stack pointer 222 and the output of the selector 233. Stack pointer 222
Is selected at the time of processing of a subroutine return instruction, and otherwise, the instruction prefetch address information output from the selector 233 is selected.

As a result of indexing the branch history table 242, hit information and predicted address are read out,
It is set in the flag 243 and the register 244. Flag 2
The output of 43 is used as hit information of the branch history table and as a selection instruction of the selector 233. Further, the registration address and registration data to the branch history table 242 are sent from the arithmetic execution unit 12 via the signal lines L203 and L205. The stack pointer 222 is updated by the adder / subtractor 221 during processing of a subroutine read instruction or during processing of a subroutine return instruction. In the present embodiment, it is assumed that the operation of -4 is performed when the subroutine read instruction is processed, and the operation of +4 is performed when the subroutine return instruction is processed.
However, the same applies even when the addition and subtraction are reversed. Selector 22
Reference numeral 0 is an input selector of the stack pointer 222, and the initial value sent to the arithmetic execution unit 12 and the updated value of the stack pointer 222 output from the adder / subtractor 221 are selected.

FIG. 3 shows a part of the internal structure of the arithmetic execution unit 12. The signal line L208 from the preceding control device 10,
The instruction decode information and address information sent via L210 are buffered in the instruction decode information queue 301 and address queue 302 via signal lines L301, L303.
The instruction counter 306 indicates the address where the instruction being processed by the arithmetic execution unit 12 was stored. The adder 307 is used to add the instruction length sentence so that the instruction counter 306 indicates the next instruction. Selector 305
Is the input selector of the instruction counter and is the address queue 30
2, output of ALU via signal line L304, adder 30
7 output is selected. The output of the address queue 302 is
This is selected when a branch is taken in processing a branch instruction. The output of the ALU is selected when the initial value is set. In other cases, the adder 307 is selected. Stack pointer 30
9 performs the same process as the stack pointer 222, but the timing is different. Stack pointer 222
Is updated at the timing of address generation after decoding the subroutine read instruction and the subroutine return instruction, but the stack pointer 309 is updated at the timing of the processing completion of the subroutine read instruction and the subroutine return instruction in the arithmetic execution unit 12. Adder / subtractor 311
Is used to generate update data for the stack pointer 309. The selector 308 is switched to select the ALU when setting the initial value from the ALU. Register 3
22 to 324 are the values of the instruction counter 306 in which the processed instruction is stored at the timing when the processing is completed, and the stack pointer 309 before updating the branch destination instruction address output from the address queue 302 in the arithmetic execution unit 12. The value is set. The selectors 325 and 327 are used to select the registered address and data in the branch history table. The output is sent to the preceding control device 10 via the signal lines L306 and L307, and registered in the branch history table via the signal lines L203 and L205 of the preceding control device 10. Register 32 for processing branch instructions
2, 323 are selected and output to the signal lines L306 and L307. That is, the address in which the branch instruction was stored and the branch destination address of the branch instruction are registered in the branch history table. Regarding the subroutine read instruction processing, first, the registers 322 and 323 are selected and output to the signal lines L306 and L307. That is, the address where the subroutine read instruction is stored and the subroutine entry address of the subroutine read instruction are registered in the branch history table. Next, the register 324 and the adder 326 are selected and the signal line L
It is output to 306 and L307. That is, the value of the stack pointer at the time of reading out the subroutine and the sufficient return address are registered in the branch history table. The adder 326 is an adder for calculating a subroutine return address. In this embodiment, since the instruction length of the subroutine read instruction is assumed to be 4 bytes, it is a +4 adder. FIG. 11 shows the branch operation of the branch instruction. Branch to address B by the branch instruction (BRA) at address A. At this time, address A and address B are registered as a set in the branch history table. FIG. 12 shows the subroutine calling / returning operation. Subroutine read instruction at address A (JS
R) calls a subroutine having the E address as the entrance address. At the same time, the stack pointer is updated. At this time, the address A and the address E, and the address SP and the address B are registered in pairs in the container history table. In this embodiment, addresses A and E, SP addresses and B addresses are registered in this order, but this order may be registered first.

FIG. 4 shows a part of the internal structure of the branch history table 242. The key portion 402 of the branch history table is composed of three data fields. The data section 403 is composed of one data field. In a branch instruction entry generated by registration in branch instruction processing, three data fields of a valid bit (V), a branch instruction display bit (B), and a branch instruction address part are key parts, and a branch destination instruction address part is a data part. be registered. The address of the subroutine read instruction and the subroutine entry address are registered in the same manner as the branch instruction. On the other hand, in the branch instruction entry generated by registering the stack pointer and the subroutine return address,
Three data fields of a valid bit (V), a branch instruction display bit (B), and a stack pointer portion are registered in the key portion, and a return destination instruction address portion is registered in the data portion. At this time, the branch instruction display bit (B) has a value (Ba) indicating non-display.
rB) is set. Signal lines L203 and L20 are used for registration.
The data sent from the arithmetic execution unit via 5 is used. The selector 401 selects the signal line L203 during registration. At the time of indexing, since the index address is sent from the selector 240, the selector 401 selects the selector 240. The valid bit, the branch instruction display bit, the branch instruction address section, or the stack pointer section read from the branch history table key section 402 is input to the comparators 404 and 405 and the AND gate 406. The branch instruction address part or the tuck pointer part is compared with the output of the selector 401. Also, the branch instruction indication bit is compared with the index information. The index information is a value (BarB) indicating non-display when the selector 240 selects the output of the stack pointer, that is, when the branch history table is indexed when the subroutine return instruction is processed, and otherwise displays the branch instruction display. It becomes the indicated value (B). Comparator 40
Outputs 4 and 405 are respectively input to the AND gate 406, and are ANDed with the valid bit of the index entry and the index instruction of the branch history table, and the hit information is output. This hit information is set in the hit flag 243. Further, the data part of the same entry is stored in the register 244 and used for fetching the prediction destination instruction. The index instruction of the branch history table is a signal generated from the output of the instruction decoder when processing a predetermined instruction.

An information processing apparatus having a branch history table according to the second embodiment of the present invention has the same configuration as that of the first embodiment. As shown in FIG. It has a control device 10, a storage control device 11, and a calculation execution device 12.

FIG. 5 shows a part of the internal configuration of the advance control apparatus 10 according to the second embodiment. The instruction sent from the storage controller via the signal line L501 is the instruction register 5
It is set to 01. This instruction is decoded by the instruction decode 502. The instruction decoding information output here is set in the register 503 and is also used for controlling the registers, selectors, etc. included in the preceding control device 10.
The instruction decoding information set in the register 503 is sent to the arithmetic execution unit 12 via the signal line L508. As a result of decoding by the instruction decode 502, the page address and the intex address are read from the general-purpose register file 505 for the instruction that needs the address generation, and these values are set in the registers 506 to 508 together with the displacement directly specified by the instruction. To be done. further,
The outputs of the registers 506 to 508 are the address adder 509.
Are used as operand addresses and branch addresses. The output of the address adder 509 is the signal line L5.
It is sent to the arithmetic execution unit via 10 and is also sent to the selectors 510 and 533. The selector 510 is a selector that selects an operand address or the like, and switches the outputs of the address adder 509 and the stack pointers 522 and 523, and the storage controller 1 via the signal line L506.
1 to supply address information. The selector 533 is a selector that selects an instruction read address and the like, and switches the outputs of the address adder 509, the register 544, and the instruction prefetching instruction counter adder 532 to change the signal line L507.
The address information is supplied to the storage control device 11 via the.
The output of the address adder 509 is selected when the branch destination address is generated in processing the branch instruction. In addition, the register 54
The output of 4 is selected when the hit signal is output as a result of indexing the branch history table. The output of the instruction prefetch instruction counter adder 532 is selected at the time of instruction prefetch after the instruction counter indicated by the instruction prefetch instruction counter 531. The output of the selector 533 is the selectors 530 and 54.
Sent to 0. The selector 530 is an input selector of the instruction prefetch instruction counter 531 and selects the initial value sent from the arithmetic execution unit 12 and the updated value of the instruction prefetch instruction counter 531 which is the output of the selector 533. The selector 540 is a selector that selects an index address of the branch history table 542, and is a stack pointer 52.
The output of 2 and the output of the selector 533 are selected. The outputs of the stack pointers 522 and 523 are selected at the time of processing of a subroutine return instruction, and otherwise, the instruction prefetch address information output from the selector 533 is selected. As a result of indexing the branch history table 542, the hit information and the predicted address are read out and set in the flag 543 and the register 544. The output of the flag 543 is used as hit information in the branch history table and as a selection instruction of the selector 533. Further, the registration address and registration data to the branch history table 542 are sent from the arithmetic execution unit 12 via the signal lines L503 and L505. The stack pointer 522 is used by the adder / subtractor 52 when processing a subroutine read instruction or processing a subroutine return instruction.
Updated by 1. In this embodiment, -4 when processing a subroutine read instruction, + when processing a subroutine return instruction
It is assumed that operation 4 is performed. However, the same applies even when the addition and subtraction are reversed. The selector 520 is an input selector of the stack pointer 522, and selects the initial value sent to the arithmetic execution unit 12 and the updated value of the stack pointer 522 which is the output of the adder / subtractor 521.

In this embodiment, there are two stack pointers. Here, the stack pointer A522,
That is the stack pointer B523. In addition, a register 52 indicating which stack pointer is valid
4 is prepared. This register is converted at the time of mode transition such as user mode and supervisor mode. Therefore, both stack pointers cannot be used at the same time. (However, in general, there can be a plurality of stack pointers, and it is possible to allocate them for each process. It is also possible to specify the stack pointer for each instruction.) That is, the stack pointers 522 and 523 are One is valid and the other is invalid according to the valid stack pointer number of the register 524. Reference and update always target the valid stack pointer. The output of the register 524 is sent to the arithmetic execution unit via the signal line L509. Further, the selector 541 selects the output of the register 524 and the value “0” and uses it for the index of the branch history table 542. Selector 5
At 40, when the stack pointers 522 and 523 are selected, the output of the register 524 is selected. Branch history table 5
The valid execution stack pointer number is sent to 42 from the arithmetic execution unit 12 through the signal line L504 and used for registration.

FIG. 6 shows a part of the internal structure of the arithmetic execution unit 12. The signal line L508 from the preceding control device 10
The instruction decode information and address information sent via L510 are buffered in the instruction decode information queue 601 and the address queue 602 via signal lines L601 to L603. The instruction counter 606 indicates the address where the instruction being processed by the arithmetic execution unit 12 was stored. The adder 607 is used to add the instruction length sentence so that the instruction counter 606 indicates the next instruction. The selector 605 is
Address queue 602 with the input selector of the instruction counter
The output of the ALU via the signal line L604 and the output of the adder 607 are selected. The output of the address queue 602 is selected when a branch is taken in branch instruction processing. The output of the ALU is selected when the initial value is set. In other cases, the adder 607 is selected. Stack pointer 60
9, 610 performs the same processing as the stack pointers 522, 523, but the timing is different. The stack pointers 522 and 523 are updated at the timing of address generation after decoding the subroutine read instruction and the subroutine return instruction.
In the arithmetic execution unit 12, 610 is updated at the timing of completion of processing of a subroutine read instruction and a subroutine return instruction. The stack pointers 609 and 610 correspond to the stack pointers 522 and 523, and one is valid and the other is invalid according to the valid stack pointer number included in the register (not shown) in which the mode information of the information processing device is set. Become. The stack pointer that is valid for reference and update is the target. The register 524 is a copy of the effective stack pointer number included in the register in which the mode information is set. Such a valid stack pointer number is architecture dependent,
In some cases, a mode such as a supervisor mode or a user mode may be used instead. The adder / subtractor 611 is the stack pointer 60.
It is used to generate update data for 9,610. The selector 608 is switched to select the ALU when setting the initial value from the ALU. Registers 620, 622-6
24 is a valid stack pointer number output from the instruction decoding information queue 601 at the timing of completion of processing in the arithmetic execution unit 12, a value of the instruction counter 606 in which the processed instruction is stored, and output from the address queue 602. The branch destination instruction address and the value of the stack pointer 609 before updating are set. Selector 621,6
Reference numerals 25 and 627 are used for selecting a registration address and data in the branch history table. The output is the signal line L6
It is sent to the preceding control device 10 via 05 to L607 and registered in the branch history table via the signal lines L503 to L505 of the preceding control device 10. At the time of branch instruction processing, '0', registers 622 and 623 are selected and output to the signal lines L605 to L607. That is, the address in which the branch instruction was stored and the branch destination address of the branch instruction are registered in the branch history table. Regarding subroutine read instruction processing, first,
'0', registers 622 and 623 are selected and signal line L6
05 to L607 are output. That is, the address where the subroutine read instruction is stored and the subroutine entry address of the subroutine read instruction are registered in the branch history table. When processing a branch instruction, the registers 322 and 323 are selected and the signal line L306,
It is output to L307. That is, the address in which the branch instruction was stored and the branch destination address of the branch instruction are registered in the branch history table. Regarding the subroutine read instruction processing, first, the register 32
2, 323 are selected and output to the signal lines L306 and L307. That is, the address where the subroutine read instruction is stored and the subroutine entry address of the subroutine read instruction are registered in the branch history table. Next, the registers 620 and 624 and the adder 326.
Is selected and output to the signal lines L605 to 6077. That is, the value of the stack pointer at the time of reading the subroutine and the subroutine return address are registered in the branch history table. The adder 326 is an adder for calculating a subroutine return address. In this embodiment, since the instruction length of the subroutine read instruction is assumed to be 4 bytes, it is a +4 adder. FIG. 11 shows the branch operation of the branch instruction. By the branch instruction (BRA) at address A,
Branch to address B At this time, in the branch history table,
Address A and address B are registered as a pair. FIG. 12 shows the subroutine calling / returning operation. A subroutine read instruction (JSR) at address A calls a subroutine having address E as an entry address. At the same time, the stack pointer is updated. At this time, in the container history table, address A and E
Address, SP address and B address are registered in pairs. In this embodiment, addresses A and E, SP addresses and B addresses are registered in this order, but this order may be registered first.

FIG. 7 shows a part of the internal structure of the branch history table 542. The key portion 702 of the branch history table is composed of three data fields. The data section 703 is composed of one data field. In the branch instruction entry generated by the registration in the branch instruction processing, three data fields of a valid bit (V), a branch instruction display bit (B), '0', and a branch instruction address section are provided in the key section as the branch target instruction address section. Is registered in the data section. The address of the subroutine read instruction and the subroutine entry address are registered in the same manner as the branch instruction. On the other hand, in the branch instruction entry generated by registering the stack pointer and the subroutine return address, the four data fields of the valid bit (V), the branch instruction display bit (B), the valid tact pointer number (ST), and the stack pointer part Is registered in the key part, and the return destination instruction address part is registered in the data part. At this time, the branch instruction display bit (B) is set to a value (Bar) indicating non-display.
B) is set. Signal lines L503 to L505 are used for registration.
Data sent from the arithmetic execution unit via the. The selector 701 is for registering signal lines L503 and L504.
Select. When indexing, the index address is the selector 54
Since it is sent from 0, the selector 701 is
Select. The valid bit read from the branch history table key unit 702, the branch instruction display bit, “0”, or the valid stack pointer number, the branch instruction address unit, or the stack pointer unit is input to the comparators 704 and 705 and the AND gate 706. To do. The branch instruction address part or the tuck pointer part is compared with the output of the selector 701. Further, the branch instruction display bit and "0" or the effective stack pointer number is compared with the index information. The index information is output by the selector 541 and the selector 54.
When 0 selects the output of the stack pointer, that is, when the branch history table is indexed when processing the subroutine return instruction, the value indicates non-display (BarB), and otherwise the value indicates the branch instruction display (B). Becomes The outputs of the comparators 704 and 705 are input to the AND gate 706, and are ANDed with the valid bit of the index entry and the index instruction of the branch history table, and the hit information is output. This hit information is set in the hit flag 543. The data part of the same entry is stored in the register 544 and is used for fetching the prediction destination instruction. The index instruction of the branch history table is a signal generated from the output of the instruction decoder when processing a predetermined instruction.

An information processing apparatus having a branch history table according to the third embodiment of the present invention has the same configuration as that of the first embodiment, and the information processing apparatus according to the third embodiment is as shown in FIG. It has a preceding control device 10, a storage control device 11, and a calculation execution device 12.

FIG. 8 shows a part of the internal construction of the advance control apparatus 10 in the third embodiment. The instruction sent from the storage controller via the signal line L801 is the instruction register 8
It is set to 01. This instruction is decoded by the instruction decode 802. The instruction decoding information output here is set in the register 803 and is also used for controlling the registers, selectors, etc. included in the preceding control device 10.
The instruction decoding information set in the register 803 is sent to the arithmetic execution unit 12 via the signal line L808. As a result of decoding by the instruction decode 802, for an instruction that requires address generation, the page address and the intex address are read from the general-purpose register file 805, and these values are set in the registers 806 to 808 together with the displacement directly specified by the instruction. To be done. further,
The outputs of the registers 806 to 808 are address adders 809.
Are used as operand addresses and branch addresses. The output of the address adder 809 is the signal line L8.
It is sent to the arithmetic execution unit via 10 and is also sent to the selectors 810 and 833. The selector 833 is a selector that selects an instruction read address and the like, and switches the outputs of the address adder 809, the register 844, and the instruction prefetching instruction counter adder 832 to switch the signal line L80.
The address information is supplied to the storage controller 11 via 7. The output of the address adder 809 is selected when a branch destination address is generated in processing a branch instruction. The output of the register 844 is the result of indexing the branch history table,
Selected when the hit signal is output. The output of the instruction prefetch instruction counter adder 832 is selected at the time of instruction prefetch after the instruction counter indicated by the instruction prefetch instruction counter 831. The output of the selector 833 is the selector 830,
Sent to 840. The selector 830 is an input selector of the instruction prefetching instruction counter 831, and the arithmetic execution unit 1
2 and the updated value of the instruction prefetching instruction counter 831 which is the output of the selector 833 are selected.
The selector 840 is a selector that selects the index address of the branch history table 842, and selects the output of the stack pointer 822 and the output of the selector 833. The output of the stack pointer 822 is selected at the time of processing of a subroutine return instruction, and otherwise, the instruction prefetch address information output from the selector 833 is selected. As a result of indexing the branch history table 842, the hit information and the predicted address are read out and set in the flag 843 and the register 844. The output of the flag 843 is used as hit information in the branch history table and as a selection instruction of the selector 833. Further, the branch history table 8 is sent from the arithmetic execution unit 12 via the signal lines L803 to L805.
The registration address and registration data for 42 are sent. In this embodiment, the index register is used instead of the stack pointer in the subroutine read instruction and the return instruction. The register number of the index register read from the general-purpose register file 805 for address generation (it is possible to use the base register but it is not general) is set in the register 811 and the signal line L8.
It is sent to the arithmetic execution unit 12 via 09. Also, in the selector 841, when the address adder 809 is selected in the selector 840, the output of the register 811 is selected and used as an index of the branch history table 842.

FIG. 9 shows a part of the internal structure of the arithmetic execution unit 12. Signal line L808 from the preceding control device 10
The instruction decoding information, index register number, and address information sent via L810 are signal lines L391 to L90.
3 is buffered in the instruction decoding information queue 901 and the address queue 902. The instruction counter 906 indicates the address where the instruction being processed by the arithmetic execution unit 12 was stored. The adder 907 is used to add the instruction long sentence so that the instruction counter 906 indicates the next instruction. The selector 905 is an input selector of the instruction counter, and is A through the address queue 902 and the signal line L904.
The output of the LU and the output of the adder 907 are selected. The registers 920, 922, 923 are
Instruction decoding information queue 901 at the timing of completion of processing
The index register number output by the output, the value of the instruction counter 906 in which the processed instruction is stored, and the branch destination instruction address output from the address queue 902 are set. The selectors 921, 925, 927 are used for selecting the registered address and data in the branch history table. The output is sent to the preceding control device 10 via the signal lines L905 to L907, and registered in the branch history table via the signal lines L803 to L805 of the preceding control device 10. When processing a branch instruction, the value "0", the registers 922 and 923 are selected and the signal lines L905 to L9 are selected.
It is output to 07. That is, the address in which the branch instruction was stored and the branch destination address of the branch instruction are registered in the branch history table. Regarding the subroutine read instruction processing, first, the register 920,
923 and the adder 926 are selected and the signal lines L905 to L9 are selected.
It is output to 07. That is, the index register number, the stack pointer value when the subroutine is called, and the subroutine return address are registered in the branch history table. The adder 326 is an adder for calculating a subroutine return address. In the present embodiment, the instruction string for reading the subroutine is 4 bytes long × instruction, so that it is a +8 adder. This process is shown in Figure 1.
Registration is performed at the timing when the instruction counter store instruction (STC8) processing shown in 3 is completed. Next, '0'
Value, register 922, 923 is selected and signal line L905
To L907. That is, the address where the subroutine read instruction is stored and the subroutine entry address of the subroutine read instruction are registered in the branch history table. This processing is registered at the timing when the processing of the branch instruction (BRA) shown in FIG. 13 is completed.

FIG. 11 shows the branch operation of the branch instruction. A branch instruction (BRA) at address A branches to address B.
At this time, address A and address B are registered as a pair in the branch history table. FIG. 13 shows a subroutine calling / returning operation. Instruction counter store instruction at address A (ST
C8) stores the value of the instruction counter (A) +8 in the general register R2 as an index register. That is, the return address is stored using the R2 register as the stack pointer. The next branch instruction (BRA) branches to the entry address (E) of the subroutine. At the entrance of the subroutine, first, the register R2 used as the stack pointer is updated (SB). At the exit of the subroutine, conversely, after updating (AD) the register R2, the subroutine return instruction (RET) returns to the address B. This return instruction (RET) returns to the address B. This return instruction performs an indirect branch using the register R2 as an index register. That is, the branch is performed using the contents of the address indicated by the register R2 as the return address.

In the present embodiment, the subroutine read is performed by an instruction counter store instruction (STC8) and a branch instruction (B
RA) and a register subtraction instruction (SB). In addition, the register addition instruction (A
D) and a subroutine return instruction (RET). This is because the architecture does not have a dedicated stack pointer, so it is necessary to specify a general-purpose register to be used as a stack pointer.

FIG. 10 shows a part of the internal structure of the branch history table 842. The keystroke 1002 of the branch history table is composed of four data fields. The data section 1003 is composed of one data field. In a branch instruction entry generated by registration in branch instruction processing, four data fields of a valid bit (V), a branch instruction display bit (B), 0, and a branch instruction address part are key parts, and a branch destination instruction address part is a data part. be registered. The address of the subroutine read instruction and the subroutine entry address are registered in the same manner as the branch instruction. On the other hand, in the branch instruction entry generated by registering the save address part and the subroutine return address, the valid bit (V), the branch instruction display bit (B),
Four data fields of an index register number and a stack pointer part are registered in the key part, and a return destination instruction address part is registered in the data part. At this time, the branch instruction display bit (B) is set to a value (BarB) indicating non-display. The data sent from the arithmetic execution unit via the signal lines L803 to L805 is used for registration. Selector 10
01 selects the signal lines L803 to L804 at the time of registration. At the time of indexing, since the index address is sent to the selector 840, the selector 1001 selects the selector 840.
The valid bit read from the branch history table key unit 1002, the branch instruction display bit, “0” or the index register number, the branch instruction address unit, the stack pointer unit, or the stack pointer unit is the selector 1
It is compared with the output of 001. Further, the branch instruction display bit and "0" or the effective stack pointer number is compared with the index information. When the output of the selector 841 and the output of the stack pointer are selected by the selector 840, that is, when the branch history table is indexed during the processing of the subroutine return instruction, the index information is a value (BarB) indicating non-display, and otherwise. Is information that is a value (B) indicating a branch instruction display. Comparator 1004,10
The output of 05 is input to the AND gate 1006, and is further ANDed with the valid bit of the index entry and the index instruction of the branch history table, and the hit information is output. This hit information is set in the hit flag 843. The data part of the same entry is stored in the register 844 and is used for fetching the prediction destination instruction. The branch history data index instruction is a signal generated from the output of the instruction decoder during processing of a predetermined instruction.

[0025]

As described above, in the first embodiment of the present invention, in the information processing apparatus having the branch history table, the subroutine read instruction using the stack pointer of the stack pointer as a mechanism for supporting the use of the subroutine and In the above information processing apparatus having an instruction set including a subroutine return instruction, the value of the stack pointer is registered as a key value and the return address is registered as a data value in the branch history table when the subroutine read instruction is processed, and the stack pointer Index the branch history table with the value as the key value.

The second embodiment includes, as a mechanism for supporting the use of the subroutine, a plurality of stack pointers, mode information indicating the numbers of the stack pointers currently effective, and a subroutine read instruction and a subroutine return instruction using the stack pointers. In the above information processing device having an instruction set, during processing of a subroutine call instruction, the effective stack pointer number and the value of the stack pointer are registered in the branch hit table as a key value and the fuky address as a data value, and when a subroutine return instruction is processed, The branch history table is indexed using the effective stack pointer number and the value of the stack pointer as the key value.

The third embodiment does not have a dedicated stack pointer as a mechanism for supporting the use of a subroutine, and in an information processing device including a subroutine read instruction and a subroutine return instruction using a general-purpose register, the stack is used when processing a subroutine read instruction. Branch history with the register number of the general-purpose register used instead of the pointer, the subroutine return address, and the store address when saving (corresponding to the address generated by the above subroutine read instruction) as the key value, and the subroutine return address as the data value Register in the table, and index the register number of the general-purpose register used as a substitute for the stack pointer used to generate the address when reading the subroutine return address during the subroutine return instruction processing and the generated address as the key value. .

According to the first to third embodiments, the branch history table can be used for the return processing from the subroutine, and the branch can be speeded up in the return processing. Further, since the existing branch history table is used, there is an effect that it can be efficiently realized with a small amount of metal.

Further, as shown in the first to third embodiments, various types of architectures can be supported. The first embodiment corresponds to an architecture with one stack pointer. The second embodiment corresponds to an architecture with multiple stack pointers. The third embodiment corresponds to an architecture without a stack pointer. As described above, the branch history table can be effectively used for the subroutine return processing for various types of architectures.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an internal structure of the advance control device 10 in the first embodiment.

FIG. 3 is a diagram showing an internal structure of a calculation execution device 12.

FIG. 4 is a diagram showing an internal structure of a branch history table 242.

FIG. 5 is a diagram showing an internal structure of a preceding control device 10 in a second embodiment.

FIG. 6 is a diagram showing an internal structure of a calculation execution device 12.

FIG. 7 is a diagram showing an internal structure of a branch history table 542.

FIG. 8 is a diagram showing an internal structure of a preceding control device 10 in a third embodiment.

FIG. 9 is a diagram showing an internal structure of the arithmetic execution unit 12.

FIG. 10 is a diagram showing an internal structure of a branch history table 842.

FIG. 11 is a diagram showing a branch operation of a branch instruction.

FIG. 12 is a diagram showing a subroutine call / return operation.

FIG. 13 is a diagram showing a subroutine call / return operation.

[Explanation of symbols]

10 Advance Control Device 11 Storage Control Device 12 Operation Execution Device 201, 501, 801 Instruction Register 202, 502, 802 Instruction Decoder 203, 206, 207, 208, 244, 322, 3
23, 324, 503, 506, 507, 508, 52
4,544,620,622,623,624,80
3,806,807,808,811,844,92
0,922,923 register 209,509,809 address adder 222,309,522,523,609,610
Stack pointer 221, 521, 611 Adder / subtractor 237, 531, 831 Instruction prefetch instruction counter 231, 307, 326, 532, 607, 626, 8
32,907,926 adder 242,402,403,542,702,703,8
42,1002,1003 Branch history table 243,543,843 Flag 301,302,601,602,901,902
Queue 306, 606, 906 Instruction counter 404, 405, 704, 705, 1004, 1005
Comparators 406, 706, 1006 AND gates 210, 220, 230, 233, 240, 305, 3
25, 308, 327, 401, 510, 520, 53
0,535,540,605,625,608,62
7,701,541,621,830,833,84
0,921,926,927,905,841,100
1 selector

Claims (3)

[Claims] 1. As a mechanism for supporting the use of a subroutine, a stack pointer and an instruction set including a subroutine call instruction and a subroutine return instruction using the stack pointer are provided, and the address of the branch instruction and the branch destination address of the branch instruction. In an information processing apparatus having a branch history table storing pairs of instructions, instruction decoding means for detecting the subroutine call instruction and subroutine return instruction, an instruction fetch address in response to the output of the instruction decoding means, and the stack pointer. When the instruction being executed is a predetermined branch instruction in executing the instruction and the first selector means for switching the output of the branch instruction, the address in which the branch instruction is stored, and the instruction being executed is the subroutine calling instruction Is the subroutine call instruction Second selector means for selecting the output of the updated stack pointer, third selector means for switching the branch destination address of the branch instruction and the return address from the subroutine call by the subroutine call instruction, and the first selector A branch history table characterized in that the output of the means is used as an index key, the output of the second sector means is used as a registration key, and the output of the third selector means is used as registration data. Information processing equipment. 2. An instruction set including a plurality of stack pointers, mode information indicating a currently valid stack pointer number, a subroutine call instruction and a sub routine return instruction using the stack pointers, as a mechanism for supporting the use of the subroutine. And a branch history table for storing a branch instruction address and a branch destination address of the branch instruction as a pair. First selector means for switching the instruction fetch address and the output of the stack pointer in response to the output of the means, second selector means for selecting the stack pointer number included in the mode information, and Branch with predetermined instructions When the instruction is an instruction, the address in which the branch instruction is stored, and when the instruction being executed is the subroutine read instruction, third selector means for selecting the output of the stack pointer updated by the subroutine read instruction, Fourth selector means for selecting the stack pointer number of the stack pointer selected by the third selector means, and fifth selector for switching the branch destination address of the branch instruction and the return address from the subroutine read by the subroutine call instruction. Means and the outputs of the first and second selector means as index keys, the outputs of the third and fourth selector means as registration keys, and the output of the fifth selector means as registration data. An information processing apparatus having a branch history table, characterized by comprising table means. 3. As a mechanism for supporting the use of a subroutine, there is no dedicated stack pointer, a subroutine read instruction using a general-purpose register and a subroutine return instruction are provided, and the address of the branch instruction and the branch destination address of the branch instruction are paired. In an information processing apparatus having a branch history table stored in memory, an instruction decoding means for detecting the subroutine read instruction and the subroutine return instruction, and an instruction fetch address and the subroutine return instruction in response to the output of the instruction decoding means. The first selector means for switching the address generated in step 1, the second sector means for selecting the register number of the general-purpose register used in place of the stack pointer in generating the address, and the instruction being executed in executing the instruction. If there is a predetermined branch instruction, the corresponding Address where the branch instruction was stored, and when the instruction being executed is the subroutine read instruction, third selector means for selecting a return address stored by the subroutine read instruction, and store address generation by the subroutine read instruction At this time, fourth selector means for selecting the register number of the general-purpose register used instead of the stack pointer, and fifth selector means for switching the branch destination address of the branch instruction and the return address stored by the subroutine read instruction. The branch history table means using the outputs of the first and second selector means as index keys, the outputs of the third and fourth selector means as registration keys, and the output of the fifth selector means as registration data An information processing apparatus having a branch history table.