JPH0659740B2 - Thermal transfer recording device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thermal transfer recording apparatus capable of obtaining a good intermediate recorded image.

2. Description of the Related Art In recent years, full-color thermal transfer recording devices have been developed,
High-accuracy gradation recording is required to obtain a good halftone recorded image.

Generally, it is difficult for the conventional thermal transfer recording apparatus to control the recording density per dot corresponding to one heating element, and the gradation recording has two gradations of printing or non-printing.

Hereinafter, a conventional thermal transfer recording apparatus will be described with reference to the drawings.

In FIG. 10, reference numeral 1 denotes a thermal head unit, and the thermal head unit 1 is arranged in a line on an insulating substrate and electrically divided into N units of M units each. A heat-generating element 2 composed of a plurality of heat-generating resistors, N driver circuits 3 provided for each unit of the heat-generating element 2, and N driver circuits 3 provided corresponding to the respective driver circuits 3. Latch circuit 4 and this latch circuit 4
N shift registers 5 provided corresponding to each
It is composed by.

In this thermal head unit 1, one electrode of the heating element 2 is commonly connected to the power supply for printing, and the other electrode is connected to the output terminal of the driver circuit 3. The input terminal of the driver circuit 3 is connected to the output terminal of the latch circuit 4, and the input terminal of the latch circuit 4 is connected to the output terminal of the shift register 5.

As a result, the print data signals input to the respective shift registers 5 are sent as parallel signals to the corresponding latch circuits 4, and the driver circuit 3 is driven by the print data signals sent from the latch circuits 4 for printing. The heat generating element 2 corresponding to the data signal is energized, and heat sensitive recording is performed. It should be noted that each of the driver circuits 3 is configured so that an enable signal for controlling the operation of the driver circuit 3 is independently applied in parallel.

Problems to be Solved by the Invention However, in recent years, by making the width and central portion of the heating element of the heating element narrower and widening at both ends, the resistance value of the heating element becomes larger at the central portion and smaller at both ends. By devising a new element, and thereby controlling the application time of the voltage applied to the heating element, it is possible to easily control the heating area corresponding to one heating element, that is, the recording density per dot. (Japanese Patent Laid-Open No. 60-58877)
issue).

However, when gradation recording is performed using the heating element described above, multi-gradation recording becomes possible, and accordingly, gradation is specified from the 1-bit information indicating whether print data is conventionally printed or not. Therefore, the conventional thermal transfer recording apparatus cannot process the multi-bit information at a high speed.

The present invention is to solve the above conventional problems, based on the print data consisting of a plurality of bits of information,
An object of the present invention is to provide a thermal transfer recording apparatus capable of controlling gradation recording with high accuracy and at high speed.

Means for Solving the Problems In order to achieve this object, the thermal transfer recording apparatus of the present invention employs 1 block in which n heating elements are arranged in n units (n is a natural number except 1). The arranged head portion, l × n driver circuits provided for each of the m heating elements, and n provided corresponding to each of the driver circuits.
Xl latch circuits, nxl m-stage shift registers provided corresponding to each of the latch circuits, and n sequentially provided in common for each shift register of each block. Of the comparator, a reference signal generating circuit commonly provided at one terminal of the comparator, n selectors provided at the other terminal of the comparator, and m × n data consisting of a plurality of bits. and n buffers sequentially sent by m, each selector having a configuration in which when m data is sent to each of the n buffers, each selector sequentially takes out the data stored in each buffer. is doing.

With this configuration, m × n print data consisting of a plurality of bits can be sequentially taken out from each buffer at a time by n buffers by providing n buffers, and a comparator is provided for each buffer. Thus, m print data can be sequentially processed for each buffer, and a large amount of print data can be processed at high speed.

Examples Examples of the present invention will be described below with reference to the drawings.

FIG. 1A is a block diagram of the heat-sensitive transfer recording apparatus of this embodiment, and FIG. 1B is a configuration diagram of one unit of the heating element.

In the figure, 10 is a thermal head part, which is divided into 4 blocks, and heating elements 11 are arranged in parallel in units of 8 blocks of 32 blocks.
In addition, eight driver circuits 3 (D1 to D8) 12 are provided for each of the four blocks with 32 heating elements 11 as one unit, and further eight latch circuits corresponding to the driver circuits 12 are provided. (L1 to L8) 13 and eight shift registers (SR1 to SR8) 14 are provided corresponding to each of the driver circuits 12.

In the thermal head unit 10, one of the heating elements 11 is commonly connected to the power supply unit 15 for printing, and the other is connected to the output terminal of the driver circuit 12. The input terminal of the driver circuit 12 is connected to the output terminal of the latch circuit 13, and the input terminal of the latch circuit 13 is connected to the output terminal of the shift register 14.

Here, each of the driver circuits 12 has an enable signal 1 for controlling the operation of the driver circuit 12 for each block.
6 are connected to each driver circuit 12 in parallel so as to be applied in parallel to each driver circuit 12, and a strobe signal 17 for controlling the operation of the latch circuit is common to each of the latch circuits 13. Are connected to be applied to.

Next, reference numeral 18 is a pulse control unit, and the eight signals (SIN1 to SIN8) created here are individually and independently applied to the shift register and are applied in parallel between the blocks. It is connected. Reference numeral 19 is a comparator, which compares the input from the counter 20 with the input from the first selector 21 and outputs the result. Further, 22 is a buffer in which a logic is composed of a plurality of flip-flops, and the information composed of a plurality of bits selected by the second selector 23 is sequentially input to each of the buffers 22 for each information unit. Then, of the information input thereafter for each information unit, the first selector 21
Thus, the information for one dot stored in each buffer 22 is sequentially taken out and output to the comparator 19.

Reference numeral 24 in the drawing is head correction data, and data for correcting the variation in the resistance value of the heating resistor of each heating element 11 and controlling the rising temperature of each heating element 11 is input. Further, reference numeral 25 is the adjacent and previous history correction print data, and the print data corrected in consideration of the influence degree in the vicinity of the heating element 11 to be printed is input.

Further, the counter 20 operates as a down counter when processing the head correction data 24, and operates as a special counter as shown in FIG. 6 when processing the adjacent and previous correction print data 25.

Hereinafter, the operation of the present embodiment will be described using specific numerical values with reference to the drawings.

FIG. 2B shows head correction data for one line (1024 × 4 bits), which is divided into four blocks each having 256 blocks, and one block has 8 blocks each having 32 blocks.
It is divided into individual units. FIG. 4 (a) shows adjacent and previous history correction print data for one line (1024 × 6 bits), which is divided into four blocks by 256, and one block is further divided by 32 in 8 units. Has been.

First, the head selector data 24 is set by the second selector 23.
Is read. At this time, one block (256 × 4 bits) of the data of one line (1024 × 4 bits) is read into the buffer 22 one unit (32 × 4 bits), as shown in FIG. ), The head correction data 24 is stored in each of 32 buffers in the eight buffers (B1 to B8) 22. In the figure, the leftmost number indicates the address No., and the number in the block indicates 4-bit head correction data.

Next, the 32 head correction data stored in each buffer 22 are stored in each first selector 21 (SL1 to SL1).
8) one data at a time is sequentially taken out and output to the corresponding comparators (CP1 to CP8) 19. Then, in each comparator 19, one data extracted by the first selector 21 and the input from the counter are compared and output as a head correction signal.

At this time, since the counter 20 processes the head correction data 24, it operates as a down counter (15 → 0). First, in each of the eight comparators 19, each head correction data is compared with the output “15” of the down counter. If it is equal to or more than “15”, “1” is output to each corresponding shift register, and if less than “15”, “0” is output to each corresponding shift register.
This is performed in parallel for 32 head correction data in each comparator 19, and the output of the down counter is decremented by 1 each time the comparison is completed. As a result, the head correction data as shown in FIG. 2B is processed and the head correction signal as shown in FIG. 3A is output to each shift register 14.

The head correction signal input to each shift register 14 is
Each time the output of the down counter is rolled down one by one, it is sent to each corresponding latch circuit 13 and further from each corresponding driver circuit 12. At this time,
By applying the enable signal independently connected in parallel to each driver circuit 12 for each block to only the corresponding block of the head correction data, each heating element 11 of the block generates heat.

As a result, when the count of the down counter ends to “0”, each driver circuit is eventually shown in FIG.
A pulse waveform having a pulse width corresponding to the content of the head correction data as shown in (4) is input, and the energization start time and the energization time to each heating element 11 are controlled by this pulse width, and the rising temperature is always maintained. Each heating element 11
You can get it every time.

Next, when one head correction data block (256 × 4 bits) is completed, the adjacent one block (256 × 6 bits) of the previous history correction print data 25 becomes the second block.
One unit (32 × 6 bits) by the selector 23 of
Each of them is read into the buffer 22 and is stored in each of the eight buffers (B1 to B8) 22 as shown in FIG. 4B. In the figure, the leftmost number indicates the address No., and the number in the block indicates 6-bit corrected print data. Then, the 32 pieces of correction print data stored in each buffer 22 are sequentially taken out one by one by each first selector and output to each corresponding comparator 19. Then, in each comparator 19, one data taken out by the first selector is compared with the input from the counter, and is output as a print correction signal. Since the counter 20 is processing the adjacent and previous history correction print data 25, it operates as a special counter as shown in FIG.

As shown in the figure, the counter 20 is composed of a ternary up counter 26 starting from 2 and a 32 ary up counter 27 starting from 0, and each time the strobe signal 28 is applied, the count of each counter is incremented. To do.
The ternary counter 26 has only three outputs as shown in Table 1, When the upper bit Q ₁ (OUT2) becomes “1”, the print correction signal (OUTC) is forcibly turned off, and when the lower bit Q ₀ (OUT1) becomes “1”, the 32-bit counter 27 is set. It is configured to hold. Further, when the start signal 29 is applied, Q ₀ becomes “0” and Q ₁ becomes “1”.

With this configuration, for example, one data (0
01000) is taken out, a time chart as shown in FIG. 7 is obtained.

That is, when the start signal 29 is first applied to the ternary counter 26, Q _{1 of the} ternary counter becomes “1”, and therefore OUT 2 outputs the compulsory OFF signal, and thereafter, Q _{1 of the} ternary counter remains “ ₁ ”. A forced OFF signal is output from OUT2 each time it becomes 1 ″. Next, Q _{0 of the} ternary counter
OUT1 is set to H in the ternary counter 27 every time when becomes "1".
The OLD signal is output and the count of the 32-ary counter 27 is held by one. Then, the output (O
The above operation is repeated until UT A) becomes “8” or more. When it becomes “8” or more, A ≧ B, so that the output from the comparator becomes “0”.

As a result, the count of the 32-bit counter 27 is "31".
After that, as a result, each driver circuit is input with a pulse waveform of the number of pulses corresponding to the content of the correction print data as shown in FIG. 5 (b), and the intermittent pulse keeps each heating element 11 constant. Can be maintained at the exothermic temperature of
Further, since the energization time is controlled by the number of pulses, it is possible to control the heat generation amount of each heating element 11.

By performing the comparison process in each of the comparators 19 alternately for the four head correction data blocks and the four adjacent and previous history correction print data blocks, each driver circuit results in FIG. A pulse waveform as shown in FIG. 8B is input, so that each heating element can obtain the temperature characteristic as shown in FIG. In the figure, T ₁ is a temperature at which the ink melts (ink melting point), T ₂ is a temperature at which the head part and the ink sheet do not separate from each other by sticking (stick level), and T ₃ is an optimum temperature at which the ink is transferred to the recording paper. Temperature (optimum transfer temperature)
Therefore, a constant voltage whose heat generation temperature exceeds the stick level is commonly applied to each element.

In FIG. 8, the rising section A is a section in which the heating element 11 is raised to the optimum transfer temperature T ₃ , and since the voltage higher than the stick level is commonly applied to the heating element 11, head correction for rising is performed. When the pulse is applied, the heat generation temperature rises to the optimum transfer temperature T _{2 in} a short time.

Here, since the resistance value of each element is slightly different, as shown in FIG. 8, when the resistance value of the element is large, the heat generation of the element is slow, so the generation timing of the head correction pulse should be accelerated. By increasing the pulse width,
As shown by the curve C, the energization start time of the applied voltage is shortened and the energization time is lengthened. On the contrary, when the resistance value of the element is small, the element is generated quickly. Therefore, by delaying the generation timing of the head correction pulse and narrowing the pulse width of the head correction pulse, the energization of the applied voltage starts as indicated by the curve C ′. The time is reduced and the energization time is shortened. By this head correction pulse, the rising temperature of the element is always constant, and it is easy to always obtain a stable amount of heat.

Next, in FIG. 8, the printing section B is a section in which the heating element 11 is kept constant at the optimum transfer temperature T ₃ and the time is controlled. Since the voltage higher than the stick level voltage is applied to the heating element 11, the stick level will be exceeded if the application is continued. Therefore, in order to prevent this, apply intermittent adjacent and previous correction print pulses to each driver circuit. Thus, the applied voltage is forcibly turned on and off to keep the optimum transfer temperature T ₂ constant.

Here, if an element whose heating area changes in proportion to the time for applying the optimum transfer temperature T ₃ to the heating element 11 is used, gradation recording can be controlled by adjusting the length of the printing section B. . That is, as shown in FIG. 9, the number of intermittent correction print pulses is (a), (b),
When it is reduced in order from (c), the time for which the optimum transfer temperature T ₃ can be maintained becomes short accordingly, and the heat generation area per dot becomes as small as (d), (e), (f). is there.

Therefore, by controlling the number of adjacent and previous history correction print pulses, the gradation of each dot can be controlled with high accuracy and in multiple gradations.

EFFECTS OF THE INVENTION As is clear from the above description, according to the thermal transfer recording apparatus of the present invention, by providing n buffers for m × n print data consisting of a plurality of bits, n buffers are transferred from each buffer. It is possible to take out sequentially at the same time, and by providing a comparator for each buffer, m print data can be sequentially processed for each buffer. ,
Moreover, the gradation can be controlled at high speed.

[Brief description of drawings]

FIG. 1 (a) is a block diagram of a heat-sensitive transfer recording apparatus according to an embodiment of the present invention, FIG. 1 (b) is a block diagram of a heating element unit in the embodiment, and FIG. 2 (a) is the same embodiment. FIG. 2B is a configuration diagram showing the configuration of head correction data for one line in the example, and FIG. 2B is a schematic diagram showing the contents of 4-bit head correction data stored in each buffer in the same embodiment. 3 (a) is a schematic diagram showing the content of the head correction signal output from the comparator in the embodiment, and FIG. 3 (b) is an input waveform diagram when the head correction signal is input to each driver circuit. FIG. 4 (a) is a configuration diagram showing the configuration of correction print data for one line in the same embodiment, and FIG. 4 (b) is a 6-bit correction print stored in each buffer in the same embodiment. FIG. 5 (a) is a schematic diagram showing the contents of the data in the same embodiment. FIG. 5 (b) is a schematic diagram showing the contents of the correction print signal output from the comparator, FIG. 5 (b) is an input waveform diagram when the same correction print signal is output to each driver circuit, and FIG. Of the counter of FIG. 7, FIG. 7 is a time chart showing the operation of the counter, FIGS. 8 (a) and 8 (b) are temperature characteristic diagrams of the heating element of the embodiment, and the input waveform of the corresponding driver circuit. 9A to 9C are input waveform diagrams input to the driver circuit of the embodiment, and FIGS. 9D to 9F are FIGS. 9A to 9.
FIG. 10 is a diagram showing a heating state of each heating element when the input waveform of (c) is input to each driver circuit, and FIG. 10 is a block diagram of a conventional thermal transfer recording apparatus. 10 ... Head part, 11 ... Heating element, 12 ... Driver circuit (D1 to D8), 13 ... Latch circuit (L1 to L)
8), 14 ... Shift registers (SR1 to SR8), 1
9: Comparator (CP1 to CP8), 20: First
Selectors (SL1 to SL8), 21 ... Buffer (B
1-B8).

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Taichi Ito 1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Zenichi Tsuru, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (1)

[Claims] 1. A head section in which n blocks each of which includes m heat generating elements (n is a natural number except 1) are arranged, and xn heat generating elements are provided for each of the m heat generating elements. Driver circuit, n × latch circuits provided corresponding to each of the driver circuits, a shift register including n × m stages provided corresponding to each of the latch circuits, N comparators sequentially provided in common for each shift register of each block, a reference signal generation circuit commonly provided at one terminal of the comparator, and n provided at the other terminal of the comparator. N selectors and m × n pieces of data composed of a plurality of bits are sequentially sent m by n
Buffers, and m for each of the n buffers.
The thermal transfer recording apparatus, wherein each of the selectors sequentially takes out the data stored in each of the buffers when the individual data is sent.