JPH065898B2 - Multi-scan type television receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention receives an image of a video signal having a different horizontal frequency from a conversion device or the like that doubles the number of scanning lines, in addition to an image of an ordinary television broadcast. The present invention relates to a multi-scanning television receiver capable of performing.

[Conventional technology]

For example, in an NTSC television signal, an image is formed with a vertical frequency of about 60 Hz and a horizontal frequency of about 15.75 kHz. On the other hand, there has been proposed a conversion device that doubles the number of scanning lines by arithmetic processing or the like to improve the image quality of an image received. When using this device, the signal output from this device has a vertical frequency of about 60 Hz and a horizontal frequency of about 31.5 kHz.
It has become.

In addition, there is a so-called high-resolution display computer output signal having a horizontal frequency of about 24 kHz. In the so-called high-definition television, the horizontal frequency is scheduled to be about 33.75kHz. Thus, a multi-scanning television receiver has been proposed in which a single device can receive various signals having different horizontal frequencies.

First, a multi-scanning image receiver proposed by the present applicant will be described with reference to FIGS. 3 to 6.

FIG. 3 shows an overall block diagram. In this figure, a normal TV broadcast tuner or video tape recorder,
When receiving a normal video signal from a video disc player, a satellite broadcast tuner, or some personal computers, the video signal supplied to the input terminal (1) passes through the video process circuit (2) to the RGB process circuit.
It is supplied to (3) and the three primary color signals are formed. The video / RGB switching signal supplied to the input terminal (4) is RGB
The three primary color signals from the video signal selected by the process circuit (3) are supplied to the cathode ray tube (6) through the output circuit (5).

Further, the video signal from the input terminal (1) is supplied to the sync separation circuit (7) to separate the vertical and horizontal sync signals. Further, the switching signal from the input terminal (4) is supplied to the sync separation circuit (7), the vertical synchronization signal from the video signal selected by this is supplied to the vertical deflection circuit (8), and the formed vertical deflection signal is formed. Are supplied to the vertical deflection yoke (9) of the cathode ray tube (6). Further, the horizontal sync signal from the video signal selected by the sync separation circuit (7) is the AFC circuit (10) and the mode detection circuit (1
1), the signal from the AFC circuit (10) is supplied to the horizontal oscillator circuit (12), and the normal-time control signal from the mode detection circuit (11) is supplied to the horizontal oscillator circuit (12). To be done. The signal from the horizontal oscillation circuit (12) is supplied to the horizontal deflection circuit (13), and the formed horizontal deflection signal is supplied to the horizontal deflection yoke (14) of the cathode ray tube (6). Further, the signal from the horizontal deflection circuit (13) is supplied to the high voltage generation circuit (15) such as a flyback transformer, and the high voltage is supplied to the high voltage terminal (16) of the cathode ray tube (6), and a part of the signal is AFC circuit
Supplied to (10).

Further, the commercial power supply from the power supply input (17) is supplied to the power supply circuit (18), and the normal voltage corresponding to the signal from the mode detection circuit (11) is supplied to the horizontal deflection circuit (13). Also power input
The commercial power supply from (17) is supplied to the other power supply circuit (19), and the formed voltage is supplied to the other circuit.

As a result, a normal video signal is received. On the other hand, in the case of receiving digital or analog R, G and B three primary color signals (hereinafter referred to as RGB signals) from some personal computers, so-called captain demodulators, teletext demodulators or scan converters. , The digital RGB signal supplied to the input terminals (20R) (20G) (20B) and the analog RGB signal supplied to the input terminals (21R) (21G) (21B) are selected by the selector switch (22). It is selected and supplied to the RGB process circuit (3), selected by the switching signal from the input terminal (4) and supplied to the output circuit (5).

In addition, the digital sync signal from the input terminal (20S) and the analog sync signal from the input terminal (21S) are changed over to the switch (23).
Input to the sync separation circuit (7) and input terminal (4)
Vertical deflection circuit (8) and AF selected by switching signal from
It is supplied to the C circuit (10). Further, the signal from the sync separation circuit (7) is supplied to the mode detection circuit (11) to form a control signal corresponding to the frequency of the horizontal sync signal.
2), the horizontal deflection circuit (13) and the power supply circuit (18).

As a result, an image of a digital or analog RGB signal is received. Further, in the case of performing so-called superimpose image reception in which an RGB signal is displayed by being superimposed on the normal video signal described above, the switching signal supplied to the input terminal (4) is set to the RGB mode and the input terminal ( Ys indicating the position of the superimposed signal supplied to 24)
The signal and the Ym signal indicating the range to be superimposed are supplied to the RGB process circuit (3), and these Ys,
Switching between the video signal and the RGB signal is performed during the Ym signal.

As described above, images of various signals are received. Further, in the above-mentioned apparatus, the horizontal deflection system is specifically configured as follows. In FIG. 4, the horizontal sync signal from the sync separation circuit (7) is supplied to the frequency-voltage conversion circuit (FVC) (31) which constitutes the mode detection circuit (11) to form a voltage corresponding to the horizontal frequency. It This voltage is supplied to the voltage controlled oscillator (VCO) (34) which constitutes the horizontal oscillation circuit (12) through the limiter circuit (32) which determines the lower limit and the buffer amplifier (33). The oscillation output of the VCO (34) is supplied to the switching transistor (36) forming the horizontal deflection circuit (13) through the drive circuit (35).

Further, the voltage from the FVC (31) is supplied to a parametric power supply circuit (39) of, for example, a YZ type which constitutes a power supply circuit (18) through a limiter circuit (37) which determines upper and lower limits and a control amplifier (38). The output voltage of the power supply circuit (39) is fed back to the amplifier (38) through the voltage dividing circuit (40) to stabilize the output voltage. This output voltage is supplied to the flyback transformer (41).

This flyback transformer (41) has a transistor (3
6) is connected. A series circuit of a damper diode (42), a resonance capacitor (43), a horizontal deflection yoke (14) and an S-shaped correction capacitor (44) is connected in parallel with the transistor (36).

In addition, a detection circuit in which the horizontal synchronization signal constitutes the AFC circuit (10)
The signal from the voltage dividing circuit (46) provided in series with the transistor (36) is supplied to the detection circuit (45) through the low pass filter (LPF) (47) and is supplied to the detection circuit (45).
The C signal is formed. This signal is a low pass filter (L
It is supplied to the control terminal of VCO (34) through PF (48).

Further, capacitors (50) and (51) are connected in parallel with the resonance capacitor (43) through the switch circuit (49). Further, capacitors (53) and (54) are connected in parallel with the S-shaped correction capacitor (44) through the switch circuit (52). Further, the voltage from the FVC (31) is supplied to a comparison circuit (55) for binary comparison corresponding to the input horizontal frequency of 20 kHz and 30 kHz, for example, and the frequency is 20 kHz.
Below, a three-valued comparison output corresponding to each range of 20 to 30 kHz and 30 kHz or more is formed, and according to this comparison output, the two switches incorporated in the switch circuits (49) and (52) are both turned off. Alternatively, control is performed so that either one of them is turned on.

As a result, in this horizontal deflection system, the VCO (34) forms an oscillation signal which is changed to 15 to 34 kHz in synchronization with the input horizontal synchronizing signal to perform horizontal deflection, and at the same time, the power supply circuit (39). At, a voltage is generated that is changed to, for example, 58 to 123 volts according to the horizontal frequency, and control is performed so that the amplitude of horizontal deflection becomes constant. Also resonant capacitors (43)
In parallel with the S-shaped correction capacitor (44), capacitors (50) (51) and (53) (54) are connected in accordance with the horizontal frequency range, and the characteristics are respectively corrected.

The vertical deflection system in the above apparatus is specifically configured as follows. In FIG. 5, a sync separation circuit (7)
The vertical synchronizing signal from the is supplied to the sawtooth wave oscillator (61) that constitutes the vertical deflection circuit (8), and for example, the capacitor (62) is charged and discharged by the current of the current source (63) to form a sawtooth wave. It The sawtooth wave is supplied to the comparison circuit (64) to form a three-valued comparison output indicating a predetermined voltage range and below or above the predetermined voltage range. The comparison output is an up-down counter (UDC) (6
It is supplied to the control terminal of 5). A vertical synchronizing signal is supplied to the counting terminal of the UDC (65). The count value of the UDC (65) is supplied to the DA conversion circuit (DAC) (66), and the current source (63) is controlled by the converted analog value.

Therefore, a sawtooth wave whose peak value (amplitude) is controlled within a predetermined voltage range is extracted from the sawtooth wave oscillator (61) regardless of the frequency of the vertical synchronizing signal. This sawtooth wave output circuit (67)
Through the vertical deflection yoke (9). Further, a series circuit of a capacitor (68) and a resistor (69) is connected in series with the deflection yoke (9), and a voltage divider circuit is connected in parallel with the resistor (69).
(70) is connected. The divided voltage output of the voltage dividing circuit (70) is supplied to the output circuit (67).

As a result, vertical deflection with a constant amplitude is always performed even if the vertical frequency changes. Further, by making one resistor that constitutes the voltage dividing circuit (70) variable, the amplitude of vertical deflection can be arbitrarily controlled.

Further, another set of circuits of the sawtooth wave oscillator (61) to DAC (66) (oscillator (71) to DAC (76)) is provided, and the output value of the DAC (76) of this circuit is the pin distortion correction signal. It is supplied to the forming circuit (77) and, for example, the deflection yoke (9) and the capacitor
The vertical parabolic signal from the connection midpoint of (68) is supplied to the forming circuit (77) to form a pin distortion correction signal. This signal is supplied to the pin distortion correction circuit.

Thus, in the above-mentioned device, horizontal / vertical deflection necessary for various horizontal / vertical frequencies is performed and various signals are received.

[Problems to be Solved by the Invention]

By the way, in the VCO (34) which constitutes the horizontal oscillation circuit (12) of such a multi-scan television receiver, as shown in FIG. 6, a power source of a voltage value + BV is supplied from the power source (18). A resistor (81) and a capacitor (82) connected in series are connected between the power supply terminal (80) and ground, and a pair of differentially connected transistors (83a) (83b) and an inverter circuit ( A transistor that forms a discharge path for a capacitor (82) controlled by one transistor (83a) via
(85) is provided, and VCO (3
The oscillation frequency of 4) is decided. Therefore, when the horizontal frequency of the input signal changes, the resistance value of the resistor (81) needs to be variable so that the oscillation frequency of the VCO (34) changes accordingly.

On the other hand, the detection output of the detection circuit (45) obtained via the LPF (48) passes through the resistor (86) to the resistor (81) and the capacitor (8).
The AFC circuit (10) is supplied to the connection point of 2), and the AFC sensitivity of the AFC circuit (10) is equal to the voltage value of the power source + BV, the detection output of the detection circuit (45), and the resistor (81). It is determined by the ratio of the currents flowing through (86), that is, the ratio between the resistors (81) and (86). For this reason, the resistance value of the resistor (81) is varied to change the VCO.
When the oscillation frequency of (34) is changed, A of the AFC circuit (10)
The FC sensitivity is also changed, and the loop gain and pull-in range of the AFC circuit (10) change.

The present invention has been made in view of the above points by changing the horizontal oscillation frequency.
It proposes a device that can make the AFC sensitivity of the C circuit constant.

[Means for Solving the Problems]

The multi-scan television receiver of the present invention supplies the horizontal synchronizing signal of the input signal to the frequency-voltage conversion circuit (31) as shown in FIG. 1, and the output voltage of the frequency-voltage conversion circuit (31) causes In a multi-scanning television receiver in which the horizontal frequency of the horizontal deflection circuit (13) is switched so that input signals of different horizontal frequencies can be received, the oscillation frequency is changed by the output voltage of this frequency-voltage conversion circuit (31). Voltage-controlled oscillator forming a controlled horizontal oscillation circuit (12)
(34) is provided, and a detection circuit (45) for obtaining an AFC signal by comparing the output signal of the voltage controlled oscillator (34) with the horizontal synchronization signal is provided, and the voltage controlled oscillator is generated by the AFC signal of the detection circuit (45). A to control the oscillation frequency of (34)
The FC circuit (10) is provided with a gain adjusting variable resistor whose resistance value is changed by the switches (91) and (93), and the frequency-
Comparison circuit (94) to which the output voltage of the voltage conversion circuit (31) is supplied
Is provided, and the switches (91) and (93) are switched according to the comparison output of the comparison circuit (94) to change the resistance value of the variable resistor for gain adjustment, so that the sensitivity of the AFC circuit (10) is increased. The input signal is made constant regardless of the horizontal frequency.

[Action]

According to such a configuration, when the horizontal frequency of the input signal is changed, the voltage according to the horizontal frequency of the input signal is supplied from the FVC (31) to the horizontal deflection circuit, and the horizontal frequency of the horizontal deflection circuit is changed. At the same time, the voltage corresponding to the horizontal frequency of the input signal is supplied from the FVC (31) to the AFC circuit (10), and the switches (91, 93) are switched according to the comparison output of the comparison circuit (94) to adjust the gain. The resistance values of the variable resistors (89, 90, 91, 92, 93) are made variable, and the sensitivity of the AFC circuit (10) is made constant regardless of the horizontal frequency of the incoming signal.

〔Example〕

An embodiment of the main part of the multi-scanning television receiver of the present invention will be described below with reference to FIGS. 1 and 2. In FIGS. 1 and 2, FIGS.
The parts corresponding to those in the figure are designated by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 1, (31) indicates an FVC which constitutes the mode detection circuit (11), and the output voltage of this FVC (31) is connected to the base of a PNP type transistor (87) via a buffer amplifier (86). The transistor (87) emitter to resistor (8
8) to the power supply terminal (80) and connect this transistor (8
The collector of 7) is grounded via the capacitor (82). In this case, the buffer amplifier (86), the transistor (87) and the resistor (88) make the oscillation frequency of the VCO (34) equal to the input frequency of the FVC (31).

Further, the detection output of the detection circuit (45) is connected to one end of the resistor (89) via the LPF (48), and the other end of the resistor (89) is connected to the collector of the transistor (87) and the capacitor (82). The resistor (89) and the series circuit of the resistor (90) and the first switch circuit (91) are connected in parallel to this resistor (89).
A series circuit of a resistor (92) and a second switch circuit (93) is connected in parallel with. Further, the output voltage of the FVC (31) is supplied to the comparison circuit (94), one comparison output of the comparison circuit (94) is supplied to the control terminal of the first switch circuit (91), and the comparison circuit (94) is supplied. 94) the other comparison output to the second switch circuit
Supply to the control terminal of (93). In this case, the voltage obtained by converting the input signal of about 15.75 kHz from the FVC (31) is the comparison circuit (94).
Is supplied to the comparator circuit (94), the first and second switch circuits (91) and (93) are both turned off, the collector current of the transistor (87) at that time and the resistor (89). The AFC sensitivity of the AFC circuit (10) is set to a predetermined value according to the ratio of the current flowing to the
When the voltage obtained by converting the input signal of is supplied to the comparison circuit (94), the comparison circuit (94) causes the first and second switch circuits to operate.
(91) and (93) are turned on and off respectively, the collector current of the transistor (87) at that time and the resistors (89) and (9)
The ratio to the current flowing in (0) is about 1 from the above-mentioned FVC (31).
The collector current of the transistor (87) when the voltage converted from the 5.75kHz input signal is output, and the resistor (89) and
Resistor (90) to be equal to the ratio of the current flowing in (90)
When a voltage obtained by setting the resistance value of the FVC (31) and converting the input signal of about 31.5 kHz is supplied to the comparison circuit (94), the comparison circuit (94) causes the first and second switch circuits ( 91) and
(93) is turned off and on, the transistor at that time
The ratio of the collector current of (87) to the current flowing through the resistors (89) and (90) is a transistor when a voltage obtained by converting an input signal of about 15.75 kHz is output from the FVC (31) described above.
The resistance value of the resistor (92) is set so as to be equal to the ratio of the collector current of (87) and the current flowing through the resistors (89) and (90).

On the other hand, the collector of the transistor (87) and the capacitor (82)
The connection point of is connected to the base of the transistor (83a), the collector of this transistor (83a) is connected to the power supply terminal (80) through the resistor (95), and the emitter of this transistor (83a) is connected to the transistor (83b). Is connected in common to the emitter of, the common connection point is grounded via a constant current source (96), and the base of this transistor (83b) is connected in series between the power supply terminal (80) and ground ( 97) and (98) connection point, the collector of this transistor (83b) is connected to the power supply terminal (80), and the resistor (98) and the switch circuit (1
Connect the series circuit of 00).

On the other hand, the signal obtained at the connection point between the collector of the transistor (83a) and the resistor (95) is passed through the inverter circuit (84) to the drive circuit (35), the control terminal of the switch circuit (100) and the transistor (85). This transistor (8
The collector of 5) is connected to the connection point of the collector of the transistor (87) and the capacitor (82), and the emitter of this transistor (85) is grounded. In addition, the resistance values of the resistors (97), (98) and (99) are set so that the transistor (83b) is turned off and on when the switch circuit (100) is turned on and off, respectively. This switch circuit with setting (100)
Are turned on and off when the inverter circuit (84) outputs a high level signal and a low level signal, respectively. The other horizontal deflection system, vertical deflection system, power supply circuit, signal processing system, etc. are constructed in the same manner as shown in FIGS.

According to such a configuration, when an input signal having a horizontal frequency of about 15.75 kHz is received, the input signal of about 15.75 kHz is detected by the detection circuit (4
5) and FVC (31), and about 1 from this FVC (31)
The output voltage obtained by converting the 5.75kHz input signal is supplied to the buffer amplifier (86) and the comparison circuit (94).
The collector current of the transistor (87) is controlled by (86) and the switch circuits (91) and (93) are controlled by the comparison circuit (94).
Are both turned off, the VCO (34) oscillates at about 15.75 kHz, the collector current of the transistor (87) and the resistor (8
A) with a predetermined AFC sensitivity that can be compared with the current flowing in 9)
The FC circuit (10) operates.

When receiving an input signal having a horizontal frequency of about 24 kHz, the input signal of about 24 kHz is detected by the detection circuit (45) and the FVC (31).
Is output to the buffer amplifier (86) and the comparison circuit.
It is supplied to (94) and the collector current of the transistor (87) is controlled by this buffer amplifier (86) and the comparison circuit
The switch circuits (91) and (93) are turned on and off respectively by (94), the VCO (34) oscillates at about 24 kHz and the collector current of the transistor (87) and the current flowing through the resistor (89). The ratio of the AFC circuit is fixed as shown in FIG.
(10) operates with a constant AFC sensitivity. Therefore, even if the horizontal oscillation frequency is changed, the AFC circuit (10) operates with a constant AFC sensitivity, the loop gain and pull-in range of the AFC circuit (10) can be kept constant, and a good image can be received. Can be done.

Even when an input signal with a horizontal frequency of about 31.5 kHz is received, the oscillation frequency of the VCO (34) is about 31.5 with the AFC sensitivity of the AFC circuit (10) kept constant as shown in FIG. It can be oscillated by changing to kHz.

As described above, according to this example, the horizontal synchronizing signal of the input signal is applied to the FVC (31), the output voltage of the FVC (31) is applied to the horizontal deflection circuit, and the horizontal frequency of the horizontal deflection circuit is switched. In a multi-scanning television receiver that receives input signals of different horizontal frequencies, the output voltage of the FVC (31) is applied to the AFC circuit (10) to which the horizontal synchronizing signal is applied, and the AFC sensitivity of the AFC circuit (10) is applied. Since it is made constant regardless of the horizontal frequency of the input signal, the AFC sensitivity of the AFC circuit (10) becomes constant even if the horizontal oscillation frequency is changed,
The loop gain and pull-in range of the AFC circuit (10) can be kept constant, and good image reception can be performed.

In the above embodiment, the horizontal frequency of the input signal is about 1
AFC circuit for 5.75, about 24 and about 31.5kHz
Although the case where the AFC sensitivity of (10) is made constant is described, it is needless to say that the present invention can be applied to an input signal of about 33.75 kHz and other horizontal frequencies. Further, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

〔The invention's effect〕

According to the multi-scanning television receiver of the present invention, the horizontal synchronizing signal of the input signal is applied to the FVC, the output voltage of the FVC is applied to the horizontal deflection circuit, and the horizontal frequency of the horizontal deflection circuit is switched to change the horizontal frequency. In a multi-scanning television receiver that receives the input signal of, the FVC output voltage is applied to the AFC circuit to which the horizontal synchronizing signal is applied so that the sensitivity of the AFC circuit is made constant regardless of the horizontal frequency of the input signal. Therefore, even if the horizontal oscillation frequency is changed, the sensitivity of the AFC circuit is kept constant, the loop gain and pull-in range of the AFC circuit can be kept constant, and there is an advantage that a good image can be received. .

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a main part of a multi-scanning television receiver of the present invention, FIG. 2 is a schematic diagram used to explain FIG. 1, and FIG. 3 is a multi-scanning television image receiver. FIG. 4 is a block diagram showing an example of the machine, FIG. 4 is a configuration diagram showing the horizontal deflection system of FIG. 3 extracted, and FIGS. 5 and 6 are third diagrams respectively.
It is a block diagram which extracts and shows the vertical deflection system of a figure. (1), (20S) and (21S) are input terminals, (10) is an AFC circuit, (12) is a horizontal oscillation circuit, (31) is an FVC, and (34) is a VC.
O, (45) is a detection circuit, (48) is an LPF, (82) is a capacitor, (86) is a buffer amplifier, (87) is a transistor, (8)
8), (89), (90) and (92) are resistors, (91) and (93) are first and second switch circuits, respectively, and (94) is a comparison circuit.

Claims (1)

[Claims] 1. A horizontal synchronizing signal of an input signal is supplied to a frequency-voltage conversion circuit, and the horizontal frequency of a horizontal deflection circuit is switched by the output voltage of the frequency-voltage conversion circuit to receive input signals of different horizontal frequencies. In the multi-scan type television receiver capable of performing the above, a voltage controlled oscillator that constitutes a horizontal oscillation circuit whose oscillation frequency is controlled by the output voltage of the frequency-voltage conversion circuit is provided, and the output signal of the voltage controlled oscillator and the above A gain control circuit is provided with a detection circuit for comparing with a horizontal synchronization signal to obtain an AFC signal, and the AFC signal of the detection circuit controls the oscillation frequency of the voltage controlled oscillator. A variable resistor is provided and a comparison circuit to which the output voltage of the frequency-voltage conversion circuit is supplied is provided, and a comparison output of the comparison circuit is provided. The sensitivity of the AFC circuit is made constant regardless of the horizontal frequency of the input signal by changing the resistance value of the gain adjusting variable resistor by switching the switch according to the force. Multi-scanning type television receiver.