JPH0658981A - Current detecting circuit for cmos integrrated circuit - Google Patents

Abstract

PURPOSE:To obtain a current detecting circuit for CMOS circuit with which current consumption under various static states of the CMOS circuit can be measured in a short time. CONSTITUTION:Since pass/fail of a CMOS circuit 2 can be decided by comparing voltage drop due to consuming current under static state thereof with a voltage reference through 8 comparator 10 built in an integrated circuit 1, the integrated circuit 1 is simply required to be connected directly with external power supply voltage for test VTEST and a voltage reference VREF and thereby stray capacitance of external wiring can be decreased with respect to a power supply terminal 3 onto which power supply voltage is applied during normal operation. Consequently, operating time of CMOS circuit 2 required for making transition from one static state to another static state can be shortened resulting in the enhancement of decision efficiency of CMOS circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a CM suitable for efficiently detecting current consumption of a CMOS integrated circuit in a stationary state.
The present invention relates to a current detection circuit of an OS integrated circuit.

[0002]

2. Description of the Related Art Generally, a packaged integrated circuit is individually subjected to a functional test before being shipped, and only an integrated circuit which passes this test is shipped unambiguously. For example, when testing the function of an integrated circuit having a CMOS device, it is performed by examining the current consumption in a static state inside the integrated circuit. That is, CMOS
Since the current consumption when the operation of the element is stopped is extremely small on the order of nA, when the current consumption deviates from the nA order, it is determined that the CMOS element is in an abnormal state.

FIG. 2 shows that the operation of the above CMOS device is stopped.
Schematic used to measure current consumption while running
Is. In FIG. 2, (11) is an integrated circuit,
The MOS transistor is connected in CMOS inside the circuit (11).
It is assumed that the CMOS circuit (12) is formed.
Power supply terminal V derived from integrated circuit (11)_DDAnd ground terminal
V_SSIs a CMOS circuit for operating the CMOS circuit (12).
Is internally connected to the line (12) and is connected to the power supply terminal V _DDas well as
Ground terminal V_SSPower supply V between_TESTAnd ammeter (13)
Column connected.

Then, the consumption current in a stationary state where the operation of the CMOS circuit (12) is stopped is measured by an ammeter (13),
By checking whether or not the value is on the order of nA, it is judged whether or not the CMOS circuit (12) is normal.

[0005]

However, when the ammeter (13) and the power source V _TEST are connected in series outside the integrated circuit (11) as shown in FIG. 2, the power source terminal V _DD and the ground terminal V _SS are connected to each other. Since the routing of the power supply line becomes long, the stray capacitance between the power supply terminal V _DD and the ground terminal V _SS cannot be ignored. In general, when the CMOS circuit (12) is stopped in a certain state and current consumption is measured and then the CMOS circuit (12) is stopped in a different state to measure current consumption, the former still state may be changed to the latter still state. The CMOS circuit (12) must be operated. However, due to the existence of the above-mentioned stray capacitance, the CMOS circuit (12) requires a time of μsec order from one stationary state to the next stationary state. Considering that the normally required change time between the respective quiescent states of the CMOS circuit (12) is on the order of nsec, in the circuit of FIG. 2, the operation of the CMOS circuit (12) is stopped in an arbitrary state. Measure the current consumption and
There is a problem that it takes a lot of time to judge the quality of the MOS circuit (12). This has been a cause of delaying the shipment of the integrated circuit (11) and increasing the cost for measurement.

Therefore, an object of the present invention is to provide a current detection circuit for a CMOS circuit, which can measure the current consumption of the CMOS circuit in various stationary states in a short time.

[0007]

The present invention has been made to solve the above-mentioned problems, and is characterized in that the current consumption of a CMOS integrated circuit in a stationary state is measured, and the CMOS CMO for judging the quality of integrated circuits
In the current detection circuit of the S integrated circuit, a CMOS circuit formed by connecting MOS transistors in CMOS, a test power supply terminal to which a test power supply voltage is applied, and a CMOS power supply terminal connected to the CMOS circuit via the test power supply terminal, The CMO
In order to prevent the voltage drop of the measuring resistor that causes a voltage drop corresponding to the current consumption of the S circuit and the voltage drop of the measuring resistor from exceeding a predetermined value when the current consumption of the CMOS circuit exceeds a predetermined value, the measurement At least one suppressing diode connected in series at both ends of the resistance for resistance is compared with the voltage generated by the voltage drop of the resistance for measurement and the reference voltage to obtain the CMO.
And a determination circuit that determines whether or not the current consumption of the S circuit is within a normal range.

[0008]

According to the present invention, the voltage drop and the reference voltage caused by the consumption current in the static state of the CMOS circuit are converted into the CM.
Since the judgment circuit provided inside the OS integrated circuit is used to judge whether the CMOS circuit is good or bad, the CMO
It is only necessary to directly connect the test power supply voltage and the reference voltage to the S integrated circuit, and it is possible to reduce the addition of stray capacitance to the power supply terminal during normal operation due to external wiring.
As a result, the operation time required for the CMOS circuit to change from one stationary state to the next stationary state can be shortened, and the determination efficiency of the CMOS circuit can be improved.

[0009]

The details of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing a current detection circuit of a CMOS integrated circuit according to the present invention. In FIG. 1, (1) is an integrated circuit having a CMOS structure, and has a MOS transistor CM inside.
A CMOS circuit (2) formed by OS connection is built in.
Further, from the integrated circuit (1), a power supply terminal (3) to which the power supply voltage V _DD is applied during normal operation, and a test power supply voltage V _TEST are applied when the quality of the CMOS circuit (2) is judged. Power supply terminal for testing (4), output terminal (5) for outputting the P / F of the judgment result P / F of the CMOS circuit (2), reference voltage V _REF
A reference terminal (6) to which is applied and a ground terminal (7) to be grounded are led out. The power supply terminal (3) and the ground terminal (7) are connected to the CM so that the CMOS circuit (2) can operate.
It is connected to a desired portion of the OS circuit (2).

Inside the integrated circuit (1), (8) is a CM
This is a measuring resistor for measuring the current consumption in a stationary state where the operation of the OS circuit (2) is stopped, and is connected between the test power supply terminal (4) and the power supply part of the CMOS circuit (2). ing. That is, the quality of the CMOS circuit (2) is determined based on the voltage drop across the measuring resistor (8). Since the current consumption of the CMOS circuit (2) in the stationary state is extremely small on the order of nA,
Measuring resistor (8) for easy judgment of circuit (2)
Is set to a large value of at least kΩ order.

Further, (9) is at least one suppressing diode connected to both ends of the measuring resistor (8). Here, in the CMOS circuit (2), although the current consumption when the operation is stopped is extremely small, the current consumption during the operation is μ
Since it is as large as A order, the voltage drop of the measuring resistor (8) during the operation of the CMOS circuit (2) becomes extremely large. In this state, CMOS
During the operation of the circuit (2), the power supply voltage applied to the CMOS circuit (2) falls below the minimum voltage level required for the CMOS circuit (2) to operate normally.
This leads to malfunction of the OS circuit (2). Therefore, during the operation of the CMOS circuit (2), measurement is performed until the power supply voltage applied to the CMOS circuit (2) becomes equal to or lower than the minimum necessary voltage level required to operate the CMOS circuit (2) normally. Suppression diode to suppress the terminal voltage of the measuring resistor (8) so that the voltage drop of the operating resistor (8) does not occur.
(9) is provided. That is, the suppression diode (9)
The number of stages of the CMOS circuit is defined as
(2) is set to a number that can be suppressed to the lowest voltage that allows normal operation.

Reference numeral (10) is a comparator (determination circuit), the non-inverting input (+) terminal is connected to one end of the measuring resistor (8), and the inverting input (-) terminal is the reference terminal (6). It is connected. That is, when measuring the current consumption in the state where the operation of the CMOS circuit (2) is stopped, if the CMOS circuit (2) is normal, the voltage drop of the measuring resistor (8) from the test power supply voltage V _TEST. When the voltage obtained by subtracting is higher than the reference voltage V _REF and the CMOS circuit (2) is abnormal due to gate breakdown or the like, a large through current flows.
The voltage obtained by subtracting the voltage drop of the measuring resistor (8) from the test power supply voltage V _TEST is lower than the reference voltage V _REF . That is, a high level is output from the comparator (10) when the CMOS circuit (2) is normal, and on the contrary CM
When the OS circuit (2) is abnormal, a low level is output, and these determination results are output as the pass / fail determination result P / F via the output terminal (5).

As is apparent from the above-described configuration of FIG.
Since the suppression diode (9) is provided in the
To change (2) from one stationary state to the next stationary state, the CM
Even if the OS circuit (2) is operated, the voltage drop of the measuring resistor (8)
It is possible to suppress the bottom to the terminal voltage of the suppression diode (9).
Therefore, it is possible to operate the CMOS circuit (2) while the CMOS circuit (2) is operating.
Supply the line (2) with a power supply voltage that allows it to operate normally.
can do. In addition, the power supply for testing the integrated circuit (1)
Power supply V directly to terminal (4) and reference terminal (6) _TESTas well as
V_REFThe quality of the CMOS circuit (2) can be determined simply by connecting
Since this can be done, the addition of stray capacitance to the power supply terminal (3) can be reduced.
This allows the CMOS circuit (2) to
CMOS times required to move from one state to the next
The operation of the path (2) can be performed in a short time, that is, the integration time
The quality of the road (1) can be determined at high speed.

[0014]

According to the present invention, the judgment circuit provided inside the CMOS integrated circuit compares the voltage drop caused by the consumption current of the CMOS circuit in the stationary state with the reference voltage to judge whether the CMOS circuit is good or bad. Therefore, it is only necessary to directly connect the test power supply voltage and the reference voltage to the CMOS integrated circuit, and it is possible to reduce the stray capacitance added to the power supply terminal by the external wiring during the normal operation. As a result, the operation time required for the CMOS circuit to change from one stationary state to the next stationary state can be shortened, and the determination efficiency of the CMOS circuit can be increased.

[Brief description of drawings]

FIG. 1 is a diagram showing a current detection circuit of a CMOS integrated circuit of the present invention.

FIG. 2 is a diagram showing a current detection circuit of a conventional CMOS integrated circuit.

[Explanation of symbols]

 (1) Integrated circuit (2) CMOS circuit (4) Test power supply terminal (8) Measurement resistor (9) Suppression diode (10) Comparator

Claims (3)

[Claims] 1. A current detection circuit of a CMOS integrated circuit for measuring current consumption of the CMOS integrated circuit in a stationary state to judge pass / fail of the CMOS integrated circuit, and a CMOS circuit in which MOS transistors are connected in CMOS, and a test. A test power source terminal to which a power source voltage is applied, a measuring resistor connected to the CMOS circuit via the test power source terminal, and causing a voltage drop according to the current consumption of the CMOS circuit; At least one suppressing diode connected in series at both ends of the measuring resistor to prevent the voltage drop of the measuring resistor from exceeding a certain value when the current consumption exceeds a predetermined value; Judgment comparing the voltage generated by the voltage drop of the resistor and the reference voltage to judge whether the current consumption of the CMOS circuit is within the normal range The current detection circuit of the CMOS integrated circuit comprising: the road, the. 2. The number of stages of the suppression diode is C
The voltage drop of the measuring resistor according to the current consumption when the MOS circuit is operating is set to a number that can be suppressed to the minimum voltage at which the CMOS circuit can operate. A current detection circuit of the CMOS integrated circuit described. 3. The current detection circuit of a CMOS integrated circuit according to claim 2, further comprising a normal power supply terminal for operating the CMOS circuit, to which a power supply voltage is applied during normal operation.