JPH065884A - Diode - Google Patents

Diode

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Publication number
JPH065884A
JPH065884A JP15986592A JP15986592A JPH065884A JP H065884 A JPH065884 A JP H065884A JP 15986592 A JP15986592 A JP 15986592A JP 15986592 A JP15986592 A JP 15986592A JP H065884 A JPH065884 A JP H065884A
Authority
JP
Japan
Prior art keywords
layer
region
electrode
conductivity type
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15986592A
Other languages
Japanese (ja)
Inventor
Masamitsu Wakasa
正光 若狭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP15986592A priority Critical patent/JPH065884A/en
Publication of JPH065884A publication Critical patent/JPH065884A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To provide a diode with stable surge withstand voltage by replacing the P<+> layer of an N<+>-N<->-P<->-P<+> diode by an N<+> region with opposite conductivity type. CONSTITUTION:An impurity out of a surface of an N<-> silicon layer 3 with low impurity density is diffused to form a P<+> layer 4 with low impurity density on an N<+> silicon substrate with high impurity density. Impurity diffusion is carried out through a window part in an SiO2 film 6 to form a circular P<+> region 5 with high impurity density. Impurity diffusion is carried out again at a central part thereof to form a circular N<+> region 8 with high impurity density. When an electrode 7 is positively and an electrode 1 is negatively biased, the electrons injected from the N<+> substrate 2 into a P<-> layer 4 is caused to flow through the N<+> region 8 and reach the electrode 7. Then, when a negative overvoltage is applied to the electrode 7 and a positive voltage to the electrode 1, an avalanche breakdown is caused at a junction between an N<-> layer 3 and the P<+> layer 4, but an NPN structure formed with the N<+> region 8 is put in an on-state. Consequently, an overvoltage is absorbed and the surge withstanding voltage can be improved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体のpn接合によ
る整流作用を利用したダイオードに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diode utilizing the rectifying function of a semiconductor pn junction.

【0002】[0002]

【従来の技術】電源の高効率化、高周波化が最近さらに
進んで来ている。この要求に適したダイオードとして
は、逆電圧回復時間trrが短く、順電圧VF が低く、さ
らには電源配線路における誘導ノイズに対してサージ耐
量が高いことが要求される。これに対し、図2に示すよ
うに高不純物濃度のN+ 基板2上に同導電型で低不純物
濃度のN- 層3を形成し、このN- 層内に逆導電型で低
不純物濃度のP- 層4を形成し、さらにそのP- 層内に
高不純物濃度のP+ 層5を設けた構造で、N+ 基板2の
表面にカソード電極1、P+ 層表面に酸化膜6の開口部
でアノード電極7が接触する、比較的VF の小さいダイ
オードが製作できる。
2. Description of the Related Art Recently, higher efficiency and higher frequency of power supplies have been further advanced. A diode suitable for this requirement is required to have a short reverse voltage recovery time trr , a low forward voltage V F , and a high surge resistance against induced noise in a power supply wiring path. On the other hand, as shown in FIG. 2, an N layer 3 of the same conductivity type and a low impurity concentration is formed on an N + substrate 2 of a high impurity concentration, and an N layer 3 of the opposite conductivity type and a low impurity concentration is formed in this N layer. The P layer 4 is formed, and the P + layer 5 having a high impurity concentration is further provided in the P layer. The cathode electrode 1 is formed on the surface of the N + substrate 2 and the oxide film 6 is formed on the surface of the P + layer. It is possible to manufacture a diode having a relatively small V F in which the anode electrode 7 is in contact with each other.

【0003】[0003]

【発明が解決しようとする課題】しかし、図2のような
構造は、trrを短くするには難しく、電源の高周波化に
対して不都合であり、またサージ耐量を向上するために
はダイオードの体積を大きくしなければならないという
問題があった。本発明の目的は、上述の問題を解決し、
電源の高効率化、高周波化に対応できるダイオードを提
供することにある。
However, the structure as shown in FIG. 2 is difficult to shorten trr and is inconvenient for increasing the frequency of the power source. Further, in order to improve the surge withstand capability, the diode is not used. There was a problem that the volume had to be increased. The object of the present invention is to solve the above problems,
An object of the present invention is to provide a diode which can cope with high efficiency and high frequency of a power supply.

【0004】[0004]

【課題を解決するための手段】上記の目的を達成するた
めには、本発明のダイオードは一側に高不純物濃度の層
を備えた第一導電型の層の他側に低不純物濃度の第二導
電型の層を備え、その第二導電型の層の表面層にそれぞ
れ高不純物濃度の第一導電型の領域と第二導電型の領域
とが隣接して設けられ、その両領域の表面に共通に電極
が接触するものとする。そして、第一導電型の領域が環
状の第二導電型の領域に囲まれていても、あるいは第二
導電型の領域が環状の第一導電型の領域に囲まれていて
もよい。
In order to achieve the above object, the diode of the present invention comprises a layer of high impurity concentration on one side and a layer of low impurity concentration on the other side of the first conductivity type layer. A second conductivity type layer is provided, and a first conductivity type region having a high impurity concentration and a second conductivity type region are provided adjacent to each other on the surface layer of the second conductivity type layer, and the surfaces of both regions are provided. The electrodes are commonly in contact with. Then, the first conductivity type region may be surrounded by the annular second conductivity type region, or the second conductivity type region may be surrounded by the annular first conductivity type region.

【0005】[0005]

【作用】第一導電型の層と第二導電型の層の間のPN接
合に対する順バイアスが印加されたとき、第一導電型の
高不純物濃度の層から低不純物濃度の層を経て第二導電
型の不純物濃度の層に注入された少数キャリアは、障壁
のない第一導電型の高不純物濃度領域から電極に到達す
るため、VF が小さくなる。そしてオフ時には、少数キ
ャリアの蓄積がなく、高不純物濃度の第二導電型領域お
よび第一導電型領域が同一電極に接していることから動
作抵抗が小さくなり、trrが短くなる。また、第一導電
型の層と第二導電型の層の間のPN接合に対して過電圧
の逆バイアスが印加され、アバランシェ降伏したときに
は、第二導電型の層を第一導電型の層および領域ではさ
んでいることによって形成されるNPN構造あるいはP
NP構造がブレークオーバしてオン状態になるため、過
電圧が吸収され、サージ耐量が向上する。
When a forward bias is applied to the PN junction between the first conductivity type layer and the second conductivity type layer, the first conductivity type high impurity concentration layer passes through the low impurity concentration layer Since the minority carriers injected into the layer having the conductivity type impurity concentration reach the electrode from the first conductivity type high impurity concentration region having no barrier, V F becomes small. At the time of off, there is no accumulation of minority carriers, and since the second conductivity type region and the first conductivity type region having a high impurity concentration are in contact with the same electrode, the operating resistance becomes small and trr becomes short. When an overvoltage reverse bias is applied to the PN junction between the first-conductivity-type layer and the second-conductivity-type layer to cause avalanche breakdown, the second-conductivity-type layer and the first-conductivity-type layer are NPN structure or P formed by interposing in the area
Since the NP structure breaks over and is turned on, the overvoltage is absorbed and the surge withstand capability is improved.

【0006】[0006]

【実施例】以下、図2と共通の部分に同一の符号を付し
た図を引用して本発明の実施例について述べる。図1に
示した実施例では、高不純物濃度のN+ シリコン基板2
上にエピタキシャル法で形成した低不純物濃度のN-
リコン層3の表面からの不純物拡散により10〜20μmの
深さの低不純物濃度のP- 層4を形成したのち、その表
面を覆うSiO2 膜6の窓部からの不純物拡散により5〜
10μmの深さで直径0.7mmの円形の高不純物濃度のP+
領域5を形成し、さらにその中央部へ再度不純物拡散を
行って直径0.05〜0.1mmの円形の高不純物濃度のN+
域8を形成した。アノード電極7はP+ 領域5およびN
+ 領域8に共通に接触している。このダイオードの電極
7にプラス、電極1にマイナスのバイアス電圧を加えた
場合、N+ 基板2からP- 層4に注入された電子はN+
領域8を通って電極7に到達する。そして、電極7にマ
イナス、電極1にプラスの過電圧が印加され、N- 層3
とP- 層4の間の接合にアバランシェ降伏が起きたとき
には、N+ 領域8とによって形成されるNPN構造がオ
ン状態になる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawing in which the same reference numerals are given to the same parts as in FIG. In the embodiment shown in FIG. 1, the N + silicon substrate 2 having a high impurity concentration is used.
After a low impurity concentration P layer 4 having a depth of 10 to 20 μm is formed by the impurity diffusion from the surface of the low impurity concentration N silicon layer 3 formed by the epitaxial method, a SiO 2 film covering the surface is formed. 5 due to impurity diffusion from the window of 6
Circular high impurity concentration P + with a diameter of 0.7 mm at a depth of 10 μm
Region 5 was formed, and impurity diffusion was performed again to the central portion to form a circular N + region 8 having a high impurity concentration and having a diameter of 0.05 to 0.1 mm. Anode electrode 7 is P + region 5 and N
+ Commonly touches the area 8. When a positive bias voltage is applied to the electrode 7 of the diode and a negative bias voltage is applied to the electrode 1, the electrons injected from the N + substrate 2 into the P layer 4 are N +.
The electrode 7 is reached through the region 8. Then, a negative overvoltage is applied to the electrode 7 and a positive overvoltage is applied to the electrode 1, so that the N layer 3
When the avalanche breakdown occurs at the junction between the P + layer 4 and the P layer 4, the NPN structure formed by the N + region 8 is turned on.

【0007】図3に示した実施例では、N+ 領域8が円
環状に形成され、P+ 領域5をとり囲んでいる。これ
は、過電圧の逆バイアスが印加され、NPN構造がオン
状態になった場合にN+ 領域8を流れる短絡電流を外周
部に分散することにより、電流集中が改善され、また熱
放散も良好になるので、耐圧が向上し、安定する。
In the embodiment shown in FIG. 3, the N + region 8 is formed in an annular shape and surrounds the P + region 5. This is because the reverse current bias is applied and the short-circuit current flowing in the N + region 8 is distributed to the outer peripheral portion when the NPN structure is turned on, whereby current concentration is improved and heat dissipation is also improved. Therefore, the breakdown voltage is improved and stabilized.

【0008】[0008]

【発明の効果】本発明によれば、N+ −N- −P- −P
+ 構造をもつダイオードのP+ 層あるいはN+ 層の一部
を逆導電型のN+ 領域あるいはP+ 領域に置き換えるこ
とにより、VF が低く、trrが短く、さらにサージ耐量
が向上し、安定したダイオードが得られた。
According to the present invention, N + -N -- P -- P
By replacing a part of the P + layer or the N + layer of the diode having the + structure with the N + region or the P + region of the reverse conductivity type, the V F is low, the trr is short, and the surge withstand capability is further improved. A stable diode was obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例のダイオードの断面図FIG. 1 is a sectional view of a diode according to an embodiment of the present invention.

【図2】従来のダイオードの断面図FIG. 2 is a sectional view of a conventional diode.

【図3】本発明の別の実施例のダイオードの断面図FIG. 3 is a sectional view of a diode according to another embodiment of the present invention.

【符号の説明】 1 カソード電極 2 N+ 基板 3 N- 層 4 P- 層 5 P+ 領域 7 アノード電極 8 N+ 領域[Explanation of reference numerals] 1 cathode electrode 2 N + substrate 3 N layer 4 P layer 5 P + region 7 anode electrode 8 N + region

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】一側に高不純物濃度の層を備えた第一導電
型の層の他側に低不純物濃度の第二導電型の層を備え、
その第二導電型の層の表面層にそれぞれ高不純物濃度の
第一導電型の領域と第二導電型の領域とが隣接して設け
られ、その両領域の表面に共通に電極が接触することを
特徴とするダイオード。
1. A layer of the first conductivity type having a high impurity concentration layer on one side, and a layer of the second conductivity type having a low impurity concentration on the other side.
A region of the first conductivity type and a region of the second conductivity type each having a high impurity concentration are provided adjacent to each other on the surface layer of the layer of the second conductivity type, and the electrodes commonly contact the surfaces of both regions. A diode characterized by.
【請求項2】第一導電型の領域が環状の第二導電型の領
域に囲まれた請求項1記載のダイオード。
2. The diode according to claim 1, wherein the first conductivity type region is surrounded by the annular second conductivity type region.
【請求項3】第二導電型の領域が環状の第一導電型の領
域に囲まれた請求項1記載のダイオード。
3. The diode according to claim 1, wherein the second conductivity type region is surrounded by an annular first conductivity type region.
JP15986592A 1992-06-19 1992-06-19 Diode Pending JPH065884A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15986592A JPH065884A (en) 1992-06-19 1992-06-19 Diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15986592A JPH065884A (en) 1992-06-19 1992-06-19 Diode

Publications (1)

Publication Number Publication Date
JPH065884A true JPH065884A (en) 1994-01-14

Family

ID=15702911

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15986592A Pending JPH065884A (en) 1992-06-19 1992-06-19 Diode

Country Status (1)

Country Link
JP (1) JPH065884A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006179823A (en) * 2004-12-24 2006-07-06 Matsushita Electric Ind Co Ltd Surge protecting semiconductor device and its manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006179823A (en) * 2004-12-24 2006-07-06 Matsushita Electric Ind Co Ltd Surge protecting semiconductor device and its manufacturing method

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