JPH065878B2 - Image processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image processing apparatus having an image identification function suitable for use in a digital copying machine, a facsimile, and the like.

[Prior Art] Conventionally, in this type of device, when a document in which characters and halftone images are mixed is reproduced or encoded and transmitted, the image tone (characteristics or characteristics of the image) is different, so that the entire document is covered. The same playback process or the same code and decoding could not be applied. Therefore, it is necessary to identify different image tones in the manuscript, and various proposals have been made. However, it is difficult to provide a processing device that is suitable for high-speed processing and has a small hardware scale and that has an image-tone identification function. Further, it is difficult to accurately distinguish the halftone image and the line image such as characters.

[Object] The present invention has been made in view of the above points, and it is an object of the present invention to provide an image processing apparatus that can accurately distinguish a halftone image and a line image with a simple configuration.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an image processing apparatus according to the present embodiment. In the figure, reference numeral 16 has a sensor such as a CCD, and a document is read by this sensor and 6-bit image data IS
Is an image reading unit that outputs Note that this sensor is a line sensor, which electrically scans the document in the line direction (main scanning direction) and mechanically scans in the direction perpendicular to the line direction (sub scanning direction) to read the entire document. . Reference numeral 10 is a two-dimensional smoothing circuit (smoothing unit) that performs two-dimensional smoothing processing on the 6-bit image data IS, and 11 is image data smoothed by the two-dimensional smoothing circuit 10 (smoothed signal SS). ) Is subjected to dither processing (halftone processing) by a predetermined dither matrix,
It is a dither processing circuit (dither binarization unit) for digitizing. With the above configuration, the dither processing circuit can obtain the binarized signal DS in which moire is suppressed. Reference numeral 12 is the other binarization circuit, which is a 6-bit image data IS.
And the 6-bit image data IS is binarized using the smoothed signal SS as a threshold.

In this embodiment, by using the smoothed image data SS as the threshold value, it is possible to extract and reproduce even a character portion that is likely to be buried in the background image (texture of the original). 13 is 2
Binary signal output from the binarization circuit 12 (high resolution signal)
This is an identification circuit for inputting HS to identify the image tone. The identification circuit 13 determines the feature amount (described later) from the array in the vicinity of the pixel of interest.
Are counted, and the feature amount is thresholded to identify the image tone.
Then, the switch 15 is turned on in accordance with the image-tone identification result RE to select either the binarized signal HS or the binarized signal DS and output it to the recording device 14 such as a laser beam printer. That is, the discrimination circuit 13 selects the binarized signal DS in which moire is suppressed when it is determined that the pixel of interest is a halftone dot area, and is 2 when it is determined to be a line drawing area such as a character.
The binarized signal HS is selected.

The two-dimensional smoothing circuit and the like in FIG. 1 are described in detail in Japanese Patent Application Laid-Open No. 59-246131 filed by the applicant of the present invention, and thus the description thereof is omitted.

Next, the identification circuit 13 shown in FIG. 1 will be described in detail. First, the identification algorithm in this embodiment will be described in detail. In this example, in order to distinguish between a character and a halftone dot image, the following two points are noted as its features.

Generally, the difference between the character features and the halftone image features lies in their spatial frequencies. That is, halftone dot images have high spatial frequencies in both orthogonal directions, but line drawings such as characters are
In many cases, the frequency becomes high only in any one direction.

A halftone dot is a set of round dots, while a character (especially Kanji) is a set of orthogonal straight lines.

Therefore, the identification algorithm used in the present embodiment pays attention to the difference in the frequency components described above, and at the same time, by utilizing the fact that the characters are composed of thin lines, the fine kanji characters that are apt to be erroneously judged as halftone dots have a high number of lines ( It is possible to distinguish from a halftone dot image.

In this embodiment, the feature amount Pf (x, y) is calculated for each pixel in order to identify the image tone of each pixel.

In the area of (2n + 1) × (2m + 1) (n, m is a natural number) near the binarized image P (x, y), the feature amount Pf (x, y) is defined by the following equation.

Here, Q (l, s) ≡P (x + i, y + l) P (x + I + l, y + j + s) is an exclusive OR, and · is a logical product.

The binary image P (x, y) and the adjacent binary image sequence are shown in FIG. 2, and the physical meaning of the feature amount Pf (x, y) will be described. In FIG. 2, the binarized image uses the binarized signal HS output from the binarization circuit 12.

FIG. 2 shows the neighborhood 2 including the pixel of interest P (x, y) (center in the figure).
This shows the binary state of 5 pixels, where black pixels are represented by "●" and white pixels are represented by "○". If the pixel of interest is black, , White is represented by “⊚”. As can be seen from the figure, four pixels (P (x-1, y), which are adjacent to the target pixel P (x, y),
From the state of P (x + 1, y), P (x, y-1), P (x, y + 1)), the isolation and linearity of the target pixel P (x, y) with respect to the neighboring pixels can be recognized. . That is, in FIG. 2 (a), Q (-1,0) = P (x, y) P (x-1, y) = 0 Q (1,0) = P (x, y) P (x + 1, y) = 1 Q (0, -1 = P (x, y) P (x, y-1) = 1 Q (0,1) = P (x, y) P (x, y + 1) = 0, so Q (-1,0) .Q (0, -1) = 0 Q (1,0) .Q (0, -1) = 1 Q (-1,0) .Q (0 , 1) = 0 Q (0,1) · Q (1,0) = 0.

Therefore, in the target pixel P (x, y) of FIG. 2 (a), two pixels adjacent to each other at right angles (for example, P (x, y-1), P (x + 1, y))
Of the array P (x, y-
1) → P (x, y) → P (x + 1, y) exists once. Note that this array is hereinafter referred to as an inverted array. A value obtained by performing the same counting (counting of the inverted array) over each pixel around the pixel of interest and integrating is the feature amount Pf (x, y).

Here, the difference in the characteristic amount Pf (x, y) between the halftone dot and the character will be described with reference to FIGS. 2 (b) and 2 (c). Fig. 2 (b)
Image shows the case where halftone dots are assumed, and Pf (x,
y) is Pf (x, y) = 1 if n = m = 1 in the equation
It becomes 6. Similarly, FIG. 2 (c) shows a case where a thin line is assumed, and Pf (x, y) = 0.

Therefore, if the value of the feature amount Pf (x, y) is thresholded, it is possible in principle to distinguish between a halftone dot area and a line drawing area such as a character.

That is, when Pf (x, y)> K, the pixel of interest P (x, y) belongs to the halftone dot area.

When Pf (x, y) ≦ K, the target pixel P (x, y) belongs to the line drawing area.

Can be judged.

Now, using the above-mentioned algorithm, a halftone dot image of 100 lines / inch or more and a character image are identified, and for the former, dither processing in which moire is suppressed by the dither processing circuit 12 as shown in FIG. If the binarization circuit 12 intends to binarize the latter, it is desirable that m = n = 3 and the value of K be selected from 16 to 20.

Next, the circuit configuration of the identification circuit 13 will be described with reference to FIG. The circuit of FIG. 3 executes the above-mentioned algorithm, but is configured to count the feature amount Pf (x, y) over 6 × 6 neighboring pixels including the pixel of interest.

In the figure, 1-1 to 1-7 are 4K x 1-bit study R
In AM, input binary image HS that is sequentially input is set to 1
Each line is delayed in the sub-scanning direction. 2-1 to 2-8 are delayed flip-flop circuits (hereinafter referred to as DF / F circuits), which are input from a terminal T and a static RAM.
The outputs of 1-1 to 1-7 are delayed by one pixel in the main scanning direction. Further, 3-1 to 3-6 are also D-F / F circuits, and further delay the outputs of the D-F / F circuits 2-2 to 2-7 by one pixel. Therefore static RA
M1-1 to 1-7 and DF / F circuits 2-1 to 2-8,
At the output terminals 3-1 to 3-6, a binary image corresponding to the document can be simultaneously detected two-dimensionally by 8 pixels in the sub scanning direction and 3 pixels in the main scanning direction. 4-1 to 4-19 are exclusive OR circuits (hereinafter referred to as EX-OR gates), and these EX-OR gates are the D-F / F circuit 2-2.
The exclusive OR between 6 pixels corresponding to 2-7 outputs and adjacent pixels is calculated. 5-1 and 5-2 are ROMs,
The operation results of 19 EX-OR gates are input, and it is determined whether or not the levels of two adjacent pixels of the six pixels that are orthogonal and adjacent to each other are both inverted with respect to the pixel of interest, and the number of inverted arrays is counted. In this example, two ROMs 5-1 and 5-2 each having 2 ¹⁰ (= 1K) words are used, and the output of the EX-OR gate 4-10 is input to both chips. Therefore ROM
5-1 and 5-2 are for performing the above-mentioned determination and counting of the inverted array for every three pixels. The outputs of the ROMs 5-1 and 5-2 are added by the adder 6, and the operation result (the integrated value of the inverted array of 6 pixels) is delayed and held by the DF / F circuits 7-1 to 7-5. It is input to the adders 8-1 to 8-3. The adders 8-1 to 8-3 add the above calculation results for two columns in the main scanning direction, and the addition results of each adder are input to the ROM 9. Therefore, a signal corresponding to the trace amount Pf (x, y) obtained from the 6 × 6 pixel area based on the equation is applied to the address input terminal of the ROM 9. The ROM 9 has a table in which the outputs of the adders 8-1 to 8-3 are used as addresses. The table stores a 1-bit identification result RE indicating whether it is a halftone dot pixel or a line image. There is. That is, the ROM 9 stores the feature quantity Pf (x,
y) is input, and the feature amount Pf (x, y) is the value K.
Comparison result of whether or not greater than (1 bit identification signal RE)
Is output.

As described above with reference to FIG. 3, memories such as RAM and ROM,
The image recognition processing can be performed in real time with a simple configuration using a gate circuit or the like.

[Effect] As described above, according to the present invention, each pixel of a plurality of pixels in a block is used as a determination pixel, and for each determination pixel, the levels of two pixels adjacent to the determination pixel are both inverted with respect to the determination pixel. It is determined whether or not there is a calculation, and the sum of the number of inversions by the determination for a plurality of pixels in the block is compared with a predetermined value to identify whether the image tone of the pixel of interest in the block is a halftone dot image or a line image. It is possible to accurately distinguish the halftone image and the line image with a simple configuration.

[Brief description of drawings]

FIG. 1 is a block diagram of an image processing apparatus according to this embodiment,
FIG. 2 is a diagram for explaining the image tone discrimination algorithm in this embodiment, and FIG. 3 is a detailed circuit diagram of the discrimination circuit 13. Here, 10 is a two-dimensional smoothing circuit, 11 is a dither processing circuit, 12 is a binarization circuit, 13 is an identification circuit, 14 is a printer, 15 is a changeover switch, 16 is an image reading unit, 1-1 to 1-1.
1-7 is a static RAM, 2-1 to 2-8, 3-1
3-6, 7-1 to 7-5 are delayed flip-flop circuits, 4-1 to 4-19 are exclusive OR circuits, 5-
1, 5-2 and 9 are ROMs, and 6,8-1 to 8-3 are adders.

Claims (1)

[Claims] 1. A two-dimensional block composed of input means for inputting binary image data and binary image data of a plurality of pixels of main scanning n pixels × sub scanning m pixels input by the input means. And an identifying unit for identifying the image tone of the target pixel, wherein the identifying unit sets each pixel of the plurality of pixels in the block as a determination pixel when identifying the image tone of the target pixel, and It is determined whether or not the levels of two pixels adjacent to the determination pixel are both inverted with respect to the determination pixel, and the sum of the number of inversions by the determination for a plurality of pixels in the block is compared with a predetermined value. An image processing device characterized by identifying whether a picture tone of a pixel of interest is a halftone dot image or a line image.