JPH0658775A - Absolute encoder - Google Patents

Abstract

PURPOSE:To obtain an absolute signals, whose missing is less. CONSTITUTION:With respect to the number of graduations P of an absolute pattern 6, (k) (positive integer) sets of detecting parts satisfying 2<k-1P<=2<k> are constituted of (m) pieces of detecting elements 8, 9, 10 and 11 having the width of lambda/m ((m) is an integer of 3 or more). An incremental signal, which is divided into (m) parts, is used as a timing signal. One detecting element is selected for every detecting part in (k) sets out of (m) pieces of the detecting elements in an absolute-signal detecting means 2 with a signal selecting circuit 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an absolute encoder.

[0002]

2. Description of the Related Art As shown in FIG. 4, a conventional absolute encoder includes a code plate 101, an absolute signal detector 102, an incremental signal detector 103,
And a signal selection circuit 104. Code plate 10
1 includes a 1-track absolute pattern 105 composed of a 4-bit absolute code in a minimum reading unit λ and an incremental pattern 10 having a pitch of λ.
6 and 6 are provided side by side substantially parallel to each other.

The absolute signal detector 102 has a minimum reading unit of the absolute pattern 105 of about λ /.
Absolute light receiving element 10 having a width corresponding to 2
, 108 are combined two by two to combine first detection units 107 and 108 (hereinafter, first detection unit) and second detection units 109 and 110 (hereinafter, second detection unit), It is composed of third detection units 111 and 112 (hereinafter, third detection unit) and fourth detection units 113 and 114 (hereinafter, fourth detection unit).

In the incremental signal detector 103, the incremental light receiving elements 115 and 116 having a width corresponding to about λ / 2 of the incremental pattern are n + λ /.
It is arranged at intervals of 4 (n is an integer). The operation of the signal selection circuit 104 will be described with reference to the timing chart of FIG. 5, but here the first of the absolute signal detectors is used.
Only the detector will be described.

When the code plate 101 moves from the right side to the left side of the drawing, the output of the light receiving element 107 constituting the first detecting section is the signal 117, and the light receiving element 10 of the first detecting section is also output.
The output of 8 is signal 118. Then, the signal selection circuit 1
Reference numeral 04 denotes an absolute detection element 1 when the incremental signal 119 output from one light receiving element 115 which constitutes the incremental signal detector 103 is at a high level.
When 08 is selected and the incremental signal 119 is at a low level, the absolute detection element 107 is selected and output.

That is, the signal selection circuit 104 switches the signal 118 output from the absolute detection element 108 and the signal 117 output from the absolute detection element 107 between the H level and the L level of the incremental signal, and the signal 117. Signal 12 that is a combination of signal 118 and
1 is output from the output section 120 of the signal selection circuit 104 to a signal processing circuit (not shown).

The absolute encoder is configured in this way, and the absolute signal is switched by the incremental signal so as to alternately complement the unstable regions near the rising and falling edges of the absolute signal and output the absolute signal. The above absolute encoder is disclosed in Japanese Patent Application Laid-Open No. 2-168115 by the present applicant.

[0008]

In the conventional technique as described above, as shown in FIG. 5, the signal 121 output from the output section 120 of the signal selection circuit 104 has a dip 12
3 can be seen. This drop 123 occurs when the signal 117 of the absolute light receiving element 107 and the signal 118 of the absolute light receiving element 108 are switched by the incremental signal, and this drop is
Since it approaches the slice level 124 that converts the signal 121 into a rectangular wave, there is a possibility that the waveform of the rectangular wave is broken.

That is, as an absolute encoder, there is a problem that this rectangular crack causes an erroneous output. In order to solve this problem, the dip can be eliminated by making the rising or falling gradient of the waveform of the absolute signal of the first signal and the second signal steep.
As a method of making this gradient steep, a method of reducing the light source, a method of reducing the distance between the code plate and each light receiving element, or the like can be raised. However, when the light source is reduced, the light amount decreases and the light is output from the light receiving element. There is a possibility that mechanical contact may occur if the signal to be reduced becomes small or if the distance between the code plate and the light receiving element is made small.

Further, in order to reduce the distance between the code plate and the light receiving element, it is very difficult to adjust the arrangement of the code plate and the light receiving element. The present invention has been made in view of such a problem, and reduces the drop of the absolute signal that occurs when the absolute signal is switched so as to be complemented alternately with the incremental signal, and obtains a stable absolute signal. To aim.

[0011]

According to a first aspect of the present invention, there is provided a one-track absolute pattern (6) having a minimum reading unit length of λ and a graduation number P (a positive integer).
A code plate (1) on which an incremental pattern (7) having a pitch of λ is formed, and an absolute pattern (6)
Detects, m pieces having a width of 2 ^{k-1 <k} that satisfies P ≦ 2 ^k (positive integer) sets of detector the lambda / m (m is an integer of 3 or more) with respect to the scale number P Detection elements (8, 9, 10, 1
The absolute signal detecting means (2) and the incremental pattern (7) respectively configured in 1) are detected,
An incremental signal detecting means (3) for generating an incremental signal and an incremental signal detected by the incremental signal detecting means (3) are divided into m.
The division circuit (4) and m detection elements (8, 9, 10, 1) forming the absolute signal detection means (2) using the m-divided incremental signals as timing signals.
The signal selection circuit (5) for sequentially selecting one detection element from 1) from each of the k sets of detection units is provided.

[0012]

In the present invention, the eyes of the absolute pattern
2 for the number P^k-1<P ≦ 2 ^kAnd λ / m (m
Is an integer greater than or equal to 3) m detector elements (8,
In the detection unit of k (positive integer) pairs consisting of 9, 10, 11)
Incremental m-divided incremental detector
M mental signals as timing signals for each detector
Detection elements are sequentially selected and the absolute signal rises.
When the unstable areas near the rise and fall are alternately complemented
It is possible to reduce the drop of the
Can be obtained.

[0013]

FIG. 1 shows an embodiment of the present invention. As shown in FIG. 1, the absolute encoder includes a code plate 1, an absolute signal detector 2, an incremental signal detector 3, an m division circuit 4 (m is an integer of 3 or more), and a signal selection circuit 5. It is configured.

The code plate 1 has a minimum reading unit of λ, a first track 6 on which a one-track absolute pattern with a scale number P (P is a positive integer) is formed, and an incremental pattern with a pitch of λ. The second track 7 and the second track 7 are provided in parallel. In this embodiment, a 4-bit absolute pattern having a scale number P of 16 is used.

Therefore, the absolute signal detector 2 is
2 ^k-1 <for 16 scales of absolute pattern
It has k = 4 sets of detection units that satisfy 16 ≦ 2 ^k .
Each detector has a width of about λ / 4 of the minimum reading unit λ,
A total of 16 absolute light receiving elements 8, 9, 10, 11, 12, 13, 14, 15, arranged at ¼ pitch intervals,
It is composed of 16, 17, 18, 19, 20, 21, 22, 23, and each of the four absolute light-receiving elements is combined to form a first detection unit 8, 9, 10, 11, 11.
(Hereinafter, the first detection unit) and the second detection units 12, 13, 1
4, 15 (hereinafter, second detecting unit), and third detecting units 16, 1
7, 18, 19 (hereinafter, third detection unit) and fourth detection unit 2
0, 21, 22, 23 (hereinafter referred to as a fourth detection unit).

As described above, when the absolute signal detector 2 composed of four detectors is arranged on the first track 6 on which the 4-bit absolute pattern is formed, the code plate 1 and the absolute detector 2 are arranged. With the relative movement, the first signal, the second signal, and the third signal of the pulse trains corresponding to the absolute patterns from the respective detection units,
The fourth signal is output. Each of these signals is sequentially output with a phase difference corresponding to 1/4 of the minimum reading unit of the absolute pattern.

In the incremental signal detector 3, the incremental light receiving elements 24 and 25 having a width corresponding to about λ / 2 of the incremental pattern 7 are n + λ / 4 (n).
Are integers) and are spaced apart from each other to generate an A-phase signal and a B-phase signal that are 90 degrees out of phase with each other. The m-division circuit 4 has a second divisional pattern on which an incremental pattern is formed.
It is for dividing the A-phase signal and the B-phase signal output from the incremental signal detector 3 for detecting the track 7, and is a four-division circuit in this embodiment.

The dividing circuit referred to here may be one that divides (interpolates) using a resistor array or one that uses phase division. The signal selection circuit 5 will be described only for the first detection unit for the sake of simplicity. Signal selection circuit 5
When the A-phase signal is at H level and the B-phase signal is at H level,
When the absolute light receiving element 10 is selected and the A phase signal is at the H level and the B phase signal is at the L level, the absolute light receiving element 11 is selected and the A phase signal is at the L level and the B phase signal is at the L level.
At the level, select the absolute light receiving element 8
When the phase signal is at L level and the B phase signal is at H level, the absolute light receiving element 9 is selected.

The operation of the absolute encoder configured as described above will be described with reference to the timing chart of FIG. In the present embodiment, for simplification of description, only the first detection unit of the absolute signal detector 2 will be described. Each of the absolute light receiving elements 8 constituting the first detector when the code plate 1 moves from the right side to the left side of the drawing,
The output signals from 9, 10, and 11 are the signal 26 for the absolute light receiving element 8 and the signal 2 for the absolute light receiving element 9.
7, the absolute light receiving element 10 has a signal 28, and the absolute light receiving element 11 has a signal 29.

Each of the signals 29, 28, 27 and 26 is a pulse train signal corresponding to an absolute pattern, and is output with a phase difference of 1/4 of the minimum reading unit. Each of the signals 29, 28, 27, and 26 is sequentially selected from the absolute light-receiving elements 8, 9, 10, and 11 of the first detector, using the A-phase signal and the B-phase signal divided into four as timing signals. To do.

As described above, the signal selection circuit 5 uses the A-phase signal and the B-phase signal of the incremental signal as the first signal.
A signal 33 obtained by sequentially selecting each of the absolute light receiving elements of the detection unit and complementarily switching the unstable regions of rising and falling of each signal 26, 27, 28, 29 from the output unit 32 of the signal selection circuit 5 is not shown. Is output to the signal processing circuit.

Therefore, in the signal selection circuit 5, the signal drop 34 at the time of switching the light receiving element becomes small, and the signal level becomes sufficiently away from the slice level 35, so that when it is converted into a rectangular wave, rectangular cracking is avoided. be able to. Minimum reading unit of absolute pattern λ
On the other hand, when m detecting elements are arranged, the signal drop becomes 1/2 m.

In this embodiment, m = 4, but m
The case of = 3 will be described. That is, when m = 3, the number of graduations of the absolute pattern and the number of detection units of the absolute signal detector are the same as when m = 4, and the number of graduations is 16 and the number of detection units is 4. The number of light receiving elements that make up each detector is 3
The dividing circuit for dividing the incremental signal is also a three-dividing circuit.

When m = 3, the incremental signal is as shown in FIG.
As shown in FIG. 5, the signal is divided into U signal, V signal, and W signal which are shifted by about 120 degrees. Then, for example, if the U signal is H
When the V signal is L level, the V signal is H level and W
When the signal is L, the W signal is at the H level, and the U signal is at the L level, it is possible to select a preset light receiving element of each detector.

However, the incremental signal detector 12
By arranging the 0-degree phase shift, it is not necessary to provide a three-divided circuit.

[0026]

As described above, according to the present invention, the absolute signal detector for detecting the one track absolute pattern having the minimum reading unit length of λ and the number of scales P (a positive integer) is the number of scales. From ^k detectors (positive integer) consisting of m detectors having a width of λ / m (m is an integer of 3 or more) and satisfying 2 ^k-1 <P ≦ 2 ^k for P The incremental signal that is configured and divided into m is used as a timing signal, and m detecting elements are sequentially selected for each detecting unit to reduce the fall when the unstable regions near the rising and falling of the absolute signal are alternately complemented. can do.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an absolute encoder showing an embodiment according to the present invention.

FIG. 2 is a timing chart showing an operation description of the configuration shown in FIG.

FIG. 3 is a configuration diagram of a conventional absolute encoder.

FIG. 4 is a timing chart showing an operation description of the configuration shown in FIG.

FIG. 5 is a diagram showing rectangular waves that are 120 degrees out of phase.

[Explanation of symbols]

 1 Code plate 2 Absolute signal detector 3 Incremental signal detector 4 Division circuit 5 Signal selection circuit

Claims (1)

[Claims] 1. The length of the minimum reading unit is λ, and the number of scales is P.
(Positive integer) 1-track absolute pattern
And an incremental pattern with a pitch of λ is formed.
Code plate and the absolute pattern are detected, and the scale number P is set.
To 2^k-1<P ≦ 2 ^kOf k (positive integers) satisfying
M detectors with a width of λ / m (m is an integer of 3 or more)
Absolute signal detection with each detection element
Means for detecting the incremental pattern and
Incremental signal detecting means for generating an incremental signal, and an incremental signal detected by the incremental signal detecting means.
An m division circuit for dividing the mental signal by m, and a timing signal for the m divisional incremental signal.
No., the k sets of the absolute signal detecting means
One of the m detecting elements constituting the detecting section of
The detection elements are sequentially selected from each of the k sets of detection units.
And a signal selection circuit that
Encoder.