JPH02168115A - Absolute encoder - Google Patents

Abstract

PURPOSE:To attain a high resolving power by a method wherein a first or second signal from each set of detectors for absolute signals totaling (n) sets each comprising two detectors is selected in accordance with the state of a binary signal delivered from a detector for an incremental signal. CONSTITUTION:A code plate 11 is provided with a track 13 having an absolute pattern and with a track 15 having an incremental pattern, the two tracks being parallel to each other. A detecting element 20 has photodiodes (PD) 21a, 21b to 24a, 24b are detectors for absolute signals and PD 25 as a detector for an incremental signal. A light being applied from above the code plate 11, the absolute pattern of the track 13 is detected on the side of the lower surface of the code plate 11 by the PDs 21a, 21b to 24a, 24b, while the incremental pattern of the track 15 is detected by the PD 25. A signal processing element 30 outputs a pulse train formed by a buffer circuit to output terminals 61 to 64 when a binary signal from a comparator is at a low level, and outputs a pulse train formed by the PDs 21b to 24b to the terminals 61 to 64 when the binary signal is at a high level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an absolute encoder.

[Conventional technology] Conventionally, an example of an absolute encoder is the Japanese Patent Application Laid-open No. 5
7-17', +211 publication mata is Utility Model No. 60-152
As shown in Publication No. 915, the absolute pattern on the code plate is made into one track, a plurality of detectors are arranged in the length direction of this track, and the absolute position is detected by the combination code of the output of each detector. Magnetic or optical absolute encoders are known.

In the conventional absolute encoder described above, whether magnetic or optical, a number of non-contact detectors corresponding to the number of bits of the combination code are tracked to read the binary bits 0 and 1 of the absolute pattern. It is necessary to waveform-shape the output signal from each detector into a rectangular wave using an electric circuit and then convert it into a binary number.

However, when converting the output fS from each detector into a rectangular wave by waveform shaping processing, the rising and falling times are performed after a finite period of time, and the timing inevitably differs between each detector. . Therefore, for example, when making the absolute pattern of the code plate finer in order to increase the resolution of the encoder, synchronization of the rise and fall times and timing of the output pulses of each detector becomes a particular problem, and the relative movement of the detector and code plate becomes a problem. For both forward and reverse directions,
The readout results of each detector output at these rising and falling portions may not be accurate position codes, and there is a risk that errors may occur in the encoder output.

[Problems to be Solved by the Invention] As one solution to this problem, the present inventors added an incremental pattern track to the one-track absolute pattern on the code board, and utilized this incremental track. By operating the latch circuit using the created clock No. 13 as a strobe signal,
We have previously proposed a method for obtaining an absolute output by simultaneously reading the output pulses of each detector at optimal timing (Japanese Patent Application No. 63-170782). An outline of this method is shown in Figs. 4(a) and 4(b). The example in Fig. 4(a) is an optical type example where the number of scale divisions is 24 = 16 (n = 4) pulses.
One absolute pattern track 2 and one incremental track 3 are manufactured on a disc-shaped code plate l. The absolute pattern of track 2 is 000
0110101111001. 4-1~4
-4 is the front sensor for reading and reading track 2, and from this is the absolute 12 which consists of a 4-bit binary code.
get a number. The incremental track 3 is read by a further optical sensor 5. Note that 6 is the rotation axis of the code plate 1.

FIG. 4(b) shows the output circuit, in which the incremental signals from sensor 5 and sensors 4-1 to 4-4 are output.
and the absolute signal from the pulse shaping circuit 1, respectively.
After shaping the waveform into a rectangular wave with 0.10-1 to 10-4, the absolute signal is directly input to the latch circuit 14,
The incremental pulses are manually input to the one-shot circuit 12 to generate clock pulses at both the rising and falling points of the incremental pulses, which are used as strobe signals for the latch circuit 14. In this case, the clock pulse is designed to rise at approximately the center of the pulse width of the unit pulse constituting the absolute signal. Each time a clock pulse arrives, the latch circuit 14 reads the high/low level of the pulse of the absolute signal at that time, latches the value until the next clock comes in, and outputs it to the output terminals 16-1 to 16-4.
continues to output.

This type of latching system avoids the above-mentioned error in the encoder output, but in this system, the clock pulse generated from the incremental signal of another track is used as a strobe signal to latch the absolute signal. For example, when the power is turned on, before the rising or falling edge of the incremental signal is detected, the clock pulse as a strobe signal is not generated, so the correct absolute signal is not output, and the sign is It has been pointed out that the disadvantage is that the plate must be moved by the minimum reading unit of the absolute signal to cause the rise or fall of the incremental signal and then wait for the first latch by the strobe pulse.

The present invention has been made in view of this point, and provides a high-precision absolute encoder that can immediately obtain accurate absolute position detection output even when the power is turned on, and that is extremely unlikely to cause reading errors. The purpose is to

[Means for Solving the Problems] The absolute encoder of the present invention includes a code plate having an absolute pattern track and an incremental pattern track substantially parallel to each other, and a detection device that is movable relative to the code plate in the longitudinal direction of the track. In particular, in order to achieve the above-mentioned problem, the absolute pattern is read and the first signal of the corresponding pulse train and a pulse width corresponding to 1/2 of the minimum reading unit pulse in the pulse train are read. a plurality of sets of absolute signal detectors each generating a second signal having a phase difference; and a binary signal having a repetition period approximately equal to the pulse width of the minimum reading unit pulse in the pulse train by reading the incremental pattern. , a detector for an incremental signal generated with a phase difference of approximately the station of the repetition period with respect to the unit pulse, and a detector for each set of absolute signals when the binary signal takes one value. from said first
and signal selection means for extracting only the signal, and extracting only the - of the second signal when the binary signal has the other value.

[Function] In the absolute encoder of the present invention, when the absolute pattern of the track on the code plate is read by the plurality of sets of absolute signal detectors, each set of detectors outputs the first signal of the pulse train corresponding to the absolute pattern. and a second signal are output. These first and second signals have a phase difference corresponding to 1/2 of the pulse width of the minimum reading unit pulse in the pulse train in each set.

On the other hand, in synchronization with this, the incremental number 8 detector transmits a 2 (W) signal with a repetition period approximately equal to the pulse width of the minimum reading unit pulse to the unit pulse with a repetition period of approximately 1/4 of the repetition period. Caused by phase difference.

The first signal and the second signal each consist of sequences of the same content with a phase difference corresponding to % of the absolute unit pulse width, and the binary signal No. 19 has a repetition period approximately equal to the absolute unit pulse width, and 1 signal and 2nd
It leads or lags the signal by a phase difference corresponding to approximately the unit pulse width.

Therefore, the rising and falling points in the pulse train of the first signal and the second signal are synchronized at which point in the pulse of the binary signal. If synchronized when the binary signal is at a high level, the second (
The rising and falling edges of the pulse train of No. 3 are synchronized with the low level of the binary signal, and conversely, if the rising edges and falling edges of the pulse train of the first signal are synchronized with the low level of the binary signal, the pulse train of the second signal is synchronized. The rising and falling edges in the middle are synchronized with the high level of the binary signal.

An absolute position output can be obtained by selecting either the first signal or the second signal of each set of absolute signal detectors and simultaneously reading the high and low levels. to select the first signal or second signal,
When the binary signal takes one value, only the first signal is taken out from each set of absolute signal detectors, and when the binary signal takes the other value, only the second signal is taken out. is taken out.

In this way, the first signal or the second signal from each set of n sets of two absolute signal detectors is converted into a binary value from the incremental signal detector regardless of the direction of relative movement between the code plate and the detector. It selects and extracts the signals according to the state of the signal, and obtains an absolute position signal output as parallel data of a predetermined number of bits n.

For example, if the absolute pattern of the code plate consists of 4-bit absolute codes, there will be 4 sets of 2 bits each (8 bits in total).
(2) absolute signal detectors and one incremental (I) No. 3 detector are used.

The four sets of absolute signal detectors are arranged in the longitudinal direction of the track so that the pitch of each set corresponds to about % of the minimum reading unit pattern length of the absolute pattern. That is, in this case, each set consists of two detectors with a pitch corresponding to approximately 1/2 of the unit pattern length, and four such sets of detectors are arranged in a cup.

-M-wise, the number of sets of this Absolini No. 118 detector is 21-th x ≦ 2 n-(
There are n pairs that satisfy the relationship 1), and the absolute (m
The total number of separate detectors is 20.

As mentioned above, when four sets of two detectors are arranged for each track of a 4-bit absolute pattern,
With the relative movement, the four sets of detectors sequentially output a first signal and a second signal each consisting of a pulse train having a phase difference corresponding to % of the absolute unit pulse width. The four sets of first signals and the four sets of second signals are both 4-bit parallel data having the same content, but their phases are different from each other with a phase difference corresponding to % of the absolute unit pulse width. During this time, the incremental signal detector synchronously generates a binary signal with a repetition period approximately equal to the absolute unit pulse width, and these two values (No. 3 corresponds to the first signal and the second (No. 3 unit pulse) In other words, the combination of the incremental pattern of the code plate and the detector for the incremental signal has a phase difference of approximately the magnitude of the repetition period. The arrangement and positional relationship relative to the set of vessels is determined.

For example, when the binary signal is at a high level, the signal selection means extracts the first signal of each set as a 4-bit parallel data output and blocks the second signal; The second signal is taken out as a 4-bit parallel data output and the first signal is blocked.

In the present invention, the operation of the signal selection means is performed based on the high and low levels of the binary signal, and the binary signal for this purpose is preferably obtained from the detection signal of an incremental pattern with a constant pitch provided on the code plate. . Also in this case,
The so-called A phase output and B phase output, which are out of phase with each other by 90 degrees, are taken out as detection signals, and the signal selection means selects these A phase outputs.
It is equivalent to perform the selection operation using the B-phase output.

Embodiments of the present invention will be described below with reference to the drawings.

[Embodiment] FIG. 1 shows an embodiment of the present invention in the case of a 4-bit optical absolute encoder using a photoelectric conversion element as a detector.

In FIG. 1, this absolute encoder includes a code plate (scale) 11, a detection unit 20 for reading the absolute signal and incremental signal recorded on the code plate, and a signal from the detection unit to process the signal and determine the absolute position. Signal processing unit 3 converts into 4-bit parallel data representing
It consists of 0.

The code number (scale) 11 is made of a transparent substrate, and on the surface thereof, an opaque part (hatched part) and a transparent part (white part) made of a metal Go stone etc. form r□, IJ bits. First track 13 provided with a pattern
and a second track 15 which divides the entire length of the scale into 32 equal parts and alternately repeats each divided area into an opaque area and a transparent area to form an incremental pattern are provided in parallel.

The absolute pattern formed on the first track 13 is a 4-bit pattern with 16 graduations by dividing the entire length of the scale into 16 minimum reading unit patterns (n=4).
) is the absolute code for the following pattern, called the all-periodic sequence, rOOooololloolllol
J. This absolute pattern consists of four continuous "OJ bits" formed by transparent parts in the first track 13 of FIG.
Single 'rl' bit due to opaque area, single '0' bit due to transparent area, two consecutive 'IJ' bits due to opaque area, two consecutive '0' bits due to transparent area, four consecutive '0' bits due to opaque area one “1” bit,
Shown as a single '0' bit due to transparent parts and a single '1' bit due to opaque parts.

The second track 15 has an incremental pattern for obtaining the binary signal for signal selection,
On this track 15, exactly 1/2 of the minimum reading unit pattern of the absolute pattern is arranged along the entire length.
32 sections with a length corresponding to , are arranged with alternating transparency and opacity, forming an incremental pattern in which the total length is divided into 32 sections. Further, the incremental patterns are arranged with a phase difference corresponding to the waste of the unit pattern with respect to the absolute pattern.

The detection unit 20 includes eight photodiodes 21a, 21b to 24a, 24b constituting a photodiode array as an absolute signal detector, and a single photodiode 25 as an incremental signal detector. , shine light from above the code plate 11, and photodiode on the bottom side of the code plate 11.
21a, 21b ~ 24a, 24b
The absolute pattern of the track 13 is detected by the photodiode 25, and the incremental pattern of the track 15 is detected by the photodiode 25. In this case, the transmitted light is "0".
”, and the light shielding is set to [1].

FIG. 2 shows an example of a circuit of the signal processing section 30 for processing the detection outputs of the photodiodes 21a to 24b and 25.

That is, the detection outputs of the photodiodes 21a, 21b to 24a, 24b as absolute signal detectors are outputted to amplifiers 31a, 31b to 34a, 34b, respectively.
After being amplified by comparators 41a, 41b to 44a
, 44b, the pulse train 71a is made up of a rectangular wave signal.

71b to 74a, 74b, and tristate buffer circuits 51a, 5 forming the signal selection circuit 50, respectively.
1b to 54a and 54b are manually operated.

On the other hand, the detection output from the photodiode 25 as an incremental signal detector is similarly shaped into a square wave via an amplifier 35 and a comparator 45, and is converted into a binary signal 75.
It is inputted to the control input terminal of each of the tristate buffer 7 circuits 51a, 51b to 54a, 54b of the signal selection circuit 50 as a signal selection circuit. As a result, when the binary signal 75 from the comparator 45 is at a low level, the tristate buffer 7
Circuits 51a, 52a, 53a, 54a output pulse trains based on detection signals from photodiodes 21a, 22a, 23a, 24a to output terminals 61.62.63.64, and binary signal 75 from comparator 45 is at high level. When , the tri-state buffer circuits 51b, 52
b, 53b.

54b is the photodiode 21b, 22b, 23b, 2
The pulse train based on the detection signal by 4b is output to the output terminal 61,
Output to 62, 63, and 64.

FIG. 3 is a waveform diagram showing the relationship between the output waveform of each comparator and the final output signal.
, b are comparators 41a, 42a, and 43a when the binary signal 75 is at a low level.

The photodiode 21a is output from the photodiode 44a.

Pulse train 71 based on detection outputs of 22a, 23a, and 24a
a, 72a, 73a, and 74a are selected as the final output, and conversely, when the binary signal 75 is at a high level, the comparator 4
This means that the pulse trains 71b, 72b, 73b, 74b based on the detection outputs of the photodiodes 21b, 22b, 23b, 24b outputted from 1b, 42b, 43b, 44b are selected as the final output, and regarding the final output, The parallel code of the selected pulse train is expressed in hexadecimal.

The phase relationship between the absolute No. 13 and the incremental signal is as follows: photodiodes 21a, 22a, 23a
, 24a, pulse trains 71a, 72a, 7
The photodiodes 21b, 22b, 2 are arranged so that the rising and falling timings of the photodiodes 3a and 74a are approximately in the middle of the pulse width of the binary signal 75 when the binary signal 75 is at a low level.
Pulse trains 71b and 72b based on the detection outputs of 3b and 24b
.

The rising and falling timings of the signals 73b and 74b are arranged to be approximately at the midpoint of the high-level pulse width of the binary signal 75, so that the selected output signal has an absolute signal pulse train. The uncertain parts around the rise and fall of the square wave are no longer included,
This prevents incorrect content from being read. Selection of such phase difference timing is based on the absolute pattern track 13 and the photodiode arrays 21a to 2 for its detection.
This can be easily realized by appropriately setting the phase difference in the arrangement of the combination of the track 15 of the incremental pattern and the photodiode 25 for detecting the track 15 of the incremental pattern for the combination of 4b.

The absolute pattern of this embodiment is a 16-division so-called full period array of N=4 bits as described above, and as shown in FIG. The four adjacent photodiodes 2
1 ab, 22ab, 23ab, and 24ab are relatively shifted by the pitch of one set, the code 18 with the same rO, IJ combination over the entire length of the code plate 11 is created in the four adjacent sets. Absolute pattern arrangement on track 13 to avoid noise (absolute coat)
is defined, and as mentioned above, this is rooooI
ol 100111101J.

Therefore, output terminal 61 is 2°, 62 is 2', 63 is 22
By assigning 64 to 23, a 4-bit absolute signal is obtained, and FIG. 3 shows the hexadecimal numbers corresponding to each absolute signal as the final signal.

In this way, by switching and outputting the binary signal using the incremental tH signal so as to alternately and complementarily conceal the unstable regions near the rising and falling edges of the paired absolute signal, it is possible to always output a stable absolute position. A signal is extracted and an immediate output is obtained when the power is turned on.

Although the numbers in the final signal obtained as described above are not arranged in order, it may be converted into a desired number sequence by a suitable converting means such as a ROM in actual use.

There are various absolute pattern arrangements other than the above-mentioned 16-division arrangement, and the arrangement is determined as follows.

That is, when the number of bits is small, it may be performed sequentially by trial and error, but when the number of points in focus is large, it is necessary to perform calculations using a computer.

To explain the above-mentioned case of 4 bits, for example, since there is always a case where each bit is "0", first we have four consecutive "0"s ro, 0, 0 . Think about O.J. If there are five consecutive [0's], the same combination will occur, so 'O
I think that ``rl'' always comes after four ``'' in a row. In this way, either r01 or "l" is added one after another, and when the bits are shifted one bit at a time in groups of four, combinations with the same contents do not occur.

The results of the computer calculations are shown in FIGS. 5(a), (b), (c), and (d).

FIG. 5(a) shows the absolute code for 5 bits, that is, N=5, and FIG. 5(b) shows the absolute code for 6 bits, that is, N=5.
This is the absolute code when =6, and is shown in Figure 5 (C
) is the absolute coat for 8 bits, that is, N=8, and FIG. 5(C) is for 10 bits, that is, N=8.
This is the absolute code for the case of 10.

The absolute coat in Figures 5(b),(c),(d) is
The last bit of a row is connected to the first bit of the next (lower) row to form a series.

When these absolute coats shown in Figure 5 are used in a rotary encoder, the last bit in the bottom row is the first bit.
Connect to the first bit of the line so that it continues like an end.

In the example shown in Fig. 5, the code arrangement is used when each set of photodiodes of the absolute signal detector is arranged at a pitch corresponding to % of the minimum reading unit of the absolute pattern, but as the pattern becomes finer, the photodiodes If the array bits cannot be arranged any finer due to dimensional limitations, by devising the absolute pattern code arrangement, it is possible to arrange the photodiodes at intervals of, for example, every other bit of the code arrangement. As such an example, FIG. 6 shows an absolute code when N=10.

In this case, since N=10, ten sets of two photodiodes are arranged in each set at 1-bit intervals.

Of course, it is possible to appropriately determine the absolute code for other intervals as well; - For boat fishing, it is possible to create an absolute code for an integral multiple of the array pitch between each string of the photodiode of the absolute signal detector. .

Furthermore, each absolute code in Fig. 5 is shown in terms of the number of divisions: (a) is N=5 and 32 divisions, (b) is N = 6 and 64 divisions, (C) is N = 8 and 256 divisions, and (d) is 1 when N=10
024 scale, however, in actual use, a number of scales with good separation is often required instead of such a half-baked number of scales. Nos. 7 to 12 show examples of such absolute coats with well-defined scale numbers.

That is, Fig. 7 shows an example of 360 scale marks suitable for reading the angle once with a rotary encoder, etc., and Fig. 8 shows an example of scale a.
iooo example, Figure 9 is an example with 2 ooo graduations, Figure 10 is an example with 5000 graduations, and Figures 1A to IIC are 10 graduations.
000 example, Figure 12AN12F is an example of a 21600 scale suitable for 1 minute angle reading.

According to the absolute code as exemplified above,
Since an absolute pattern can be realized with one track, it is possible to obtain an absolute encoder whose magnitude is almost the same as that of a so-called incremental encoder.

The present invention is applicable to both a linear encoder for reading a linear position and a rotary encoder for reading a rotational position. Needless to say, this method can be applied to the absolute encoder of this method.

[Effects of the Invention] As described above, according to the present invention, an absolute position signal can be obtained immediately when the electric field is turned on, and the absolute pattern of the code plate can be detected by multiple sets of detectors on the truck. When reading, the uncertain areas around the rising and falling edges of each set of absolute signals are alternately and complementarily concealed and retrieved using incremental signals. The goal is to provide an absolute encoder with high resolution.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing the configuration of an optical absolute encoder according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of the f33 processing path for processing the detection output of the detector, and FIG. 4(a) is a schematic plan view of the code plate of the optical absolute encoder according to the previous proposal; FIG.
b) is also for processing the detection output of the detector (
A circuit diagram showing an example of the No. 3 processing circuit, Fig. 5 is an explanatory diagram showing some examples of an absolute L-coat for determining an absolute pattern to obtain an absolute signal with a different number of bits, and Fig. 6 is an explanatory diagram showing an example of an L-tocoat. Fig. 7 is an explanatory diagram showing the absolute code when the number of divisions is 360, and Fig. 8 is an illustration showing the absolute code when the number of divisions is t ooo. An explanatory diagram, Fig. 9 is an explanatory diagram showing the absolute code when the number of scales is 2000, Fig. 10 is an explanatory diagram showing the absolute code when the number of scales is 5000, and Fig. 11 is the combination arrangement of Figs. 11A-11C. 11A and 1180 are explanatory diagrams showing the absolute coat when the number of graduations is 10,000, and FIG. 12 is an explanatory diagram showing the combination arrangement of FIGS. 12A to 12F.
A2B, 12C, 12D, 12E, 12F figures have 2 scale marks.
16 is an explanatory diagram showing an absolute code in the case of 1600. FIG. (Explanation of codes of main parts) +1: Code plate +3 track (absolute) 15 track (incremental) 21ab to 24ab: Photodiode array 25 track
Photodiode 31ab ~: 14ab: Amplifier 41ab ~ 44ab: 51ab ~ 54ab 61 ~ 64: Comparator signal selection circuit tri-state rose output terminal F circuit

Claims (1)

[Scope of Claims] An absolute encoder comprising a code plate having an absolute pattern track and an incremental pattern track substantially parallel to each other, and a detector movable relative to the code plate in the longitudinal direction of the track, A plurality of sets of absolutes that read the absolute pattern and generate a first signal of a corresponding pulse train and a second signal having a phase difference corresponding to 1/2 of the pulse width of the minimum read unit pulse in the pulse train. a signal detector, which reads the incremental pattern and generates a binary signal having a repetition period approximately equal to the pulse width of the minimum read unit pulse in the pulse train, at a rate approximately 1/4 of the repetition period with respect to the unit pulse; a detector for incremental signals generated by a phase difference; and a detector for extracting only the first signal from each set of absolute signal detectors when the binary signal takes one value; An absolute encoder comprising: signal selection means for extracting only the second signal when the second signal is detected.