JPH0658627B2 - Electronics - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field of the Present Invention> The present invention relates to an electronic device that controls a drive unit based on a device operating program stored in a storage device.

<Prior Art and Problems> With the recent development of microcomputers, an increasing number of microcomputers control the operation of various devices.

As shown in FIG. 4, this type of electronic device is configured such that an arithmetic processing unit 2 (hereinafter, referred to as a CPU) controls a drive unit 3 in accordance with a device operating program stored in advance in a memory 1. Has been done.

This memory 1 is a non-volatile, read-only memory,
A device in which a program for operating the device is fixedly stored in advance has been used conventionally.

However, since the memory contents of this type of memory are retained even after being removed from the device, there is a risk that the memory contents are easily known. If the program for operating the device is leaked, it may cause serious damage to a person engaged in the manufacture and sale of the device.

That is, the device operating program stored in the memory 1 is copied to manufacture and sell a completely equivalent device,
There is a possibility that the device operating program has been misused to misuse the device.

Therefore, conventionally, the memory 1 and the CPU 2 are covered with the resin 4 so that the names and terminals of the CPU 2 and the memory 1 cannot be seen from the outside to prevent leakage of the device operating program stored in the memory 1. ing.

However, as described above, if the memory 1 is covered with the resin 4, the device operating program cannot be changed, and all the control units including the CPU 2 must be replaced, which is extremely inconvenient. It was an economy.

For this reason, as shown in FIG.
There is a memory device that allows the memory 1 to be replaced by connecting it to the CPU 2 via a socket (or a socket), but this causes the device operating program of the memory 1 to be easily read.

Even in this case, if the old memory 1 that has been replaced is wasted and there are many devices that need to exchange device operating programs, a large number of exchange memories must be carried to perform the memory exchange operation. However, there is a problem that the work efficiency is reduced due to complexity.

In order to solve this, for example, JP-A-61-2535
Like the missile guidance device shown in No. 39, program data input from an external device is stored in a readable / writable memory (RAM), and the device is controlled based on the program data stored in this memory. It is also conceivable to configure so that.

According to this technology, the control of the device can be changed by a program input from the outside, which eliminates the need to replace the memory when changing the program and facilitates the change work. By changing the above, there is a very high risk that the device will be illegally used.

Also, in the case of a readable / writable memory that requires constant power supply to retain data, the retained data may change due to an abnormal change in the power supply, etc. It may be in a state.

<Object of the present invention> The present invention has been made in order to solve the above problems, there is very little risk that the contents of the device operating program is easily known from outside, or is illegally changed,
Moreover, it is an object of the present invention to provide an electronic device capable of easily and inexpensively changing a regular program and preventing an abnormal operation of the device due to a change in a stored program.

<One Embodiment of the Present Invention> One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a program diagram showing an example of an electronic device and a program transmission device to which the present invention is applied.

In the figure, 21 indicates an electronic device and 22 indicates an electronic device 2.
The drive unit 1 and the control unit 23 control the drive unit 22.

Reference numeral 24 is a RAM having a sufficient address space for storing a device operating program for controlling the electronic device 21, and 25 is program data input from the outside of the electronic device 21 to the RAM 24. This is a first ROM in which a reception program for sequentially storing at a predetermined address is stored in advance.

The RAM 24 is backed up by a battery (not shown) to retain the stored contents even when the electronic device 21 is powered off.

26 is a first ROM for inputting program data
RA sequentially according to the receiving program stored in 25.
It is a first CPU that controls the drive unit 22 in accordance with a device operating program that is stored in a predetermined address of M24 and is stored in the RAM 24.

Reference numeral 27 denotes a data receiving unit for receiving program data from the outside of the electronic device 21, and a reception connector 28 connectable from the outside of the electronic device 21 and a program from the outside input in series from the reception connector 28. The serial / parallel converter 29 is composed of a shift register or the like for converting data into parallel program data having a bit number corresponding to the first CPU 26.

It should be noted that this control unit 23, except for the receiving connector 28,
Since it is covered with resin and it is impossible to identify and electrically contact each circuit from the outside, the power line etc. is disconnected by the brute force to remove this resin for illegal purposes. Then, the contents stored in the RAM 24 are volatilized.

On the other hand, 31 is a program transmission device for transmitting the device operating program to the electronic device 21 side, and 32 is
A device operating program to be stored on the electronic device 21 side is stored in a predetermined address space, and a transmitting program for sequentially outputting the program data of the device operating program to the electronic device 21 side is stored from an initial address. It is the second ROM.

The device operating program is preconfigured so that the result of binary addition of all the program data becomes "0".

Reference numeral 33 denotes a second CPU that sequentially outputs the program data of the apparatus operating program in parallel according to the transmission program stored in the second ROM 32, and 34 denotes the second CPU.
Is a data transmission unit for converting program data output in parallel from the CPU 33 into serial program data and transmitting the serial program data to the electronic device 21 side.

The data sending unit 34 includes a parallel / serial converter 35 including a shift register for converting parallel program data output from the second CPU 33 into serial series program data, and a serial / serial converter 35. In order to send the program data to the data receiving section 27 of the electronic device 21, the transmission connector 36 is formed so as to be connectable to the receiving connector 28 of the data receiving section 27.

In addition to the serial line S for transmitting the program data from the program transmission device 1, all of the program data input from the direct line S is sent to the electronic connector 21 through the transmission connector 36 and the reception connector 28. RAM2
In order to inform the program transmission device 31 side that the data is stored in No. 4, from the electronic device 11 side to the program transmission device 31 side.
A control line C for sending a store end signal E to the side,
A power supply line B for supplying power to the program transmission device 31 from the electronic device 21 side is provided.

Further, the program transmitting device 31 is provided with a display 37, and the display 37 displays a display indicating "transmitting" while the device operating program is being transmitted to the electronic device 21 side. When the transmission of the application program is completed, a display indicating "end of transmission" is displayed, and when the program data from the program transmission device 31 is securely stored on the electronic device 21 side, "store completed" is displayed. Is displayed, or when the program data is not stored securely, the alarm is displayed on the first CP.
Display according to the display signal from U33.

Next, a program transmission processing procedure of the program transmission device 31 and a program reception processing procedure of the electronic device 21 will be described with reference to the flowcharts of FIGS. 2 and 3.

FIG. 2 is a flow chart showing the control procedure of the transmission program of the program transmission device 31, and when the transmission connector 36 of the program transmission device 31 is first connected to the reception connector 28 of the electronic device 21, the electronic device 21 side is connected. The power is supplied to the program transmission device 31 from the power transmission line B (a).

The second CP of the program transmitter 31 to which power is supplied
U33 is initialized to execute the transmission program of the second ROM 32 (b).

Next, according to the transmission program from the second CPU 33, the start code is the data transmission unit 34 and the serial line S.
Is sent to the electronic device 21 side via (c).

Next, the final address value L of the device operating program in the second ROM 32 is read and sent to the electronic device 21 side (d), and the initial address value of the device operating program is A.
(E).

Next, a display indicating "program is being sent" is displayed on the display 37 (f), and the program data of the device operating program having the address value A is sent to the electronic device 21 via the data sending unit 34 and the serial line S. Sent to the side (g).

The address value A is compared with the final address value L of the device operating program (h), the address value A is incremented by 1 until the final address value L and the final address value L become equal (i), and the device operating program is operated. The program is sequentially transmitted as program data in the order of addresses.

When the address value A of the device operating program becomes equal to the final address value L (that is, when all the program data of the device operating program is sent to the electronic device 11 side), the transmission of the device operating program ends. Is displayed on the display 37 (j), and the timer set to the predetermined time T is started (k).

When the store end signal E is input from the electronic device 11 side through the control line C within this predetermined time T (l), a display indicating "store end" is displayed on the display 37 (m), and the program The transmission operation ends.

When the store end signal E is not input from the electronic device 21 side and the predetermined time T has passed (n), the electronic device 21
On the side, an alarm display indicating that the device operating program has not been reliably stored is displayed on the display 37 (o).

Next, the first ROM 25 of the control unit 23 on the electronic device 21 side
The control means of the reception program stored in FIG. 3 will be described with reference to FIG.

First, when power is supplied to the electronic device 21, the first CP
U26 is initialized to execute the reception program stored in the first ROM 25 (a ').

When the receiving program is executed, the timer set at the predetermined time T'starts (b ').

Within this predetermined time T ′, the transmission connector 36 of the data transmission unit 34 of the program transmission device 31 and the reception connector 28 of the electronic device 21 side are connected, and the program transmission device 3
When the start code from 1 is input (c '), the final address value L of the device operation program that is subsequently input is L.
Is received and the address value L is temporarily stored in a predetermined address of the RAM 24 where the device operating program is not stored (d ').

Next, the initial address value of the device operating program to be newly stored in the RAM 24 is substituted into D (e '), and the program data initially sent from the program transmitting device 31 is stored in the address of D ( f ').

Every time the program data is received from the program transmission device 31, the address value D is incremented by 1 (h ') until the address value D becomes equal to the final address value L (g'). The addresses are sequentially stored.

In this way, when all the program data from the program transmitting device 31 is stored in the predetermined address space of the RAM 24 as a new device operating program, RA
The write end code is stored in a predetermined address of M24 (address where the device operating program is not stored) (i ').

Next, in order to check the program stored in the RAM 24, all program data stored in a predetermined address space of the RAM 24 are binary-added (k '), and if the addition result is "0" (l ′), It is determined whether the write end code is correctly stored in the predetermined address of the RAM 24 (m ′).

When the write end code is correctly stored, the store end signal E is sent from the electronic device 21 to the program transmission device 31 via the control circuit C (n ').

After sending the store end signal E, the receiving program stored in the first ROM 25 jumps to the initial address of the device operating program newly stored in the RAM 24 (q ') and is stored in the RAM 24. The operation of the drive unit 22 is controlled in accordance with the new device operating program (p ').

When the timer starts (b ') and the start code from the program transmitting device 31 cannot be received within the predetermined time T' (j '), the device operating program previously stored in the RAM 24 is detected. It is checked in the same manner as described above (l ', m'), and the drive unit 22 of the electronic device 21 is drive-controlled (o ', p') according to the previously stored device operating program.

If the binary addition values of all the program data of the device operating program stored in the RAM 24 are not “0”, or if the write end code is not stored in the predetermined address of the RAM 24, the electronic device 21 Since the control operation is stopped (q '), it is necessary to input the device operating program again from the program transmitting device 31 or check the control unit of the electronic device 21.

As described above, the new device operating program is stored in the RAM 24 of the electronic device 21 from the program transmitting device 31, and after the store end signal E from the electronic device 21 side is confirmed by the program transmitting device 31, this program is executed. The connection between the transmission connector 36 of the data transmission unit 34 of the transmission device 31 and the reception connector 28 of the electronic device 21 is released, and the work of changing the device operating program is completed.

In this embodiment, when the power of the electronic device 21 is turned on, the program transmitting device 31 transmits a new device operating program to change the device operating program of the electronic device 21. 21 in operation (3rd
(P ')), when the start code from the program transmission device 31 is received, the second CPU 26 is interrupt-controlled and (p') to (d ') in the flowchart of FIG.
It is also possible to jump to and change the program for operating the device.

<Other Embodiments of the Present Invention> In the above embodiment, the data sending unit 34 is connected in parallel
A serial converter 35 is provided to transmit serial program data, and the serial / parallel converter 2 on the electronic device 21 side is provided.
In FIG. 9, the program data is converted into parallel program data, but a parallel buffer or the like may be used instead of the converters 18 and 35 to transmit and receive the program data as parallel data.

<Effects of the Present Invention> As described above, the electronic device of the present invention is hermetically sealed by the sealing means made of resin so that at least the RAM, the ROM, and the CPU are integrated into a control unit.
Since this control unit is provided with the timer means, the start code judging means, the data storing means, the program checking means, the program executing means and the control prohibiting means, the CPU powers on after the device operating program is stored in the RAM. The drive unit is controlled based on the program for operating the device, which is automatically stored by the operation, and the program data is not output to the control unit other than the resin-sealed control unit.
When there is no fear that the contents of the device operating program will be known while the electronic device is operating, and when it is desired to change the contents of the device operating program, a new program for operating the device will be sent from the dedicated program transmitter via the connector. There is an advantage that the program can be easily changed by transmitting the program data of.

In addition, even if an attempt is made to rewrite the device operating program by inputting fake program data from the outside through a connector for the purpose of fraudulent operation or to know the contents of the program itself, the timer means starts for a predetermined time. Without knowing the contents of each of the check items of the code and program checking means and their combination, it is impossible to access the RAM within a predetermined time, and these means can sufficiently function as a key and keep confidentiality. It has extremely high reliability above.

Further, when an attempt is made to remove the resin or the like that seals the control unit with an unreasonable force that cuts off the power supply to the RAM, the device stored in the RAM without the person being aware of it. There is no danger that the operating program will be volatilized and the contents of the device operating program will be known.

Further, even if the resin is removed properly, a memory in which an incorrect program is recorded is attached instead of the regular RAM, or the program stored in the RAM is changed due to an abnormality in the power supply or the like. Even if it happens, in the electronic device of the present invention, the RAM is provided by the timer means and the program check means each time power is supplied.
Since the program is executed after it is checked whether or not the device operating program stored in is normal, the control by such an illegal or abnormal program is prohibited, and the device abnormally operates. There is no fear.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are flowcharts showing a control procedure of a control unit of the embodiment. 4 and 5 are block diagrams showing the configuration of a conventional electronic device. 21 ... Electronic device, 22 ... Drive unit, 23 ... Control unit,
24 ... RAM, 25 ... first ROM, 26 ... first
CPU, 27 ... Data receiving part, 28 ... Receiving connector, 29 ... Serial / parallel converter, 31 ... Program transmitting device, 32 ... Second ROM, 33 ... Second CPU, 34 ... ... Data transmission unit, 35 ... Parallel / serial converter, 36 ... Transmission connector.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Morifumi Okugawa 1-2356 Takeshi, Yokosuka City, Kanagawa Prefecture NTT Communications Corp. (72) Inventor Tatsujiro Kawakita 1-2356 Takeshi Yokosuka City, Kanagawa Japan Telegraph and Telephone Corporation, Complex Communication Laboratory (56) References JP-A-61-253539 (JP, A)

Claims (1)

[Claims] 1. A drive unit controlled based on an apparatus operating program, a RAM for storing the apparatus operating program, and a receiving program for receiving program data input via a connector. A ROM stored therein and program data based on the reception program stored in the ROM are received, stored in the RAM as a device operating program, and based on the device operating program stored in the RAM. A CPU for controlling the drive unit, and at least the RAM, ROM,
And a sealing unit made of resin or the like that seals a CPU into a control unit and seals the control unit, wherein the control unit has the following means a to f based on the reception program. An electronic device which operates so as to have. a. Timer means that operates for a predetermined time after power is supplied b. Start code determination means for determining whether or not the received program data has a start code for changing the program while the timer means is operating. C. Data storing means for sequentially storing the received program data in a predetermined address area of the RAM when the start code determining means determines that there is a start code. D. Program check means for determining whether or not the program data stored in the RAM is normal after the operation of the timer means is completed. E. When the program check means determines that the program is normal, the program data stored in the RAM is regarded as a device operating program, and the program executing means f controls the drive unit based on the device operating program. ． By the program check means, the RAM
When it is determined that the device operating program stored in the device is not normal, a control inhibiting means for inhibiting the control of the drive unit by the device operating program.