JPH065786A - Fabrication of semiconductor device - Google Patents
Fabrication of semiconductor deviceInfo
- Publication number
- JPH065786A JPH065786A JP4187492A JP18749292A JPH065786A JP H065786 A JPH065786 A JP H065786A JP 4187492 A JP4187492 A JP 4187492A JP 18749292 A JP18749292 A JP 18749292A JP H065786 A JPH065786 A JP H065786A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- resistor
- forming
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に多結晶シリコンで形成された抵抗(以下、単
に抵抗と称する)の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a resistor formed of polycrystalline silicon (hereinafter, simply referred to as a resistor).
【0002】[0002]
【従来の技術】従来のこの種の抵抗の製造方法の一例を
図3に示す。先ず、図3(a)のように、シリコン基板
1上に下地絶縁膜2を形成し、全面に多結晶シリコン膜
4を形成する。この多結晶シリコン膜4に、ヒ素やリン
等の不純物をイオン注入を用いてドープした後、図3
(b)のように、フォトリソグラフィを用いて多結晶シ
リコン膜4を選択的にエッチングし、抵抗10を形成す
る。次いで、図3(c)のように、抵抗10を保護する
為の保護用絶縁膜6を形成した後、フォトリソグラフィ
を用いて抵抗コンタクトホール7を開口し、最後に抵抗
コンタクトホール7を通して抵抗10に接続される電極
8を形成する。2. Description of the Related Art An example of a conventional method of manufacturing a resistor of this type is shown in FIG. First, as shown in FIG. 3A, a base insulating film 2 is formed on a silicon substrate 1, and a polycrystalline silicon film 4 is formed on the entire surface. After doping the polycrystalline silicon film 4 with impurities such as arsenic and phosphorus by ion implantation,
As shown in (b), the polycrystalline silicon film 4 is selectively etched by photolithography to form the resistor 10. Next, as shown in FIG. 3C, after forming a protective insulating film 6 for protecting the resistance 10, the resistance contact hole 7 is opened by photolithography, and finally the resistance 10 is passed through the resistance contact hole 7. Forming an electrode 8 connected to.
【0003】又、他の製造方法を図4に示す。図4
(a)のように、シリコン基板1上に下地絶縁膜2を形
成し、かつ多結晶シリコン膜で抵抗10を形成した後、
図4(b)のように、全面にSOG(Spin On Glass )
11を塗布し、 900℃前後で熱処理した後、多結晶シリ
コンの抵抗10の表面が露出するまでSOG11をエッ
チングバックする。これにより、SOG11は抵抗10
の側壁部分のみに残され、抵抗10のこの部分の段差を
緩和する。次いで、図4(c)のように、全面に保護用
絶縁膜6を形成し、かつ抵抗コンタクトホール7及び電
極8を形成する。Another manufacturing method is shown in FIG. Figure 4
As shown in (a), after forming the base insulating film 2 on the silicon substrate 1 and forming the resistor 10 with the polycrystalline silicon film,
As shown in Fig. 4 (b), SOG (Spin On Glass) is formed on the entire surface.
11 is applied and heat-treated at about 900 ° C., and then SOG 11 is etched back until the surface of the polycrystalline silicon resistor 10 is exposed. As a result, the SOG 11 has a resistance of 10
Is left only on the side wall of the resistor 10 and alleviates the step of this part of the resistor 10. Next, as shown in FIG. 4C, a protective insulating film 6 is formed on the entire surface, and a resistance contact hole 7 and an electrode 8 are formed.
【0004】[0004]
【発明が解決しようとする課題】上述した従来の抵抗の
製造方法のうち、図3に示した方法では、抵抗10を形
成するための多結晶シリコン膜4の膜厚が、保護用絶縁
膜6の膜厚に比べて厚い場合には、抵抗10の側壁部分
の角度が急峻になる。このため、電極形成工程におい
て、スパッタ法を用いて全面にアルミニウム,金等の金
属膜を形成し、抵抗コンタクトホール上以外の金属膜を
反応性イオンエッチングにより選択的に除去する場合
に、多結晶シリコンの抵抗の側壁部分に金属が残ってし
まい、ショート不良等の原因になるという問題点があっ
た。Among the conventional methods of manufacturing a resistor described above, in the method shown in FIG. 3, the thickness of the polycrystalline silicon film 4 for forming the resistor 10 is the same as that of the protective insulating film 6. If it is thicker than the film thickness of, the angle of the side wall portion of the resistor 10 becomes steep. For this reason, in the electrode formation step, when a metal film of aluminum, gold, or the like is formed on the entire surface by sputtering and the metal film other than on the resistance contact hole is selectively removed by reactive ion etching, the polycrystalline film is used. There is a problem that metal remains on the side wall portion of the silicon resistor, which causes a short circuit defect or the like.
【0005】又、図4に示した方法では、SOG11を
抵抗10の側壁部分に残してその段差を緩和しているた
め、前記したような金属が残るという問題が解消できる
が、SOGの処理に際しては高温で熱処理を行う必要が
ある為、例えばバイポーラICの場合には、既に形成さ
れているベース拡散層の不純物濃度プロファイルに悪影
響を与え、トランジスタの特性を悪化させるという問題
点があった。本発明の目的は、抵抗の側壁部分の段差を
緩和する一方で高温による熱処理を不要にした半導体装
置の製造方法を提供することにある。Further, in the method shown in FIG. 4, since the SOG 11 is left on the side wall portion of the resistor 10 to mitigate the step, the problem of metal remaining as described above can be solved, but in the processing of SOG. Since it is necessary to perform heat treatment at a high temperature, for example, in the case of a bipolar IC, there is a problem that it adversely affects the impurity concentration profile of the already formed base diffusion layer and deteriorates the characteristics of the transistor. It is an object of the present invention to provide a method of manufacturing a semiconductor device that alleviates the step difference on the side wall portion of the resistor and does not require heat treatment at high temperature.
【0006】[0006]
【課題を解決するための手段】本発明は、半導体基板上
に第1の絶縁膜を形成し、かつこの上に第1の絶縁膜と
エッチング選択性のある第2の絶縁膜を形成する工程
と、抵抗を形成する部分の第2の絶縁膜を選択的にエッ
チング除去する工程と、全面に多結晶シリコン膜を形成
し、これに不純物を導入して所要の導電性を持たせる工
程と、抵抗を形成する部分の多結晶シリコン膜上にマス
クを形成し、このマスクを用いて多結晶シリコン膜を選
択的にエッチング除去する工程とを含む。According to the present invention, a step of forming a first insulating film on a semiconductor substrate, and forming a second insulating film having etching selectivity with the first insulating film on the first insulating film And a step of selectively etching away the second insulating film where a resistor is formed, a step of forming a polycrystalline silicon film on the entire surface, and introducing impurities into the polycrystalline silicon film to give a required conductivity. A step of forming a mask on the portion of the polycrystalline silicon film where the resistance is to be formed, and using the mask to selectively remove the polycrystalline silicon film by etching.
【0007】[0007]
【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の第1実施例を製造工程順に示す断面
図である。先ず、図1(a)のように、シリコン基板1
上に下地絶縁膜としての第1の絶縁膜2と、この第1の
絶縁膜とはエッチングの選択性のある第2の絶縁膜3を
形成する。そして、この第2の絶縁膜3に対してフォト
リソグラフィ技術による選択エッチングを行い、多結晶
シリコンの抵抗を形成する部分のみ第2の絶縁膜3をエ
ッチングする。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a first embodiment of the present invention in the order of manufacturing steps. First, as shown in FIG. 1A, the silicon substrate 1
A first insulating film 2 as a base insulating film and a second insulating film 3 having etching selectivity with respect to the first insulating film are formed thereover. Then, the second insulating film 3 is selectively etched by a photolithography technique, and the second insulating film 3 is etched only in a portion where a resistance of polycrystalline silicon is formed.
【0008】次に、図1(b)のように、全面に第2の
絶縁膜3と同程度の厚さ(1000Å〜3000Å)の多結晶シ
リコン膜4を成長させ、かつこれにヒ素,リン等の不純
物をイオン注入を用いてドープする。更に、その上にフ
ォトレジスト5を塗布する。そして、前記第2の絶縁膜
3の選択エッチングに用いたマスクを再度利用し、第2
の絶縁膜3をエッチング除去した領域、即ち抵抗を形成
する領域上にフォトレジスト5を選択的に残す。Next, as shown in FIG. 1 (b), a polycrystalline silicon film 4 having the same thickness (1000Å to 3000Å) as the second insulating film 3 is grown on the entire surface, and arsenic and phosphorus are deposited on the polycrystalline silicon film 4. Etc. are doped using ion implantation. Further, a photoresist 5 is applied on it. Then, the mask used for the selective etching of the second insulating film 3 is reused to
The photoresist 5 is selectively left on the region where the insulating film 3 is removed by etching, that is, on the region where the resistor is formed.
【0009】次いで、図1(c)のように、残されたフ
ォトレジスト5をマスクにして第1の絶縁膜2が露出す
るまで多結晶シリコン膜4を等方性エッチングし、抵抗
10を形成する。その後、フォトレジスト5を除去す
る。これにより、形成された抵抗10は、等方性エッチ
ングの為にフォトレジスト5の端部付近もサイドエッチ
ングによりエッチングされ、結果として抵抗の断面形状
は第2の絶縁膜3と略同じ平面の膜状に形成される。そ
の後、図1(d)のように、全面に抵抗保護用の絶縁膜
6を形成し、抵抗コンタクトホール7を開口した後、抵
抗コンタクトホール7を通して抵抗10に接続される電
極8を形成する。Next, as shown in FIG. 1C, the polycrystalline silicon film 4 is isotropically etched by using the remaining photoresist 5 as a mask until the first insulating film 2 is exposed to form a resistor 10. To do. Then, the photoresist 5 is removed. As a result, the formed resistor 10 is also etched by side etching near the edges of the photoresist 5 for isotropic etching, and as a result, the cross-sectional shape of the resistor is a film having substantially the same plane as the second insulating film 3. Formed into a shape. Thereafter, as shown in FIG. 1D, an insulating film 6 for resistance protection is formed on the entire surface, a resistance contact hole 7 is opened, and then an electrode 8 connected to the resistance 10 through the resistance contact hole 7 is formed.
【0010】したがって、この製造方法によれば、多結
晶シリコン膜4で形成される抵抗10は第2の絶縁膜3
のエッチングされた領域に形成されるため、その側壁は
同程度の厚さの第2の絶縁膜3でカバーされる。このた
め、抵抗10の側壁部分における段差は殆ど解消され、
それに起因する抵抗側壁部の金属残りによるショート不
良等を防止できる効果がある。Therefore, according to this manufacturing method, the resistor 10 formed of the polycrystalline silicon film 4 has the second insulating film 3
Since it is formed in the etched region, the side wall thereof is covered with the second insulating film 3 having the same thickness. Therefore, the step on the side wall of the resistor 10 is almost eliminated,
There is an effect of preventing a short circuit defect or the like due to the metal remaining on the side wall of the resistor resulting from this.
【0011】図2は本発明の第2実施例を製造工程順に
示す断面図である。先ず、図2(a)のように、前記第
1実施例と同様にしてシリコン基板1上に第1の絶縁膜
2と第2の絶縁膜3を形成し、かつ抵抗を形成する部分
の第2の絶縁膜3を選択的にエッチングし、多結晶シリ
コンの膜4の形成とイオン注入を行う。次に、図2
(b)のように、第2の絶縁膜3の端部から若干寸法、
ここでは 500〜1000Å程度よりも内側の領域に多結晶シ
リコン膜4をカバーするフォトレジスト5を形成する。
続いて、多結晶シリコン膜4の膜厚の1/3程度を反応
性イオンエッチングにより異方性エッチングする。更
に、図2(c)のように、残りの多結晶シリコン膜4を
等方性エッチングにより除去する。その後、フォトレジ
スト5を除去する。FIG. 2 is a sectional view showing a second embodiment of the present invention in the order of manufacturing steps. First, as shown in FIG. 2A, the first insulating film 2 and the second insulating film 3 are formed on the silicon substrate 1 in the same manner as in the first embodiment, and the first portion of the portion where the resistance is formed is formed. The second insulating film 3 is selectively etched to form a polycrystalline silicon film 4 and perform ion implantation. Next, FIG.
As shown in (b), some dimensions from the end of the second insulating film 3
Here, a photoresist 5 covering the polycrystalline silicon film 4 is formed in a region inside about 500 to 1000 Å.
Subsequently, about 1/3 of the film thickness of the polycrystalline silicon film 4 is anisotropically etched by reactive ion etching. Further, as shown in FIG. 2C, the remaining polycrystalline silicon film 4 is removed by isotropic etching. Then, the photoresist 5 is removed.
【0012】最後に、図2(d)のように、第1実施例
と同様にして抵抗保護用絶縁膜6及び電極8を形成す
る。この実施例では、第2の絶縁膜3とフォトレジスト
5との距離、或いは多結晶シリコン膜4に対して異方エ
ッチングをする割合を調整することにより、多結晶シリ
コン上に残される突起9による段差をも低減する効果が
ある。Finally, as shown in FIG. 2D, the insulation film 6 for resistance protection and the electrode 8 are formed in the same manner as in the first embodiment. In this embodiment, by adjusting the distance between the second insulating film 3 and the photoresist 5 or the ratio of anisotropic etching with respect to the polycrystalline silicon film 4, the protrusion 9 left on the polycrystalline silicon is adjusted. It is also effective in reducing steps.
【0013】[0013]
【発明の効果】以上説明したように、第1の絶縁膜上に
形成した第2の絶縁膜の抵抗を形成する部分を選択的に
エッチングし、この上に多結晶シリコン膜を成長させた
後、抵抗部分以外の多結晶シリコン膜を選択的にエッチ
ングすることにより、第2の絶縁膜のエッチングされた
部分に残された多結晶シリコン膜を抵抗として構成する
ことができる。これにより、抵抗の側壁部分を第2の絶
縁膜でカバーでき、側壁部分における段差を解消し、こ
れに起因する金属残りによるショート不良等を防止でき
る効果がある。又、高温の工程が不要となるため、トラ
ンジスタの特性が悪化されることもない。As described above, after the resistance forming portion of the second insulating film formed on the first insulating film is selectively etched, a polycrystalline silicon film is grown on this portion. By selectively etching the polycrystalline silicon film other than the resistive portion, the polycrystalline silicon film left in the etched portion of the second insulating film can be configured as a resistor. As a result, the side wall portion of the resistor can be covered with the second insulating film, the step at the side wall portion can be eliminated, and there is an effect that a short circuit defect or the like due to metal residue caused by this can be prevented. Further, since the high temperature process is not required, the characteristics of the transistor are not deteriorated.
【図1】本発明の第1実施例を製造工程順に示す断面図
である。FIG. 1 is a sectional view showing a first embodiment of the present invention in the order of manufacturing steps.
【図2】本発明の第2実施例を製造工程順に示す断面図
である。FIG. 2 is a sectional view showing a second embodiment of the present invention in the order of manufacturing steps.
【図3】従来の第1の方法を製造工程順に示す断面図で
ある。FIG. 3 is a cross-sectional view showing the first conventional method in the order of manufacturing steps.
【図4】従来の第2の方法を製造工程順に示す断面図で
ある。FIG. 4 is a cross-sectional view showing a second conventional method in the order of manufacturing steps.
1 シリコン基板 2 第1の絶縁膜 3 第2の絶縁膜 4 多結晶シリコン膜 5 フォトレジスト 6 保護用絶縁膜 10 抵抗 1 Silicon Substrate 2 First Insulating Film 3 Second Insulating Film 4 Polycrystalline Silicon Film 5 Photoresist 6 Protective Insulating Film 10 Resistor
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成5年3月2日[Submission date] March 2, 1993
【手続補正1】[Procedure Amendment 1]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】全図[Correction target item name] All drawings
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図3】 [Figure 3]
【図4】 [Figure 4]
【図1】 [Figure 1]
【図2】 [Fig. 2]
Claims (1)
る半導体装置において、半導体基板上に第1の絶縁膜を
形成し、かつこの上に第1の絶縁膜とエッチング選択性
のある第2の絶縁膜を形成する工程と、抵抗を形成する
部分の第2の絶縁膜を選択的にエッチング除去する工程
と、全面に多結晶シリコン膜を形成し、これに不純物を
導入して所要の導電性を持たせる工程と、抵抗を形成す
る部分の多結晶シリコン膜上にマスクを形成し、このマ
スクを用いて多結晶シリコン膜を選択的にエッチング除
去する工程とを含み、前記第2の絶縁膜がエッチングさ
れた部分に残された多結晶シリコン膜を抵抗として構成
することを特徴とする半導体装置の製造方法。1. In a semiconductor device having a resistance formed of polycrystalline silicon, a first insulating film is formed on a semiconductor substrate, and a second insulating film having etching selectivity with the first insulating film is formed on the first insulating film. A step of forming an insulating film, a step of selectively etching away the second insulating film in a portion where a resistance is formed, a polycrystalline silicon film is formed on the entire surface, and impurities are introduced into the polycrystalline silicon film to obtain a desired conductivity. And a step of forming a mask on a portion of the polycrystalline silicon film where a resistor is to be formed, and using the mask to selectively etch away the polycrystalline silicon film. A method of manufacturing a semiconductor device, comprising: forming a polycrystalline silicon film left in an etched portion as a resistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4187492A JPH065786A (en) | 1992-06-22 | 1992-06-22 | Fabrication of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4187492A JPH065786A (en) | 1992-06-22 | 1992-06-22 | Fabrication of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH065786A true JPH065786A (en) | 1994-01-14 |
Family
ID=16207014
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4187492A Pending JPH065786A (en) | 1992-06-22 | 1992-06-22 | Fabrication of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH065786A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008270333A (en) * | 2007-04-17 | 2008-11-06 | Sony Corp | Semiconductor device and its manufacturing method |
-
1992
- 1992-06-22 JP JP4187492A patent/JPH065786A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008270333A (en) * | 2007-04-17 | 2008-11-06 | Sony Corp | Semiconductor device and its manufacturing method |
JP4600417B2 (en) * | 2007-04-17 | 2010-12-15 | ソニー株式会社 | Manufacturing method of semiconductor device |
US7858484B2 (en) | 2007-04-17 | 2010-12-28 | Sony Corporation | Semiconductor device and method for producing the same |
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