JPH0656575B2 - Processor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing device, and more particularly to a high-speed arithmetic processing device having a regular cell array structure and suitable for an LSI.

2. Description of the Related Art Conventionally, regarding a high-speed multiplier, for example, the Institute of Electronics and Communication Engineers, Journal, Vol.j66-D, No.6 (1983), pages 683 to 690.
Page, and regarding high-speed dividers, IEICE Transactions, Vol.J67-D, No4 (1984) No. 4
Discussed on pages 50-457. These are arithmetic units that execute multiplication or division by a combinational circuit by using a redundant binary representation, which is a type of signed digit representation (SD representation), for internal calculation, and in terms of calculation processing time and regular array structure. Although it is superior to other arithmetic units, no consideration was given to practical use such as reduction of the number of elements and area, realization with a MOS circuit, and the like.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In the above-mentioned conventional technology, with regard to a high-speed arithmetic unit, multiplication and division are performed by using a redundant binary representation in which each digit of an internal arithmetic number is represented by each element of {-1, 0, 1}. A method of doing is proposed. However, to represent one digit of an internal operation number using 2 bits,
Since the same logical expression is used for all the digits, there is a problem in that the number of stages of the circuit increases and the high speed decreases when the number of digits of the operation increases.

An object of the present invention is to improve the above-mentioned conventional problems, and to provide an arithmetic processing unit that can be easily mounted on an LSI by realizing an arithmetic unit with a combinational circuit having a small number of elements.

Means for Solving the Problems The above object is achieved by appropriately using different logical expressions depending on the digits when one digit of the internal operation number of the arithmetic processing unit is represented by a plurality of bits.

Action When using a signed digit representation for internal operation, that is, each digit of the internal operation number is {-1, 0, 1}, {-2,-
1,0,1,2} or {-N, ...- 1,0,1, ...
When represented by any element such as ... N}, a plurality of means can be considered to represent each element. For example, each digit {−1,0,1} in the redundant binary representation can be represented by 2 bits, and six types of signals (I ₊ , I ₀ ,
I ₋ , Ia, Is, In) can be expressed by using appropriate two.

Here, In is a logical negation of I ₊ , Ia is I ₀ , and Is is a logical negation of I ₋ , but for convenience in assembling the logic, they are treated as different signals. Table 2 shows a part of the logical expression that represents {-1, 0, 1} using the two signals in Table 1.

In order to represent each digit of the internal operation number of the signed digit expression, by properly using the plurality of logical expressions depending on the digit, the amount of hardware can be significantly reduced and the operation can be performed at high speed. .

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

In particular, in the present embodiment, the redundant shift binary expression is used for the internal operation, and in the subtraction shift type divider that divides the normalized n-digit unsigned binary fraction, the one digit of the quotient is determined. The case where different digit representation methods are used for the upper 3 digits of the partial remainder and the digits after the 4th digit used in FIG.

The arithmetic shift type division method can be generally expressed by the following recurrence formula.

^{R (j + 1) = r} × R (j) -q j × D ............ (1) where, j is the index of the recurrence formula, r is the radix, D is the divisor, _{q j}
Is the j-th quotient after the decimal point, r × R ^(j) is the partial dividend before determining q _j , and R ^{(j + 1)} is the partial remainder after determining q _j . Therefore, a combination circuit can be realized by providing a cell for determining the quotient q _j for each index j of the recurrence formula and a cell for determining each digit of the partial remainder R ^{(j + 1)} .

FIG. 1 is a block diagram showing the configuration of an apparatus according to an embodiment of the present invention. Blocks 101 and 141 are partial quotient decision cells,
Blocks 102 to 106, 142 to 146 are partial remainder decision cells. The signals y ₁ 91, y ₂ 92, y ₃ 93 are respectively 0. The _{first, second, and third} decimal places of the divisor D normalized to the form y ₁ y ₂ y ₃ ... Y _n . Also the signal +2 bit signal _q j representing the decimal point j th quotient _{q j,} a _{q j-} inverted signal. signal Is the most significant digit of the partial remainder R ^(j) , Is the second digit of R ^(j) , Is the third digit of R ^(j) as r ^j _3a 128, r ^j _3s 1
29 is the fourth digit, r ^j _4a 130, r ^j _4s 131
Is a signal representing the fifth digit or its inverted signal. Also the signal Is a signal representing the upper 5 digits of the partial remainder R ^{(j + 1)} , like the signals 121 to 131. Table 3 shows a logical expression of each of the above signals.

In this embodiment, since the radix r = 2, (1) formula is ^{R (j + 1) = 2} × R (j) -q j × D ......... (2) , and the quotient determined satisfy the following conditions To do so.

| R ^{(j + 1)} | <D ……………… (3) From this condition, the quotient q _j is the upper 3 digits of the partial remainder R ^(j) [r ₀
^j . According to the value of r ₁ ^j r ₂ ^j ] _SD2 , it is determined as follows.

However, it is shown that [] _SD2 is a redundant binary expression. If 2-bit signals q _{j +} and q _j− are used to represent each element of {−1, 0, 1}, it can be easily determined by the following logical expression.

In the above equation, · is the logical product (AND), + is the logical wheel (OR), _Represents the logical negation of r ^j ₀₊ , r ^j ₀₋ , r ^j ₁₊ , r ^j ₁₋ , respectively. Also, However, in the logical formula, these are treated separately.
FIG. 2 shows partial quotient decision cells 101 and 14 in FIG.
2 is a circuit diagram showing a configuration example of No. 1 of FIG. In the figure, gate 21
1, 222 are AND-NOR composite gates, 212, 22
Reference numeral 1 is an OR-NAND composite gate, and 231 is an inverter circuit.

Further, the partial remainder R ^{(j + 1)} after the quotient q _{j is} determined is determined by the following recurrence formula.

R ^{(j + 1)} = 2 × R ^(j) + D ^(j) ………… (7) Where is -1 Represents the logical negation of y _i .

This is [0. The fact that the sign of y ₁ y ₂ ... Y _n ] ₂ can be inverted by taking the complement of 2 is used. Further, 2 × R ^(j) can be obtained by shifting R ^(j) to the left by one digit. However, [...] ₂ indicates that it is expressed in binary.

In the addition of the redundant binary number and the binary number, the intermediate carry and the intermediate sum are determined according to the rules shown in Table 4.

As a result, carry can be prevented from propagating only one digit at most, and parallel addition by the combination circuit can be performed in a constant time regardless of the number of digits of the operation number. Hereinafter, the addition of the redundant binary number and the binary number is performed according to the above addition rule.

At this time, the i-th digit d _i ^j , the intermediate carry c ^j _i and the intermediate sum s ^j _i of D ^(j) in the recurrence formula (7) can be determined by the following logical formula.

The final sum r _i ^{j + 1} is a 2-bit signal represented by r ^{j + 1} _is = s _i ^j + c ^j _{i + 1} ... (12) r _ia ^{j + 1} = s _i ^j c _{i + 1} ^j ... (13) Given in. In the above equation, is an exclusive OR (EX-OR). By using the 2-bit signals r _a and r _s , the configuration of the circuit required for determining s _i and c _i is simplified. For example, · s _I , s
_i similar signal r in the case of the quotient determined decision _+, r _- the result with the following formulas be used, the number of transistors and the number of gate stages needed for the determination of s _i is increased.

3 is a circuit diagram showing an example of the configuration of the partial remainder decision cells 105, 106 ..., And 145, 146 ... After the fourth digit in FIG. Gates 311 and 32 in the figure
1, 351 is an OR-NAND composite gate, 322 is an exclusive OR circuit, and 341 is a NAND gate. Also, r
_{i + 1s} ^j 301, r ^j _{i + 1a} 302 is a table or a 2-bit signal representing the partial remainder r _{i + 1} ^j , y _i 303 is the divisor of the i-th digit after the decimal point, Its inverted signal, Is the inverted signal of carry c ^j _i to the upper digit, Is an inverted signal of carry c ^j _{i + 1} from the lower order, d ^j _i 312
Is a 1-bit signal representing the i-th digit after the decimal point of the addend D ^(j) ,
s ^j _i 323 is a 1-bit signal representing an intermediate sum at the i-th digit after the decimal point. Also, r ^{j + 1} _is 361 and r ^{j + 1}
_ia 362 is a 2-bit signal representing the _i- th digit r ^{j + 1} _i after the decimal point of the partial remainder R ^{(j + 1)} after the quotient q _j is determined.

FIG. 4 shows the partial remainder third digit decision cell 1 in FIG.
It is a circuit diagram which shows one structural example of 04,144. The third digit of the partial remainder is a 2-bit signal ▲ r ^{j + 1} ₂₊ ▼ 155 and Or And r ^{j + 1} _2a 157, and two logical expressions are used. However, Is a signal similar to ▲ r ^{j + 1} _2s ▼. The first expression is used to determine the quotient a _{j + 1} and the partial remainder uppermost r ₀ ^{j + 2 in} the next stage, and the second expression is the next partial partial remainder second position ▲ r ^{j + 2} ₁ ▼ determination. Used for. However, in the present embodiment, in order to simplify the circuit configuration, only ^one of the 2-bit signals r ^{j + 1} _2a is used to determine the second partial remainder. ▲ r ₂₊ ^{j + 1} ▼ and Can be determined by the following logical formula.

Here, ▲ s ^j ₂ ▼ is the intermediate sum determined by the equation (10), and ▲ c ^j ₃ ▼ is the intermediate carry determined by the equation (11). In the figure, gates 411, 421, 422, 442
451 is the same as that in FIG. 3, gate 441 is NOR
It is a gate.

The 2-bit signal representing the second digit r ₁ ^{j + 1} of the partial remainder is determined by the logical expressions (16) and (17).

FIG. 5 shows the partial remainder second digit decision cell 1 in FIG.
It is a circuit diagram which shows one structural example of 03,143. In the figure, a gate 511 is an exclusive NOR circuit, 521 is a NOR gate, and 522 is a NAND gate.

Partial remainder R ^{(j + 1)} of the upper r ▲ ^{j + 1} ₀ ▼ the uppermost, leftmost digit [r ₀ ^j of like the quotient preceding partial remainder R ^(j). r
₁ ^j r ₂ ^j ] _SD2 is determined by the following logical expression so that the carry of higher digits does not occur.

FIG. 6 is a partial remainder uppermost decision cell 10 in FIG.
It is a circuit diagram which shows one structural example of 2,142. In the figure, gates 601 and 604 are NOR gates, and 602 and 603 are N gates.
AND gate, 611 is an OR-NAND gate, 612
Is an AND-NOR gate, and 621 and 622 are inverters.

In the above embodiment, the number of gate stages of the circuit is reduced by using different logical expressions to represent each digit by the upper 3 digits of the partial remainder used to determine the 1 digit of the quotient and the digits after it. Yes, you can divide at high speed. The exclusive OR and exclusive NOR circuits in this embodiment are the composite gate NAN.
It can be realized by a combination of D and NOR, or can be realized by 6 transistors by using a transfer gate. Also, by combining a NAND with an inverter, NO
It is known that it can be easily replaced by R, constructed by a combination of compound gate NAND or NOR, or vice versa.

EFFECTS OF THE INVENTION According to the present invention, in an arithmetic processing device that uses a signed digit expression for internal operation, when each digit of a certain operation number is represented, the number of elements is reduced by using an appropriate logical expression depending on the digit. The calculation speed can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an arithmetic processing unit in one embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of the configuration of a partial quotient decision cell in FIG. 1, and FIG. 3 is a partial diagram in FIG. FIG. 4 is a circuit diagram showing an example of the configuration of a decision cell of the fourth digit after the remainder, FIG. 4 is a circuit diagram showing an example of the configuration of the decision cell of the third residue of the partial remainder shown in FIG. 1, and FIG. FIG. 6 is a circuit diagram showing an example of the configuration of a partial remainder second digit determination cell.
It is a circuit diagram which shows one structural example of the partial remainder most significant digit determination cell in a figure. 101, 141 ... Partial quotient decision cells, 102 to 106,
142-146 ... Partial remainder decision cells, 211, 22
2,612 ... AND-NOR compound gate, 212,2
21,311,321,351,411,421,45
1,611 ... OR-NAND composite gate, 322, 4
22 ... Exclusive OR circuit, 341, 442, 522, 6
02,603 ... NAND gate, 231, 621, 6
22 ... Inverter circuit, 441, 521, 601 and 6
04 ... NOR gate, 511 ... Exclusive NOR circuit.

Front page continuation (72) Inventor Tamotsu Nishiyama 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) Reference JP-A-63-49836 (JP, A)

Claims (3)

[Claims] 1. An arithmetic processing unit that uses a number of signed digits, each digit being a positive, 0, or negative value, for internal arithmetic, wherein one digit of a predetermined internal arithmetic number uses a plurality of bits. , The arithmetic processing unit that uses a different logical expression depending on the digit. 2. When performing division by using the number of signed digits in an internal operation, it is used to determine one digit of a quotient when one digit of a partial remainder, which is a signed digit expression, is represented by a plurality of bits. The arithmetic processing unit according to claim 1, wherein different logical expressions are used for the upper several digits and the subsequent digits in the partial remainder. 3. The arithmetic processing unit according to claim 2, wherein the next-stage partial remainder most significant digit is determined by a signal similar to the signal used to determine one digit of the quotient.