JPH0656395B2 - Jitter Analyzer - Google Patents

Description

The present invention relates to a jitter analyzer, and more particularly to a jitter analyzer suitable for continuously collecting a jitter distribution at high speed.

(Prior Art) A jitter analyzer used for adjustment of an optical pickup of a compact disc player and the like is known, which measures a jitter distribution.

The jitter analyzer extracts, for example, only the pulse within the predetermined range width from the pulse train in the time window, converts the pulse width of the extracted pulse into a voltage corresponding to the pulse width by the time / voltage converter, and converts this converted voltage. Analog signal level corresponding to jitter. This analog signal level corresponds to the pulse width, and the extracted pulse width fluctuates. When this fluctuation width is small, the pulse width distribution curve is as shown in FIG. 5 (a). When the jitter is small and the fluctuation of the pulse width is large, the pulse width distribution curve is as shown in FIG. 5 (b), and the jitter is large.

In a conventional jitter analyzer, as shown in FIG. 6, an analog signal input as an electric signal is supplied to an A / D converter and converted into digital data. The measurement / CPU switch 2 is switched by the Q output of the flip-flop 3, and when the Q output is logic "0", it is switched to the measurement side and the digital data converted by the A / D converter 1 is stored in the jitter memory 4. Supply as address data. The data stored in the corresponding address is read from the jitter memory 4 to which the address data is supplied and preset in the jitter counter 5. Subsequent to this preset, the count value of the jitter counter 5 is incremented by "+1", and then the stored contents of the corresponding address of the jitter memory 4 is incremented by "+1". Therefore, in the jitter memory 4, the address corresponds to the jitter (pulse width), the stored content of the jitter memory 4 corresponds to the frequency, and the jitter histogram is stored equivalently.

The above measurement is repeated, and the A / D converter 1 is operated as described above.
When the storage content of the address corresponding to the analog signal level is incremented by "+1" for each input to the, and the value obtained by "+1" the storage content of any address causes the jitter counter 5 to overflow, the flip-flop is caused by the carry signal. 3
Q output is inverted to logic "1" and measured / CPU
The switching unit 2 is switched to the CPU side, all the stored contents of the jitter memory 4 are read out, the read data is processed by the CPU, and the stored contents of the jitter memory 4 are cleared after the processing is completed. Then flip-flop 3 is CP
When reset from the U side, the Q output of the flip-flop 3 is set to logic "0". The next measurement is started from this state.

(Problems to be Solved by the Invention) As described above, the conventional jitter analyzer shown in FIG.
As shown in (a), periods C ₁ , C ₂ , C ₃ , ... In which the contents of the jitter memory 4 are read from the CPU are required between the measurement periods a ₁ , a ₂ , a ₃ , .... That is, when the stored content of the jitter memory overflows, the jitter distribution measurement is temporarily terminated and switched to the CPU bus side. Until the CPU receives the stored content of the jitter memory, calculates, displays, and transfers data, etc. Since the next jitter distribution measurement cannot be performed, there is a problem that the measurement must be interrupted.

An object of the present invention is to provide a jitter analyzer capable of continuously measuring jitter distribution without interruption.

(Means for Solving the Problem) A jitter analyzer of the present invention is an A / D that converts an analog signal of a level corresponding to a pulse width into digital data.
A conversion unit, a plurality of storage units which are addressed by the output data from the A / D conversion unit during the jitter distribution measurement, and each time the addressing is performed, the stored content at the specified address is “+1”; The output data from the D / D conversion means is led to one storage means in the plurality of storage means as address data, and the address data from the data processing means is read out from the storage contents by another one in the plurality of storage means. A first switching means for leading to the storage means, a second switching means for leading to the data processing means the storage contents read from the storage means that has received the address data for reading from the data processing means, A When the end of the jitter distribution measurement by the storage means that receives the output data from the D / D conversion means as the address data is detected and detected, the first
And a switching control means for switching the second switching means, and the stored content read from the storage means in accordance with each address data is used as frequency data.

(Operation) The output data from the A / D conversion means is supplied as address data to one storage means of the plurality of storage means via the first switching means, and is stored at the designated address for each designation of the address data. The content is incremented by "+1". Therefore, the jitter distribution is stored in one storage unit of the plurality of storage units. On the other hand, the address data from the data processing means is supplied to the other one storage means of the plurality of storage means via the first switching means, and the storage content stored in the other one storage means is the designated address. Read according to the second
It is supplied as frequency data corresponding to the address designated by the data processing means via the switching means.

However, when the end of the jitter distribution measurement by the storage unit 1 is detected, the switching control unit switches the first and second switching units.

Therefore, the address data from the data processing means is supplied via the first switching means to the one storage means that has received the output data from the A / D conversion means as the address data and measured the jitter distribution. The stored content at the address corresponding to the address data is read out and supplied as frequency data to the data processing means via the second switching means. Further, the output data from the A / D conversion means is supplied as address data to the other one storage means via the first switching means, and every time the address is designated, the stored content at the designated address is "+1". Then, the frequency data is stored.

Since the reading of the stored contents and the measurement of the jitter distribution are performed in parallel as described above, it is not necessary to temporarily stop the jitter distribution measurement for reading the stored contents, and the continuous measurement can be performed.

(Examples) Hereinafter, the present invention will be described with reference to Examples.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, the same components as those of the conventional example of FIG. 6 are designated by the same reference numerals.

An analog signal converted into a voltage corresponding to the pulse width by a time / voltage converter (not shown) is supplied to the A / D converter 1 and converted into digital data. A / D converter 1
Is supplied to the address switcher 12, and switching with the address data from the CPU side supplied to the address switcher 12 is performed with the output of the flip-flop 18 for switching described later. 13 _A and 13 _B are jitter memories for storing the distribution frequency of jitter, 15 is a jitter memory switch for selecting read data from the jitter memories 13 _A , 13 _{B on} the measurement side of the jitter memories 13 _A , 13 _B , and 16 is Jitter memory switch 15
The jitter counter 17 detects an overflow when the read data output via the preset data is preset and incremented. Reference numeral 17 denotes that the count value data of the jitter counter 16 is returned to the measuring jitter memories 13 _A and 13 _B as write data. The data switcher 18 to be selected receives the overflow output of the jitter counter 16, that is, the carry signal as a clock, and latches the Q output, and the address switcher 12, the jitter memory switcher 15, the data switcher 17, and the memory described later. Control switching device 19
And a flip-flop for switching the read memory switching unit 20, 19 is a jitter memory 13 _A , 13
_A memory control switch for switching the control signal of _B to one of the measurement direct memory access (DMA) signal and the control signal from the CPU side, 20 is a switch for reading the data of the jitter memory 13 _A or 13 _{B on} the CPU side. It is a vessel. Reference numeral 10 is the measurement side of the jitter memories 13 _A and 13 _B , and the jitter counter is DMA.
A DMA signal input terminal for driving, 11 is a CPU bus group, 11 _a is a CPU control bus, and 11 _b
Is a CPU address bus, _11c is a CPU data bus, and 21 is a reset signal input terminal of the CPU.

Next, the operation of the present invention configured as described above will be described with reference to the timing chart shown in FIG. 2 and the flow chart shown in FIG.

When the power is turned on, a CPU reset signal is generated as shown in FIG. Flip-flop 18 is reset by the occurrence of CPU reset signal, Q output of the flip-flop 18 as shown in FIG. 2 (b) is a logic "0" (Step S _1). Then jitter memory 13 _A and 1
Storage content of 3 _B is cleared to all "0" (step _S 2). In FIG. 3, the right side of the broken line shows the flow on the CPU side, and the left side shows the measurement side shown in FIG.

Since the Q output of the flip-flop 18 becomes logic "0", the A / D converter 1
Digital data converted by the given as jitter in the memory 13 _A is given as address data (step S _3), to the address data the address data from the CPU address bus to the jitter memory 13 _B. This state is as shown in FIG. 2 (c).

When the converted digital data by the A / D converter 1 is given to the jitter memory 13 _A as address data, a signal for reading the data of the jitter memory 13 _A is given to the jitter memory 13 _A from the DMA signal input terminal 10 in synchronization with this. . Therefore, in this state, the jitter memory 13
_A output from the A / D converter 1 is supplied as address data, and DMA signal input terminal 10 is supplied with a read signal from the jitter memory 13 second view corresponding address in the memory of the data is read out of _A ( d) It is supplied to the jitter counter 16 via the jitter memory switcher 15. The selection data by the jitter memory switch 15 is as shown in FIG. 2 (f). Here, the DMA signal input terminal 1
0 load signal is provided to the jitter counter 16 from data stored in the corresponding address of a jitter memory 13 _A is loaded into the jitter counter 16 Second diagram (g)].
Then, from the DMA signal input terminal 10 to the jitter counter 16
An increment signal for increasing the count value of "1" is given, and the count value of the jitter counter 16 is incremented by "+1".

On the other hand, the jitter memory 13 _B is supplied with address data from the CPU address bus via the address selector 12 as address data, through the memory control switch 19 from the CPU control bus in synchronization with the supply of address data The read signal is the jitter memory 1
The data supplied to the 3 _B and read from the jitter memory 13 _B is sent to the CPU via the read memory switching unit 20.
It is output to the data bus _11C . Data reading of jitter memory 13 _B are as listed in FIG. 2 (e), CP
The data sent to the U data bus 11 _C is shown in FIG. 2 (m).
And the switching state by the read memory 20 is as shown in FIG. 2 (n).

When the count value of the above-mentioned jitter counter 16 is incremented by “+1”, the DMA signal input terminal 10 is continuously operated to start the jitter memory 1
The write signal is given to 3 _A , and the jitter counter 16
Is stored in the corresponding address. The output from the jitter counter 16, that is, the count value of the jitter counter is as shown in FIG. Thus data stored in the corresponding address of a jitter memory 13 _A is "+1" data to the data transferred to the jitter counter 16.

In this way, every time one input analog signal is supplied to the A / D converter 1, the stored content of the corresponding address becomes "+".
1 ". By repeating this, the data stored in the address where the address designation is maximum becomes maximum. Therefore, when the count value of the jitter counter 16 is increased by" +1 "by the above repetition, the jitter counter 16
Overflows. If the jitter counter 16 is an 8-bit counter, [“OFF (H)” + 1] = [2
55 → 256], overflow occurs, and the carry signal is supplied from the jitter counter 16 to the flip-flop 18 as a clock pulse. This state is shown in Figure 2 (h).
(Step S ₄ ).

Q output switches to logic "1" from a logical "0" of the flip-flop 18 receives the carry signal from the jitter counter 16 (step _S 5). This state is as shown in FIG. 2 (b).

Since the Q output of the flip-flop 18 becomes logic "1", the address switch 12 and the jitter memory switch 1
5, data switch 17, memory control switch 19
And the read memory switch 20 is switched [second
Figure (c), (f), (i), (j), (n) ], the jitter memory 13b is measured side, the jitter memory 13 _A is to be connected to the CPU side. 2 (k) shows the DMA signal input terminal 10
The signal supplied to the.

Here, instead of the jitter memory 13 _A , the jitter memory 13
_{Since B} was switched to the measurement side, the jitter memory 1
Similar to the case where 3 _A is on the measurement side, the jitter distribution, that is, frequency data corresponding to the level of the analog signal is collected and stored in the jitter memory 13 _B (steps S ₆ to S ₈ ).

Meanwhile, the CPU side after the execution step _{S 2,} Q output of the flip-flop 18 is monitoring to become logic "1" (step _S 9). This corresponds to the jitter memory 13 _A side is checked completion of being measured side,
Step S ₉ will be waiting for the interrupt when the Q output of the flip-flop 18 becomes logic "1" from a logical "0". The jitter memory 13 _A When this interrupt occurs the state in which data of the jitter distribution is stored, the jitter memory 13 _A following step S ₉
Stored contents of taken in CPU (step S _10), the stored contents of the incorporated jitter memory 13 _A is processed, displayed, forwarded, etc. (step S _11). This display provides a histogram-like display. Following step S ₁₁ , the stored contents of the jitter memory 13 _A are cleared in preparation for the next measurement (step S ₁₂ ), and wait until the measurement by the jitter memory 13 _B currently on the measurement side is completed (step S ₁₂ ). ₁₃ ). When the measurement by the jitter memory 13 _B ends, act as if the measurement side by the jitter memory 13 _A as described above has been completed (step S ₁₄ ~S _16).
Hereinafter, it is similarly repeated.

Accordingly, the jitter analyzer in this embodiment, as shown in FIG. 4 (b), following the completion of the measurement by the jitter memory 13 _A (period a ₁ in the _{measurement),} the measurement by the jitter memory 13 _B is performed ( During the measurement period b ₁ ), the measurement by the jitter memory 13 _A is performed following the end of the measurement by the jitter memory 13 _B (measurement period a ₂ ).
After that, the measurement is continuously repeated without interruption. On the other hand, when the measurement by the jitter memory 13 _A is completed, the stored contents of the jitter memory 13 _A are read out in parallel with the measurement by the next jitter memory 13 _B (C ₁ , C ₂ ,
...), when the measurement by the jitter memory 13 _B was completed in parallel with the measurement by following the jitter memory 13 _A, the jitter memory 13 _B stores the contents is read out (C _11, C ₁₂₎ Ru.
Therefore, it is not necessary to interrupt the measurement of the jitter distribution as in the conventional case.

Furthermore, by increasing the number of jitter memories and the number of jitter memory switches, it is possible to increase the processing time and other margins on the CPU side, and measure jitter distribution at a higher speed and the number of bits of the jitter counter. It is possible to perform the accurate measurement with the increased value without being restricted by the CPU side.

Further, the end of the measurement of the jitter distribution may be switched not by the overflow of the jitter counter but by the end of the measurement at a constant time by a timer or the like.

(Effects of the Invention) As described above, according to the present invention, a plurality of storage means are provided, and the jitter distribution in the plurality of storage means is started from the time when one storage means in the plurality of storage means starts the jitter distribution measurement. Since the storage content of the other one storage unit that has finished the measurement is read, the storage content reading and the jitter distribution measurement are performed in parallel, and the jitter distribution measurement is temporarily performed for reading the storage content. It is not necessary to stop, and jitter distribution can be measured continuously. Furthermore, the processing time of the read memory contents by the data processing means does not affect the jitter measurement.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a timing chart for explaining the operation of the embodiment of the present invention. FIG. 3 is a flow chart for explaining the operation of one embodiment of the present invention. FIG. 4 (a) is a diagram for explaining the operation of the conventional example. FIG. 4 (b) is a diagram for explaining the operation of one embodiment of the present invention. FIG. 5 is a diagram showing the jitter distribution. FIG. 6 is a block diagram showing a configuration of a conventional example. 1 ... A / D converter, 12 ... Address switcher, 1
3 _A and 13 _B ... Jitter memory, 15 ... Jitter memory switch, 16 ... Jitter counter, 17 ... Data switch, 18 ... Flip-flop, 19 ... Memory control switch, 20 ... Read memory switch vessel.

Claims (1)

[Claims] 1. An A / D conversion means for converting an analog signal of a level corresponding to a pulse width into digital data, and addressing and output by output data from the A / D conversion means during measurement of jitter distribution. A plurality of storage means in which the storage content at the designated address is "+1" each time, and the output data from the A / D conversion means is led to one storage means in the plurality of storage means as address data, and First switching means for guiding the address data from the processing means to another one of the plurality of storage means for reading the stored contents, and storage means for receiving the address data for reading from the data processing means. Second switching means for guiding the storage contents read from the data processing means to the data processing means, and output data from the A / D conversion means as address data And a switching control means for switching the first and second switching means when the end of the jitter distribution measurement by the storing means is detected, and the stored content read out from the storing means in accordance with each address data is used as frequency data. A jitter analyzer that is characterized.