JPH0654950B2 - Vertical deflection circuit for CRT - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a vertical deflection circuit of a CRT, and in particular, extends the lower limit range of frequency characteristics of an exciting current supplied to a vertical deflection coil to a direct current with a single power source. CRT vertical deflection circuit.

[Prior Art] As shown in FIG. 5, a cathode K to which a video signal is applied is arranged in the CRT ₁ , and a first grid G ₁ and a second grid G ₂ are provided in front of the cathode K. , A third grid G ₃ is provided, and each grid voltage is supplied from a high voltage generating circuit (not shown). Further, the high voltage V _A is supplied to the anode 2 from this high voltage generating circuit.
Further, a horizontal deflection coil 3 and a vertical deflection coil 4 are wound around the outer circumference of the CRT 1, and each of the deflection coils 3 and 4 is synchronized with a horizontal synchronizing signal a and a vertical synchronizing signal b. It is driven by the exciting currents I _H and I _V output from 6.

Then, the electrons outputted from the cathode K, that is, the electron beam 7 is controlled by the first grid G ₁ , passes through the _second and third grids G ₂ , G _3, and is horizontally moved by the horizontal deflection coil 3 and the vertical deflection coil 4. After being deflected vertically,
The light is incident on the phosphor screen of the display screen 1a. Then, the fluorescent element in the portion irradiated with the electron beam 7 emits light.

FIG. 6 is a schematic configuration diagram of a vertical deflection circuit including the vertical deflection output circuit 6 and the vertical deflection coil 4. In the figure, 8 is an input terminal to which a vertical synchronizing signal b is input, and the vertical synchronizing signal b input from this input terminal 8 is input to a sawtooth wave generating circuit 9 formed of, for example, a blocking oscillator or a multivibrator. . The sawtooth wave generation circuit 9 generates a sawtooth wave signal c synchronized with the input vertical synchronizing signal b and sends it to the next amplifier 10. Power supply 1 for amplifier 10
1, the DC voltage V _CC is supplied, and the ground terminal is grounded. The output terminal of the amplifier 10 is connected to the vertical deflection coil 4 via the output capacitor 12 ( _CO ).
It is connected to the.

In such a vertical deflection circuit, the frequency _V of the vertical synchronizing signal b is 60 Hz in a general television set.
Therefore, the frequency component of the exciting current _IV flowing through the vertical deflection coil 4 during the display period is also relatively low. Therefore, the inductance component L _V of the vertical deflection coil 4 can be almost ignored,
The vertical deflection coil 4 is equivalently approximately 10
It can be regarded as a load resistance R _L having a resistance value of about Ω. On the other hand, during the vertical blanking period, the current value greatly changes in a short time, so the inductance component L _V and the resistance component R _V
And a series circuit of and becomes the load resistance R _{L. The} amplifier 10 to which the sawtooth wave signal c having a frequency of _V (= 60 Hz) is input, amplifies the sawtooth wave signal c and outputs it from the output terminal. Therefore, the exciting current I _V flows through the vertical deflection coil 4 in the illustrated direction via the output capacitor C _O. FIG. 7 is an output voltage waveform diagram at that time. That is, since the boost circuit is built in the amplifier 10, the output voltage V _O of the amplifier 10 is twice the DC voltage V _CC of the power supply 11 only during the vertical blanking period described above, as shown in the figure. It becomes a value. Therefore, the maximum value of the output voltage V _O is twice the voltage value (2V _CC ) of the DC voltage V _CC of the power supply 11.
Determined by.

[Problems to be Solved by the Invention] However, the vertical deflection circuit of the CRT configured as shown in FIG. 6 still has the following problems. That is, when the CRT 1 is incorporated in a general home-use television set, there is no particular problem, but the CRT 1 is incorporated in a CRT display device for a monitor such as a computer terminal.
In RT1, when the image corresponding to the input video signal is displayed on the display screen 1a as much as possible, and as necessary, as shown in FIG. 8, the image 13 is displayed with a margin on the display screen 1a. There is. In this case, the image 13 may not be accurately displayed at the center position of the display screen 1a, so it is necessary to move the image 13 in the vertical and horizontal directions to position it at the center. Vertical sync signal b
In order to move the screen in the vertical direction without changing the ratio of the front porch and the back porch, it is most effective to change the DC signal level of the entire output voltage V _O waveform shown in FIG. .

However, in the amplifier 10 shown in FIG. 6, the output (coupling) capacitor C _O to block the input and output signals galvanically, it needs to be interposed between the amplifier 10 and load (R _L) There is. The value of the output capacitor C _O is a considerably large value, for example, 2000 to 3000 μF. Therefore, the lower limit range of the frequency characteristic of the output voltage V _O is limited by the output capacitor C _O , and it is difficult to change the DC signal level of the entire output voltage V _O.

Further, when the large-capacity output capacitor C _O as described above is mounted on the printed circuit board, it is generally necessary to use an electrolytic capacitor, so that not only the vertical deflection circuit as a whole is increased in size but also its life is shortened. Shorter and less reliable.

The present invention has been made in view of such circumstances,
By connecting a pair of transistors with different junction structures between the power supply and ground, and connecting the ground side end of the vertical deflection coil to the connection point, the output capacitor of the amplifier can be removed with a simple configuration, and the vertical deflection coil A CRT that can expand the lower limit of the frequency characteristic of the excitation current to DC and realize a high-performance CRT display device that includes vertical movement of the displayed image.
It is an object of the present invention to provide a vertical deflection circuit of.

[Means for Solving the Problems] In order to solve the above problems, a vertical deflection circuit of a CRT according to the present invention supplies an amplifier for amplifying a sawtooth wave signal synchronized with a vertical synchronizing signal and a DC voltage to the amplifier. Power supply,
A vertical deflection coil, one end of which is connected to the output of the amplifier,
A first transistor inserted between the power supply and the other end of the vertical deflection coil, and a second transistor inserted between the other end of the vertical deflection coil and ground and having a reverse junction structure with the first transistor. And a voltage dividing resistor for supplying a base voltage to the bases of the first and second transistors, which is interposed between the power supply and the ground.

[Operation] With the CRT vertical deflection circuit configured as described above,
First and second transistors having different junction structures, such as pnp or npn, are serially inserted between the power supply and the ground with the emitters connected to each other. Further, a constant voltage obtained by dividing the DC voltage of the power source by a voltage dividing resistor is applied to the base of each transistor. Therefore, the transistors do not conduct at the same time, and the transistors that conduct according to the voltage applied to the emitter are replaced.

For example, when the output signal of the amplifier that amplifies the sawtooth wave signal is below a certain level, for example, the first transistor on the power supply side becomes conductive, and the power supply passes through the first transistor and the vertical deflection coil as a load. When a current flows into the output end of the amplifier and the output signal of the amplifier is above a certain level, for example, the second transistor on the ground side becomes conductive, and the output end of the amplifier passes through the vertical deflection coil and the second transistor. Current flows to the ground.

Then, since the direction of the exciting current flowing through the vertical deflection coil is reversed, the output voltage of the amplifier equivalently moves up and down around the ground potential, and the output capacitor can be removed.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a vertical deflection circuit of a CRT according to an embodiment. The same parts as those in FIG. 6 are designated by the same reference numerals.

The vertical synchronizing signal b input from the input terminal 8 is input to the sawtooth wave generation circuit 9. The sawtooth wave generation circuit 9 generates a sawtooth wave signal c synchronized with the input vertical synchronizing signal b and sends it to the next amplifier 21. The amplifier 21 is supplied with the DC voltage V _CC from the power supply 22, and the ground terminal is grounded. The output terminal of the amplifier 21 is equivalently connected to one end of the vertical deflection coil 4 which can be represented by the load resistance R _L. The other end of the vertical deflection coil 4 is np
It is connected to the emitter of the n-type first transistor 23 and to the emitter of the pnp-type second transistor 24. The collector of the first transistor 23 is connected to the power supply 22, and the collector of the second transistor 24 is grounded.

A pair of voltage dividing resistors 25 and 26 having the same resistance value R are inserted in series between the power source 22 and the ground, and the voltage dividing resistors 25 and 26 are connected in series.
The connection point P of 26 is the first and second transistors 23,
It is connected to each of the 24 bases. Therefore, the voltage at the connection point P is applied to the bases of the transistors 23 and 24.
1/2 (V _CC ) is applied.

Next, the operation of the vertical deflection circuit of the CRT thus configured will be described.

For example, frequency _V (= 60Hz) input from the input terminal 8
The vertical synchronizing signal b having the above is converted by the sawtooth wave generating circuit 9 into a sawtooth wave signal c which is synchronized with the vertical synchronizing signal b. The sawtooth wave signal c is amplified by the next amplifier 21. Therefore, the output voltage V _{O at} the output terminal of the amplifier 21 changes at the frequency _V (= 60 Hz) in response to the signal waveform of the sawtooth wave signal c.

When the output voltage V _O is lower than 1/2 (V _CC ), the base-emitter voltage V _{BE of} the first transistor 23 is high, so the collector current increases and the first transistor 23 becomes conductive. , Power supply 22 to first transistor 23
The exciting current I ₁ flows into the output terminal of the amplifier 21 via the vertical deflection coil 4. In this state,
The second transistor 24 does not conduct.

Next, when the output voltage V _O becomes higher than 1/2 (V _CC ), the base-emitter voltage V _{BE of} the first transistor 23 becomes negative and the first transistor is cut off, so that the exciting current I ₁ is cut off. On the contrary, when the base-emitter voltage V _BE of the second transistor 24 becomes negative, the second transistor 24 becomes conductive, and the output terminal of the amplifier 21 passes through the vertical deflection coil 4 and the second transistor 24. The exciting current I ₂ flows to the ground.

Thus, the direction of the excitation current I _V flowing through the vertical deflection coil 4, because the forward and reverse rotation by the value of the output voltage V _O, output voltage V _O of the amplifier 21 as viewed from the load resistor 4 side as shown in FIG. 2 In addition, it will fluctuate within a voltage range of 1/2 (V _CC ) above and below the ground potential (V = 0). Therefore, the output voltage V _O
At the ground potential, the exciting current I _V (= I ₁ + I ₂ ) does not flow in the vertical deflection coil 4 which is a load, so that the output capacitor C _O in FIG. 6 can be removed.

If the output capacitor C _O can be removed, the reduced frequency component is not blocked by this output capacitor, so the lower limit range of the frequency characteristics of the output voltage V _O can be expanded to DC, and the image linearity at the lower end of the screen is improved. Can be made. Further, by changing the offset voltage of the output voltage V _O , the exciting current I _V applied to the vertical deflection coil 4 is changed.
It is possible to change the overall current level. Therefore, as shown in FIG. 8, the image 1 on the display screen 1a is
You can easily move 3 up and down.

Further, since it is not necessary to use a large-capacity output capacitor C _O composed of an electrolytic capacitor, the vertical deflection circuit as a whole can be made small and lightweight, and an electrolytic capacitor having a short life is not used, so that the reliability is improved. The manufacturing cost can be reduced at the same time.

FIG. 3 is a circuit diagram showing a vertical deflection circuit of a CRT according to another embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals.

In this embodiment, one of the voltage dividing resistors 31 and 32 connected between the power source 22 and the ground is a variable resistor, and the variable resistor 3
1 and the voltage dividing resistor 32 between the three diodes 33a, 3a
3b and 33c are inserted in series in the forward direction. And
The connection point P ₁ between the variable resistor 31 and the diode 33a is the first
Connected to the base of the transistor 23 of
A connection point P ₂ between the diode 33c and the diode 33c is connected to the base of the second transistor 24. In the figure, 23a,
Reference numeral 24a is an emitter resistance for preventing thermal runaway of the transistors 23 and 24.

In the case of the CRT vertical deflection circuit having such a configuration, assuming that the forward voltage drop when the diodes 33a, 33b, and 33c are conductive is, for example, 0.6 V, each transistor 2
A potential difference of 1.8 V is generated between the bases 3 and 24. With this potential difference, the base of each transistor 23, 24
The dead band of about 1.2 V caused by the emitter-to-emitter voltage V _BE is compensated to prevent the waveform of the output voltage V _O waveform shown in FIG. 2 from being distorted when the signal level is close to the ground potential (± 0.6 V). ing.

Therefore, it is possible to obtain substantially the same effect as that of the embodiment shown in FIG.

Further, one of the voltage dividing resistors is a variable resistor 31 and the resistance value of the variable resistor 31 is changed to equivalently change the signal level of the output voltage V _O waveform shown in FIG. 2 to the ground potential (V = 0). Can be moved up and down with respect to. Therefore, it is not necessary to separately incorporate a signal level adjusting circuit in the amplifier 21, so that the circuit configuration can be further simplified.

FIG. 4 is a circuit diagram showing a vertical deflection circuit of a CRT according to still another embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals.

In this embodiment, the connection point P of the voltage dividing resistors 25 and 26 is
Switch 34 formed by analog switch between ground and ground
Is inserted. The switch 34 is closed by a switch control circuit (not shown) only during the vertical retrace period T _V in the vertical synchronizing signal b shown in FIG.

With the CRT vertical deflection circuit configured as described above,
As shown in FIG. 2, the output voltage V _O in the vertical vertical blanking interval T _V (-) will be instantaneous change from the level to the (+) level, the base of each of transistors 23 and 24 only the period T _V By forcibly setting the potential to the ground potential, it becomes possible to more rapidly change the level of the exciting current I _V that changes corresponding to the output voltage V _O.

Therefore, the same effect as that of the embodiment shown in FIG. 1 can be obtained, and the vertical retrace time can be further shortened.

As described above, according to the vertical deflection circuit of the CRT of the present invention, a pair of transistors having different junction structures are connected between the power supply and the ground, and the vertical deflection coil is grounded at the connection point between them. The side ends are connected. Therefore, the direction of the exciting current flowing in the vertical deflection coil can be reversed in accordance with the output voltage value of the amplifier, so that the output capacitor of the amplifier can be removed. Therefore, with a simple configuration, the lower limit range of the frequency characteristic of the exciting current of the vertical deflection coil can be expanded to DC, and a high-performance CRT display device including vertical movement of a display image can be realized with a single power source.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a schematic configuration of a vertical deflection circuit of a CRT according to an embodiment of the present invention, FIG. 2 is a time chart showing the operation of the circuit of the same embodiment, and FIGS. 3 and 4 show the present invention. 5 is a circuit diagram showing a vertical deflection circuit of a CRT according to another embodiment of FIG. 5, FIG. 5 is a schematic diagram showing a configuration of a general CRT, FIG. 6 is a circuit diagram showing a vertical deflection circuit of a conventional CRT, and FIG. Shows the output voltage waveform diagram in the conventional circuit, and FIG. 8 shows a general CRT.
It is a figure which shows the display screen of. DESCRIPTION OF SYMBOLS 1 ... CRT, 3 ... Horizontal deflection coil, 4 ... Vertical deflection coil, 7 ... Electron beam, 9 ... Sawtooth wave generation circuit, 21 ... Amplifier, 22 ... Power supply, 23 ... First transistor, 24 ...
Second transistors, 25, 26 ... Dividing resistors, 31 ... Variable resistors, 34 ... Switches.

Claims (1)

[Claims] 1. An amplifier (21) for amplifying a sawtooth wave signal synchronized with a vertical synchronizing signal, a power supply (22) for supplying a DC voltage to the amplifier, and a vertical terminal having one end connected to an output terminal of the amplifier. A deflection coil (4), a first transistor (23) interposed between the power source and the other end of the vertical deflection coil, and a first transistor (23) interposed between the other end of the vertical deflection coil and the ground, First
The second transistor (2
A vertical deflection circuit of a CRT, which is provided with 4) and a voltage dividing resistor (25, 26) interposed between the power source and the ground and for supplying a base voltage to the bases of the first and second transistors.