JP3321140B2 - Video display - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video display device, and more particularly to a video display device having a function of realizing a plurality of different raster dimensions. is there. BACKGROUND OF THE INVENTION Video display devices, such as television receivers and computer monitors, typically generate one or more electron beams and deflect these beams across a fluorescent display screen. Alternatively, it has a cathode ray tube that scans and draws a raster. This raster determines the size and shape of the observable area on the screen when a video signal is present. If the video display is to be used as a computer monitor, it is desirable that the monitor can be used with products of other computer manufacturers, or in combination with different types of computer devices made by the same manufacturer. Different types of computers may have different amounts of video information per horizontal scan line, or may generate different video signals that include different numbers of scan lines per field. For example, erase (blanking)
The ratio of effective video information to time period is different between video signals having different resolution characteristics. If the amplitude of the horizontal and vertical deflections is not selected according to the characteristics of the video signal, overscanning or underscanning of the video signal occurs on the raster. If the display screen is not fully utilized, or if overscanning occurs, loss of image information will occur. [0005] According to a feature of the SUMMARY OF invention, a deflection circuit for generating a horizontal deflection current, the horizontal deflection
Circuit to control the horizontal deflection current amplitude.
Adjusting means for adjusting the raster width of the image, and the adjusting means
A) vertical velocity for correcting horizontal deflection distortion
A parabolic signal; and b) adjusting the horizontal deflection current amplitude.
Based on both the DC bias level for the adjustment means
Means for controlling the horizontal deflection current based on the unique video
A plurality of binary signals representing a specific horizontal deflection amplitude according to the standard.
Receiving the digitally encoded signal
It responds to the information specifically represented in the encoded signal.
To generate one of the decoded output signals.
Decoding the digitally encoded signal in order to
Encoding means; and the one of the plurality of decoded output signals.
The DC bus is switched by a switchable current branch.
Set the ease level, which allows you to
Means for adjusting the raster width according to the case . FIG. 1 shows a horizontal deflection circuit 10, a vertical deflection circuit 11, and a cathode ray tube 12 according to an embodiment of the present invention.
Of the video display device including the above. The cathode ray tube 12
For example, a drive signal D is output from a video processing circuit (not shown).
And applies it to the electron gun assembly 18. The electron gun assembly 18 generates one or a plurality of electron beams that cause the fluorescent display screen 19 to emit light upon impact. The horizontal deflection circuit 10 includes, for example, a TDA 2595 type integrated circuit, and applies a switching signal to the base of the driving transistor 13. When the driving transistor 13 is switched (switched), the horizontal output transistor 14 is switched via the driving transformer 15. The collector of the horizontal output transistor 14 is connected to the primary winding 16 of the output transformer 17.
To a + 97V class B + voltage source. Transformer 17 is shown as having a secondary winding 20 that produces a high voltage, which is applied to a high voltage terminal or anode terminal 21 of cathode ray tube 12. The horizontal deflection circuit further includes a damper diode 22 and a retrace circuit.
It has capacitors 23, which work in a conventional manner, producing a retrace pulse across the terminals of the primary winding 16 when the transistor 14 is switched off. Further, by the switching of the horizontal output transistor 14, a horizontal deflection current flows through the terminal HH 'to the horizontal deflection winding 24 disposed at the neck of the cathode ray tube 12. The horizontal deflection winding 24 forms a part of a deflection yoke that deflects the electron beam from the electron gun assembly 18 to form a raster on the display screen 19. The horizontal deflection circuit also includes a linearity coil 25, an S-shaped capacitor 29, and a diode modulator circuit for correcting east-west or left / right pincushion raster distortion. This diode modulator comprises an inductor 27,
It has a damper diode 30, a modulator retrace capacitor 31, a modulator trace capacitor 26, and control transistors 32 and 33. The diode modulator performs a normal operation, modulates the horizontal deflection current in a parabolic manner at the vertical deflection frequency, and corrects the left and right pincushion distortion. The vertical deflection circuit 11 is, for example, a TDA 2
A type having a 653A type integrated circuit may be used, but a vertical deflection current flows through the vertical deflection winding 34 through the terminals V and V '. The deflection winding 34 is also provided on the neck of the cathode ray tube 12, and forms a part of the deflection yoke together with the horizontal deflection winding 24. The vertical deflection current sawtooth signal is supplied to the resistor 35.
And a capacitor 36 to form a vertical frequency parabolic signal, which is applied to the base of the control transistor 32 of the diode modulator circuit described above. In accordance with one aspect of the present invention, the illustrated video display includes a raster size selection circuit 40 having a decoder 41. The decoder 41 is exemplified as a CD4052B type separation (demultiplex) circuit manufactured by RC Corporation. The decoder 41 has input terminals A and B
And a binary signal is received. This signal determines one of four possible combinations of horizontal and vertical raster dimensions based on the binary input values. The desired horizontal and vertical dimensions are determined as follows. The sample signal generated across the resistor 39 and extracted from the vertical deflection current is applied to a terminal 43 of a decoder 41 via a manual raster height adjustment resistor 42.
The decoder 41 acts essentially as a switch and the terminal 43
Is applied to terminals 44 and 4 through a low resistance path of about 400 ohms in response to signals received at terminals A and B.
5, 46 or 47. For example,
In accordance with the decoding or demultiplexing logic of decoder 41, decoder 41 couples the signal at terminal 43 to terminal 46 with a high level signal representing a digital "1" at both terminals A and B. The terminal 46 is, for example, TDA 2
Vertical deflection circuit 11 which is pin 4 of the 653A type integrated circuit
Is connected via a resistor 50 to the feedback input terminal 48 of Terminals 44, 45 and 47 are also connected to the feedback input terminal 4 of the vertical deflection circuit 11 through respective resistors having different resistance values.
8. The value of the resistor contained between the movable arm of the manual raster height adjustment resistor 42 and the feedback terminal 48 in the return path determines the raster height, so that the decoder 41 is selected through terminals A and B and is selected. Acts to control the vertical raster size in response to the size signal. Since the decoder 41 for determining the selected raster height is included in the linearity and height feedback loop, any change in deflection current due to, for example, fluctuations in the power supply voltage will be all vertical deflection circuit 11
Is compensated by this feedback circuit. Therefore, the raster height is stably maintained when any height is selected. In accordance with yet another aspect of the present invention, to control the raster width, decoder 41 switches terminal 51 to terminals 52 and 5 in response to the levels of signals applied to terminals A and B.
One of 3, 54 and 55 is coupled through a low resistance path. The decoder 41, according to its operation logic, has a terminal 4
4, 45, 46 and 47 and terminals 52, 5
3, 54 and 55 are simultaneously selected and connected to the terminals 43 and 51, respectively.
Selectable combinations of terminals. Therefore, the selection of one of the terminals 52, 53, 54 and 55 is used to determine the horizontal raster width. As shown, the terminals 53, 5
4 and 55 are coupled to each other in a manner similar to terminals 45 and 47. In this way, a particular combination of raster height versus raster width is controlled. The raster width is determined as follows. Transistor 56 is connected to terminal 5 through voltage divider 60.
It has a base connected to two. Transistor 57
Are connected to terminals 53, 54 and 5 through a voltage divider 61.
5. The collectors of transistors 56 and 57 are coupled to each other via resistors 62 and 63, respectively, and to the base of diode modulator control transistor 32 through resistor 64. Since the terminal 51 is grounded, the terminal 52 or the terminals 53, 54 or 55
Are coupled to the terminal 51 in response to the signals at the terminals A and B, the bases of the transistors 56 and 57 are pulled down to a low potential, and the corresponding transistors are turned on. Resistance 6
2 and 63 have different resistance values, the DC bias of the control transistor 32 is
7 depending on which one is conducting, ie,
It is determined by the terminal selected by the raster size selection signal applied to terminals A and B. The DC bias of the control transistor 32 determines the continuity of the transistors 32 and 33 in response to the parabolic waveform from the vertical deflection circuit 11 and substantially determines the amount of deflection current modulation, and thus the raster width. In the particular embodiment shown, for each of the four possible logical combinations of signals applied to terminals A and B, which of terminals 44, 45, 46 and 47 is connected to terminal 43. Or terminals 52, 53, 54
Which of 55 and 55 is connected to terminal 51 is as shown in the following table. [Table 1] As is apparent from this figure, the above-described raster size selection circuit can be used to select and determine four different combinations of raster height and raster width. Regardless of the raster size selected, a stable raster pattern can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a partial block circuit diagram showing a main configuration of an example video display device embodying the present invention. [Description of Signs] A, B Display signal receiving means (input terminal) 10 Horizontal deflection circuit 11 Vertical deflection current generation means (Vertical deflection circuit) 12 Cathode ray tube 14 Horizontal deflection current generation means 32, 33 Horizontal deflection current control means (both Control transistor) 39 sampling means (resistance) 40 raster size selection circuit 41 horizontal deflection current control means or deflection means (decoder) of feedback means (48) 48 feedback means

──────────────────────────────────────────────────続 き Continuation of the front page (56) References Japanese Utility Model 58-31586 (JP, U) Japanese Utility Model 56-135658 (JP, U) (58) Fields surveyed (Int. Cl. ⁷ , DB name) H04N 3/223 G09G 1/04 H04N 3/23 H04N 3/27

Claims (1)

(57) [Claims] 1.A deflection circuit for generating a horizontal deflection current; Connected to the horizontal deflection circuit to control horizontal deflection current amplitude
Adjusting means for adjusting the raster width of the image by performing A) for correcting horizontal deflection distortion;
A vertical velocity parabola signal for b.
DC bias level for the adjusting means for adjusting the width
Means for controlling the horizontal deflection current based on both Multiple representing specific horizontal deflection amplitude according to proprietary video standard
Digitally coded signal consisting of binary signals
And specifically expressed in the digitally encoded signal.
Depending on the information being output,
The digitally encoded signal to produce one of
Decoding means for decoding According to the one of the decoded plurality of output signals,
DC bias level by switchable current branch
Set, thereby complying with the above proprietary video standards
Means for adjusting the raster width and Video display device including.