JPH0654887B2 - Spread spectrum power line carrier communication method and apparatus - Google Patents

Description

The present invention relates to a communication method and device for centrally monitoring N slave devices by one master device while using a power line as a transmission line. It is about.

[Prior art]

An example of a system in which one master device centrally monitors a plurality of slave devices is a security system. In this security system, a large number of various sensors such as an infrared intrusion sensor, a window glass breakage detection sensor and a fire detection sensor are provided in the monitored area, and each of these sensors has its own transmitter and line. Centralized monitoring is performed by being connected to a monitoring device via.

However, in such a system configuration, if the number of transmitters as slave devices and the monitoring range increase, the amount of wiring increases and the cost increases.
In addition, when connecting the slave device and the master device with a signal line, it is necessary to devise a device for preventing the signal line from being cut and a device for quickly detecting that the signal line is cut. Become.

On the other hand, paying attention to the fact that each slave device obtains power from a commercial power line, a device that performs signal transmission while using the power line as a transmission line has been proposed. For example, a single sideband modulation method is used for transmission line transmission, and a frequency modulation method or a phase modulation method is used for distribution line transmission.

However, power lines such as power transmission lines and distribution lines are not designed in consideration of signal transmission. Therefore, when trying to perform signal transmission, various noises are introduced and the transmission characteristics also affect the load. It will vary greatly depending on the condition. Therefore, reliable signal transmission, particularly high-speed data transmission, is impossible.

By the way, recently, research has been carried out to actively utilize the spread spectrum communication system in each field, and the principle and explanation thereof are published in September, 1982, 96th edition of the Institute of Electronics and Communication Engineers.
It is disclosed on pages 5 and 1053 of the October issue. This spread spectrum communication system is called PN spread or direct spread, and M as a pseudo noise signal is used.
Since a narrow band information signal is spread evenly over a wide band and transmitted using a sequence code, even if multiple zero points occur in the transmission characteristics due to the load state of the power line, there is almost no effect. Even if the noise is not received and narrow band noise is mixed, the S / N becomes large because of the correlation at the receiving side.

[Problems to be solved by the invention]

However, when the above-mentioned spread spectrum power line carrier system is applied to a system in which one master device centrally monitors a plurality of slave devices, when a plurality of slave devices simultaneously transmit information signals to the master device, However, there is a problem that the information signals overlap and the received information cannot be discriminated. On the other hand, in order to prevent information signals from being simultaneously sent from a plurality of slave devices to the master device, the master device sequentially polls each slave device, and each slave device responds to this polling by sending an information signal. A polling method for transmitting a signal may be applied, but there is a problem in that the number of devices is increased and the device becomes expensive.

Therefore, the spread spectrum power line carrier communication method and apparatus according to the present invention uses a power line as a transmission path, and when one master device centrally monitors a plurality of slave devices, a complicated polling method or the like is used. An object of the present invention is to provide a spread spectrum power line carrier communication method and device capable of performing reliable monitoring without requiring a procedure and a control circuit using a central processing unit (CPU) for executing this procedure. Is.

[Means for solving problems]

The spread spectrum power line carrier communication method and device according to the present invention confirms the presence or absence of the spread spectrum modulation signal flowing in the power line used as the transmission line when the slave device side requests the transmission of the information signal, and performs the spread spectrum modulation. When there is no signal, the information signal is spread-spectrum-modulated and transmitted, and when the spread-spectrum-modulated signal is present, the transmission of the information signal is suspended, so that a plurality of slave devices are changed to one master device. This is to prevent overlapping of the transmission signals supplied.

In addition, in the present invention, the first transmitting device for spread spectrum modulation of the transmitting information signal on each slave device side.
Generating an M-sequence code and a transmitting second M-sequence code having the same code pattern as the transmitting first M-sequence code,
This second M sequence code for transmission is transmitted to the power line in addition to the spread spectrum modulation signal modulated by the first M sequence code for transmission only when the information signal for transmission is generated, and is unique to each slave device between the M sequence codes for transmission. It is used to determine the transmission slave device by providing the phase difference of.

Further, in the present invention, the phase of the transmitting second M-sequence code generated in each slave device is sequentially changed at least every one period or more, and the correlation with the signal received through the power line is obtained. Is used to identify the transmission state of another slave device.

Further, according to the present invention, the first M-sequence receiving code having the same code pattern as the first M-sequence transmitting code used for demodulating the received spread spectrum modulated signal on the master device side and the first M-sequence receiving code transmitted from each slave device. First for incoming transmission
A second M-sequence code for reception having the same code pattern used for obtaining a correlation with the M-sequence code is generated, and a phase of a clock pulse which is a basis for generating the first and second M-sequence code for reception is generated. Until the correlation between the second M-sequence code for reception and the second M-sequence code for transmission sent from the slave device is obtained, the second M-sequence code for reception is sequentially varied at every cycle that is equal to or longer than the generation cycle of the second M-sequence code for reception. The generation cycle of the second M-series code and the receiving second M-series code is synchronized.

Further, in the present invention, when the correlation between the transmitting second M-series code and the receiving second M-series code is obtained, only the phase of the receiving first M-series code is shifted while receiving at least every generation cycle thereof. Multiply demodulate the spread spectrum modulated signal,
When the demodulated signal is obtained, the phase shift is stopped to take out the received signal, and the transmission slave device is discriminated according to the phase difference between the receiving first and second M-sequence codes.

Further, in the present invention, the clock pulse generation circuit provided in each slave device and the master device is configured to generate a clock pulse that is phase-locked to the AC power source flowing in the power line, thereby ensuring phase synchronization between transmission and reception. It is a thing.

[Action]

In the spread spectrum power line carrier method and device configured as described above, each slave device confirms the presence or absence of a spread spectrum modulated signal flowing in the power line used as a transmission line, and only when there is no spread spectrum modulated signal, the transmission information signal is spread by the M sequence code. Since it is spread-modulated and transmitted, multiple slave devices do not transmit at the same time, and as a result, one master device can monitor multiple slave devices in a concentrated manner. become.

Further, in the present invention, each slave device generates the first M-sequence code for transmission and the second M-sequence code for transmission for performing spread spectrum modulation of the transmission information in a state having a phase difference unique to each slave device. Since the second M-sequence code for transmission is added to the spread spectrum modulation signal for transmission, the first M-sequence code for reception which is used for demodulating the reception spread spectrum modulation signal on the master device side and the reception It is possible to easily determine the slave device that is transmitting, from the phase difference between the second M-sequence code for reception and the second M-sequence code for reception that is included in the signal.

Further, in the present invention, when the information signal for transmission is generated, each slave device adds the second M sequence code for transmission to the spread spectrum modulated signal which is product-modulated by the first M sequence code for transmission. Since it is transmitted to the power line,
Each slave device only sequentially shifts the phase of the second M-sequence code for transmission and determines whether or not a correlation with the signal supplied via the power line is obtained, and it is easy to determine whether or not another slave device is transmitting. Can be identified.

Further, according to the present invention, the clock pulse generation circuit in each slave device and the master device is configured to generate a clock pulse phase-locked to the AC power source flowing through the power line as a telegraph path. In this case, the correlation between the second M-sequence code for reception and the received second M-sequence code for transmission which are generated based on this clock pulse and the product demodulation of the reception spread spectrum modulated signal by the first M-sequence code for reception are surely performed. Will be done.

〔Example〕

FIG. 1 is a block diagram showing an embodiment for explaining a spread spectrum power line carrier communication method and device according to the present invention, in which (a) is a slave device connected to N power lines as a transmission line, b) is a master device connected to the power line to centrally manage each slave device.
In the figure, reference numeral 1 is a coupler composed of a transformer 2 and a capacitor 3 for supplying and extracting a spread spectrum modulation signal, which will be described later, to the power line 4. Reference numeral 5 is a receiving amplifier connected to the coupler 4, 6 is a clock oscillation circuit that stably generates a clock pulse of, for example, 450 KHz, and 7 is a synchronization control circuit 23, which will be described later, for explaining the phase of the clock pulse supplied from the clock oscillation circuit 6. The clock control circuit is variable according to the output signal, and is composed of a generally known circuit having, for example, a phase lock loop circuit (PLL). Reference numerals 8 and 9 denote first and second M-series code generation circuits for generating M-series codes synchronized with the clock pulse output from the clock control circuit 7. The M-series codes generated from both have the same pattern and only the phase. Are sequentially shifted, for example, in 1-bit units according to the address of each slave device. The first and second M-sequence code generation circuits 8 and 9 are configured, for example, as shown in FIG. The first M-sequence code generation circuit 8 shown in FIG. 2 includes a shift register 10 in which flip-flop circuits FF _{1 to} FF ₃ are connected in series, and flip-flop circuits FF ₂ and FF ₃ in the shift register 10.
Exclusive-OR gate 11 which obtains an exclusive-OR for the output signal of and returns to the input side of the shift register 10
And a setting circuit 12. here,
The setting circuit 12 includes each slave device (for example, an address) between the M-sequence code generated by the first M-sequence code generation circuit 8 and the M-sequence code generated by the second M-sequence code generation circuit 9 and having the same code pattern. (Corresponding to the above) and is composed of switches 12a to 12c connected to the power supply + V and pull-down resistors 13a to 13c, and the switches 12a to 12c are shown in the drawing. When set, a setting signal of "0, 1, 1" is output. When the load control signal is supplied from the second M-sequence code generation circuit 9, each shift register FF ₁
~ FF ₃ reads the signal output from the setting circuit 12 to initialize the shift register 10,
After that, the M-sequence code is generated by sequentially shifting according to the supply of the clock pulse.

On the other hand, the second M-sequence code generation circuit 9 is similar to the first M-sequence code generation circuit 8 in that a shift register 14 in which flip-flops FF _{1 to} FF ₃ are connected in series, and a second M-sequence code generation circuit in the shift register 14 are provided. The shift register 14 is constituted by an exclusive OR gate 15 which obtains an exclusive OR for the output signal from the third stage and returns the exclusive OR, so that the shift register 14 is operated by the exclusive OR gate 15 every time a clock pulse is supplied. Is sequentially shifted to output an M-sequence code having the same code pattern as the M-sequence code generated from the first M-sequence code generation circuit 8.
Further, the second M-sequence code generation circuit 9 is provided with an add gate 16 for detecting a state in which the output signals of the flip-flop circuits FF _{1 to} FF ₃ are all “1”,
The output signal of the AND gate 16 is supplied to the shift register 10 of the first M-sequence code generation circuit as a load control signal. Therefore, the shift register 14 is all "1".
At this time, the setting signal generated from the setting circuit 12 is set in the shift register 10, so that the difference between “111” and the setting signal (“011” in this case) is the first and the second M.
It becomes the phase difference of the M-sequence code generated from the sequence code generation circuits 8 and 9, and this phase difference is set to a different value for each slave device by the setting circuit 12.

Next, in FIG. 1 (a), 17 is a sensor, 18 is a modulator, and M supplied from the first M-sequence code generation circuit 8
The series code and the sensor signal as a transmission information signal supplied via the interface circuit 19 are multiplied and product-modulated to convert a narrow band sensor signal into a spread spectrum modulation signal that is uniformly distributed over a wide band. And output. Reference numeral 20 is an adder for adding the spread spectrum modulation signal supplied from the modulator 18 and the M-sequence code supplied from the second M-sequence code generation circuit 9, and 21 is an adder 20 supplied via the switch circuit 20. It is a transmission amplifier that amplifies the output signal and supplies it to the coupler 1. Reference numeral 23 is a correlator that obtains a correlation between the output signal of the reception amplifier 5 and the M-sequence code output from the second M-sequence code generation circuit 9, and reference numeral 24 is a synchronization control circuit, which transmits a transmission information signal via the interface circuit 19. When supplied, the control circuit 7
Is controlled for a predetermined time to sequentially shift the phase of the clock pulse, thereby sequentially varying the phase of the M-sequence code generated from the first and second M-sequence code generation circuits 8 and 9 for each cycle and at least one cycle. By doing so, all the correlation conditions for the modulation signal supplied from the reception amplifier 5 of the correlator 23 are reproduced. Then, when the correlation output generated from the correlator 23 is supplied, the synchronization control circuit 24 suspends the control of the clock control circuit 7.
Therefore, the time setting in the synchronization control circuit 24 is at least the time until the phase of the M-sequence code output from the second M-sequence code generation circuit 9 makes one round. 25
Is a switch control circuit, and when the correlation output is not obtained within the operation period of the synchronization control circuit 24, that is, the M sequence of the same code pattern generated from the second M sequence code generation circuit 9 in another slave device. The switch closing enable signal is supplied to the switch circuit 22 only when the code is not transmitted to the power line 4 together with the spread spectrum modulation signal. And
The switch circuit 22 is configured to be closed only when a match between the switch closing enable signal and the sensor signal is obtained.

Next, in the master device shown in FIG. 1 (b), the coupler 26, the receiving amplifier 27, the clock oscillation circuit 28, the clock control circuit 29, the correlator 30, and the synchronization control circuit 31 are shown in FIG. 1 (a).
The configuration and connection relationship are the same as the corresponding parts in the slave device shown in FIG. 32 is a clock control circuit 2
9 is an M-th sequence code generation circuit for generating an M-sequence code in synchronization with a clock pulse supplied from the M.C. 9 and is generated in response to a setting signal supplied from a phase shift control circuit 38 described later. Are to be phase-shifted. Similarly to the first M-sequence code generation circuit 32, 33 is a second M-sequence code generation circuit for generating an M-sequence code in synchronization with the clock pulse supplied from the clock pulse generation circuit 29, which is shown in FIG. The 2M sequence code generation circuit 9 is configured by only the shift register 11 and the exclusive OR gate 13. The M-sequence code generated from these first and second M-sequence code generation circuits 32 and 33 is generated from the first and second M-sequence code generation circuits 8 and 9 of each slave device shown in FIG. 1 (a). The code pattern is the same as the M-sequence code used. Next, a demodulation circuit 34 receives the spread spectrum modulated signal output from the reception amplifier 27 and outputs it to the first M-sequence code generation circuit 3
The received information signal is extracted by performing the product demodulation using the M-sequence code generated from No. 2. Reference numeral 35 is an interface circuit for supplying the received information signal taken out by the demodulator 34 to the display circuit 36 for display, and 37 is a frequency divider composed of a counter, which is a clock oscillation circuit
Each time the clock pulse output from is divided by M, a pulse having one cycle width of the clock pulse is output. The frequency division ratio M in this case is determined by the first M-sequence code generation circuit 32.
Is set to twice or more the maximum cycle length of the M-sequence code generated from Reference numeral 38 denotes a phase shift control circuit, which is M-sequence generated from the first M-sequence code generation circuit 32 in synchronism with the output generation of the frequency divider 37 only in the period in which the output signal of the correlator 30 is supplied. The control for shifting the phase of the code is executed, and the phase shift control is stopped when the reception information signal is output from the demodulator 34.

FIG. 3 shows the first M-sequence code generation circuit 3 shown in FIG. 1 (b).
2 is a circuit diagram showing a specific example of the phase shift control circuit 38 and the phase shift control circuit 38. FIG. In the figure, an AND gate 39 provided in the phase shift control circuit 38 outputs a pulse signal of a clock cycle width supplied every time the clock pulse is frequency-divided by the frequency divider 37 and the output of the correlator 30. The signal and the output signal of the inverter 40, which inverts the output signal of the demodulator 34, are used as inputs to find a match. Reference numeral 41 is a counter, which sequentially counts the output signals of the AND gate 39. A decoder 42 generates a phase shift setting signal by decoding the count output of the counter 41.
Next, the first M-sequence code generation circuit 32 operates as the first M-sequence code generation circuit 32 shown in FIG.
Similar to the M-sequence code, the flip-flops FF _{1 to} FF ₃
And an exclusive OR for calculating the exclusive OR of the output signals generated from the shift register 10 configured by and the second and third output stages (positions where the same code pattern is obtained) in the shift register 10 and performing feedback. And an OR gate 11. Then, the shift register 10 uses the output signal of the AND gate 39 forming the phase shift control circuit 38 as a load signal and outputs the phase shift setting signal output from the decoder 42 forming the phase shift control circuit 38 in place of the setting circuit 12. Read and set as initial value.

In the system configured as described above, when the power is turned on, the clock oscillation circuit 6 of each slave device and the clock oscillation circuit 28 provided in the master device operate,
Generate clock pulses of the same frequency. Here, when a clock pulse is generated from the clock oscillation circuit 6, this clock pulse is passed through the clock oscillation circuit 7 to
By being respectively supplied to the second M-sequence code generation circuits 8 and 9, M-sequence codes having the same code pattern but different in phase from each other according to the address of each slave device are generated. That is, in the circuit shown in FIG. 2, the shift register 10 forming the first M-sequence code generation circuit 8 sequentially shifts the output signal of the exclusive OR gate 11 each time a clock pulse is supplied. In this case, since the exclusive OR gate 11 receives the output signal of the predetermined output stage of the shift register 10 as an input and feeds back the exclusive OR output, the input of the exclusive OR gate 11 The code pattern depends on the state and the maximum code length is 2
^N- 1 M-sequence codes are generated.

On the other hand, also in the second M-sequence code generation circuit 9, the shift register 14 sequentially shifts the output signal of the exclusive OR gate 16 each time a clock pulse is supplied. And
This exclusive OR gate 16 receives the signal of the same predetermined shift register output stage as that of the second M-sequence code generation circuit 8 as an input and feeds back the exclusive OR output. The code patterns of the M-sequence codes generated from the second M-sequence code generation circuits 8 and 9 are the same. However, the second M-sequence code generation circuit 9 is equivalent to the shift register 1
When the output signals of 4 are all "1", the AND gate 16 generates a load control signal and supplies it to the shift register 10 in the second M-sequence code generation circuit 8. Therefore,
When the shift register 14 is all “1”, the shift register 10 supplies the setting signal (“01
1 ") is read and set, the M-sequence code output from the first and second M-sequence code generation circuits 8 and 9 corresponds to the difference between" 111 "and the setting signal" 011 ". A phase difference is generated, and the phase difference is generated by the switches 12a to 12c that configure the setting circuit 12.
A different value is set for each slave device to represent the address of the slave device.

Here, when the sensor 17 issues a transmission information signal, this transmission information signal is supplied to the modulator 18, the switch circuit 22, and the synchronization control circuit 24 via the interface circuit 19, respectively. When the transmission information signal is supplied, the synchronization control circuit 24 controls the clock control circuit 7 so that the M-sequence code generated from the first and second M-sequence code generation circuits 8 and 9 is synchronized with each other for each period of time or more. The output clock pulse phase is sequentially shifted. Therefore, the first and second M
The M sequence code generated from the sequence code generation circuits 8 and 9 is
The phases are sequentially shifted while having a predetermined phase difference from each other. Then, the synchronization control circuit 24
Is generated by the second M-sequence code generation circuit 24 for a period of time until the phase of the generated M-sequence code makes at least one cycle.
The output signal of the correlator 23 for obtaining the correlation between the M-series code output from the receiver and the output signal of the reception amplifier 5 is monitored.
When another slave device transmits the transmission information signal by spread spectrum modulation to the master device via the power line 4, it is generated from the second M-sequence code generation circuit 9 in the slave device. The M-sequence code having a common code pattern should be added to the spread spectrum modulation signal output from the modulator 18 and output in the adder 20. Therefore, the synchronization control circuit 24 is
The output signal is obtained from the correlator 23 during the period until the phase shift operation of the M-sequence code generated from the M-sequence code generation circuit 24 is completed at least once. Then, when the output signal is supplied from the correlator 23, the synchronization control circuit 24 stops the phase shift control and monitors the output signal of the correlator 23, so that the slave device that is transmitting can be prevented from transmitting. wait. Therefore, during this waiting period, the switch control circuit 25 is made inoperative to prevent the switch circuit 22 from being closed, thereby suspending the transmission of the transmission information signal and transmitting it from another slave device. Prevents overlapping of signals.

Next, when the transmission from the other slave device described above is completed, the output signal of the correlator 23 is cut off and the synchronous control circuit 24 is notified of such a state. By controlling the clock control circuit 7 again, the synchronization control circuit 24 sequentially shifts the phase of the M-sequence code generated from the second M-sequence code generation circuit 9 at intervals of at least one cycle, and at least the phase shift occurs. If the output signal is not supplied from the correlator 23 during the period of one cycle, it is determined that all slave devices connected to the power line 4 are not performing the transmission operation, that is, as the transmission path. The switch control circuit 25 judges that the power line is in an empty state.
Supply the signal to. The switch control circuit 25 is. When a signal indicating that the transmission path is vacant is supplied from the synchronization control circuit 24, it is confirmed that no signal is sent from the correlator 23, and then a closing enable signal is supplied to the switch circuit 22.

On the other hand, the modulator 18 multiplies the transmission information signal supplied through the interface circuit 19 by the M-sequence code supplied from the first M-sequence code generation circuit 8 to spread the spectrum uniformly distributed over the wide band. The modulated signal is supplied to the adder 20. The adder 20 converts the spread spectrum modulation signal into the second M-sequence code generation circuit 9
The M-series code output from the above is added and supplied to the switch circuit 22. Here, since the switch circuit 22 is already closed due to the coincidence of the transmission information signal supplied from the interface circuit 19 and the close enable signal supplied from the switch control circuit 25, the output signal of the adder 20 is The power is supplied to the transmission amplifier 21 via the switch circuit 22, amplified, and then supplied to the power line 4 via the coupler 1.

Next, in the master device shown in FIG. 1 (b), the clock oscillating circuit 28 generates a clock pulse having the same frequency as the clock oscillating circuit 6 in the slave device. It is supplied to the first and second M-series code generation circuits 32 and 33 via the circuit 29 to generate M
Sequence code generation is performed. And this second M
The M-sequence code output from the sequence-code generating circuit 33 is added to the signal supplied from the slave device via the combiner 26 and the receiving amplifier 27 in the correlator 30, that is, the spread-spectrum modulated signal, and sent. The correlation with the M-series code generated from the second M-series code generation circuit 9 that comes is obtained. Here, when the correlation cannot be obtained in the correlator 30, the synchronization control circuit 31 controls the clock control circuit 29 so that the first and second M-sequence code generation circuits 3 are generated.
The control of sequentially shifting the phase of the clock pulse supplied to Nos. 2 and 33 and the phase of the generated M-sequence code is performed at least at intervals of at least the generation periphery thereof. Therefore, when any one of the plurality of slave devices is transmitting, the correlation is obtained from the correlator 23 at a certain point in time until the phase of the second M-sequence code makes one cycle. Is generated and supplied to the synchronization control circuit 24. The synchronization control circuit 31 includes the correlator 3
When the output signal from 0 is received, the second M-sequence code generation circuit 9 in the slave device which is transmitting the M-sequence code of the phase generated from the second M-sequence code generation circuit 33 at that time.
The phase shift operation of the clock control circuit 29 is stopped and the correlation state of the correlator 30 is maintained.

On the other hand, the frequency divider 37 having a counter configuration divides the clock pulse supplied from the clock oscillation circuit 28 into 1 / M so as to have a period of two or more periods of the M-sequence code, and thus one period of the clock pulse. Is supplied to the phase shift control circuit 38 as a pulse having a width of. Here, in the phase shift control circuit 38 shown in FIG. 3, when a pulse signal is supplied from the frequency divider 37, the output signal of the correlator 30 is "H" and the output signal of the demodulator 34 is inverted. Since the output signal of the inverter 40 is also "H", it is supplied to the counter 41 via the AND gate 39. Therefore,
The counter 41 sequentially counts the pulse signals from the frequency divider 37 and supplies the count output to the decoder 42. The decoder 42 decodes the count output of the counter 41 to output a setting signal designating a phase shift amount to each of the flip-flop circuits FF _{1 to} FF ₃ of the shift register 10 which constitutes the first M-sequence code generation circuit 32. Supply to the input end. Since the shift register 10 uses the output signal of the AND gate 39 in the phase shift control circuit 38 as the load control signal, it is output from the decoder 42 every time the pulse signal is supplied from the frequency divider 37. While the setting signal is read and the initial value is set, the M-sequence code is generated in synchronization with the clock pulse. As a result, the setting signal output from the decoder 42 sequentially changes according to the count of the counter 41, so that the phase of the M-sequence code generated from the first M-sequence code generation circuit 32 is generated from the frequency divider 37. The phase will be sequentially shifted according to the applied pulse. Then, the M-sequence code generated from the first M-sequence code generation circuit 32 is the demodulator 3
In 4, the product demodulation with the reception spread spectrum modulation signal supplied from the reception amplifier 27 is performed, and the M series code generated from the first M series code generation circuit 32 and the M sequence code used to create the reception spread spectrum modulation signal. When the phase matches the sequence code, the demodulator 34 outputs the received signal as a demodulated signal. Then, this received signal is supplied to the inverter 40 that constitutes the phase shift control circuit 38.
Is supplied to the AND gate 39, the output signal becomes "L" and the AND gate 39 is closed to prevent the pulse from the frequency divider 37 from being input. As a result, the supply of the load control signal to the shift register 10 in the first M-sequence code generation circuit 32 is stopped, so that the phase of the generated M-sequence code is fixed and the demodulation for the received spread spectrum modulation signal is performed. The operation will be continued.

On the other hand, the received signal output from the demodulator 24 is supplied to the display circuit 36 via the interface circuit 35, so that the content of the received signal is displayed. In addition, the display circuit 36 receives the setting signal output from the phase shift control circuit 38 via the interface circuit 35, so that the M-sequence code generated from the first and second M-sequence code generation circuits 32 and 33. Of the slave device that is transmitting is identified and displayed from this phase difference. Then, when the transmission operation of the slave device is cut off due to the restoration of the sensor 17 or the end of the signal transmission operation accompanying the timer operation, the output signals of the correlator 30 and the demodulator 34 are cut off. Control circuit 2
9 to control the phase of the M-sequence code generated from the second M-sequence code generation circuit 33 in order to obtain the correlation with the signal from another slave device, that is, the next received spread spectrum modulation signal. Perform control to search. Further, since the output signal of the correlator 30 is disconnected, the phase shift control circuit 38 has the AND gate 39.
Is closed to stop the phase shift operation for the first M-sequence code generation circuit 32.

FIG. 4 is a flow chart showing the operation of the slave device described above. In step S ₁ , the sensor 17 is used.
Is in a standby state until is activated. Then, when the output signal is generated from the sensor 17, the determination in step S ₁ is YES and the process proceeds to step S ₂ . Is in step S _2, the M-sequence code phases which are generated from the 2M-sequence code generation circuit 9 sequentially shifting, to determine the presence or absence of at the correlation output to a correlator 23, meet the determination result is YES In this case, since another slave device is transmitting, the operation of returning to step S ₁ is repeated to suspend the transmission from the self slave device and prevent the transmission signals from overlapping. Next, at decision step S ₂ is becomes NO, and by all the slave device proceeds to step S ₃ it is determined that it is finished transmitting, and spread spectrum modulation the sensor signal as a transmission information After performing the transmission operation of supplying the master device later via the power line, the operation of returning to step S ₁ is repeated.

Figure 5 is a flow chart showing the operation of the above-described master devices, in step S ₁₀ by sequentially shifting the M-sequence code phases which are generated from the 2M-sequence code generation circuit 33, the slave device Determines whether synchronization with the M-sequence code sent from
If the result of the determination is NO, the operation returns to step S ₁₀ is repeated to wait until synchronization is achieved. Next, when the transmission signal from the slave device is received, step S
_{If the} determination in ₁₀ is YES, the process proceeds to step S ₁₁ and the presence or absence of a received signal, that is, the M sequence code generated by the phase shift operation of the first M sequence code generation circuit 32 by the phase shift control circuit 38, and the reception It is determined whether or not a demodulation signal can be obtained from the demodulator 34 which receives the spectrum modulation signal as an input. And this step S ₁₁
If in decision to become NO, demodulates the received spectrum modulated signal using the M-sequence code, which is further phase-shifted by performing the operation returns to step S _11. By repeating such an operation, the judgment in step S ₁₁ is YES.
Becomes the S, after executing the receiving operation proceeds to step S _12, to repeat the operation returns to step S ₁₀ after displaying the address of the received information and transmitting the slave device proceeds to step S _13.

Next, the clock oscillation circuits 6 and 28 shown in FIGS.
Is configured as a PLL (Phase-Locked Loop) configuration so as to generate a clock pulse synchronized with an AC power source flowing through the power line 4, so that the phases of the clock pulses generated on the slave device side and the master device side are Since the matches are more accurate, more reliable communication can be performed.

[Effects of the Invention] As described above, in the spread spectrum carrier communication method and apparatus according to the present invention, one master device is centralized by using spread spectrum carrier communication for a plurality of slave devices connected to the power line. In the monitoring system, when a transmission request for transmission information is made to each slave device, the presence or absence of a transmission signal from another slave device is confirmed on the power line as a transmission path, and if there is a transmission signal, a transmission operation is performed. Is suspended and transmission is started when there is no other transmission signal. Therefore, even if the same power line is shared as a transmission path, the problem of overlapping signals due to simultaneous transmission from a plurality of slave devices is solved. Along with this, a plurality of slave devices are combined into one master device. The device can be reliably monitored in a centralized manner. Further, in the present invention, each slave device generates a M-sequence code used to modulate a transmission information signal, and a first M-sequence code generation circuit, and an M-sequence code generated from the first M-sequence code generation circuit. A second M-sequence code generation circuit that generates an M-sequence code having the same code pattern as the above, and each slave is placed between the M-sequence codes generated from the first and second M-sequence code generation circuits. Since the phase difference is unique to each device, the spread spectrum modulated signal obtained by modulating the transmission information signal with the M sequence code generated from the first M sequence code generation circuit is generated by the M second sequence code generation circuit. By adding the sequence code and transmitting, the master device side receives this transmission signal and obtains correlation.
By knowing the phase relationship between the sequence code and the M sequence code that can obtain the demodulation output for the spread spectrum modulation signal, it is possible to easily identify the slave device that is transmitting this transmission signal. Have an effect.

[Brief description of drawings]

1 (a) and 1 (b) are block diagrams of a slave device and a master device for explaining an embodiment of a spread spectrum power line carrier communication method and device according to the present invention, and FIG. 2 is FIG. 1 (a). FIG. 3 is a circuit diagram showing a specific example of the first and second M-sequence code generation circuits shown in FIG. 3, and FIG. 3 is a circuit diagram showing a specific example of the first M-sequence code generation circuit and the phase shift control circuit shown in FIG. 4 and 5 are flowcharts showing the operation of the slave device and the master device shown in FIGS. 1 (a) and 1 (b). 1, 26 ... Coupler, 4 ... Power line, 5, 27 ... Receiving amplifier, 6, 28 ... Clock oscillation circuit, 7, 29 ...
Clock control circuit, 8, 23 ... First M-sequence code generation circuit, 9, 33 ... Second M-sequence code generation circuit, 17 ... Sensor, 18 ... Modulator, 19, 35 ... Interface circuit, 20 ... ... adder, 21 ... transmission amplifier, 22 ...
... Switch circuits, 23,30 ... Correlators, 24,31 ...
… Synchronous control circuit, 25 …… Switch control circuit, 34 ……
Demodulator, 36 ... Display circuit, 37 ... Divider, 38 ...
Phase shift circuit.

Claims (6)

[Claims] 1. A plurality of slave devices and one master device are commonly connected to a power line as a transmission line, and each slave device is connected to another slave device that flows through the power line when a transmission request is made. If there is a transmission signal, and if there is a transmission signal from another slave device, the transmission operation is suspended, and if it is confirmed that there is no transmission signal from another slave device, the transmission information signal is sent. To the modulation signal that is spread spectrum modulated by the first M-sequence code,
The second M-series code for transmission having the same code pattern as the first M-series code and having a phase difference unique to each slave device is added, and then transmitted to the master device via the power line. The demodulated spread spectrum modulated signal is used to extract the received information, the M sequence code used when the spread spectrum modulated signal is generated, and the M sequence code transmitted in addition to this spread spectrum modulated signal. A spread spectrum power line carrier communication method, characterized in that a transmission slave device is discriminated from a phase difference between and. 2. The confirmation of a transmission signal from another slave device flowing on the power line is made by judging the presence or absence of correlation while sequentially shifting the phase of the second M-sequence code for transmission. The spread spectrum power line carrier communication method according to item 1. 3. A plurality of slave devices connected to a power line and one master device, wherein each slave device has the same M-sequence code of the same code pattern having a phase difference unique to each slave device. A first and a second M-sequence code generation circuit for generating a clock pulse as an input;
A modulator for performing spread spectrum modulation of a transmission information signal by an M-sequence code output from an M-sequence code generation circuit, a signal supplied from a power line via a combiner, and an M-sequence output from the second M-sequence code generation circuit. Generated from the first and second M-sequence code generation circuits by controlling a correlator for obtaining a correlation with a code and a clock control circuit for sequentially shifting the phase of a clock pulse when a transmission request for a transmission information signal is made. A synchronization control circuit that determines whether or not another slave device is transmitting based on the presence or absence of a correlation output from the correlator when the phase of the M-sequence code is rotated at least once, and this synchronization control circuit transmits from another slave device. From the second M-sequence code generation circuit and the spread spectrum modulation signal output from the modulator only when it is determined that Spread spectrum power line communication apparatus characterized by supplying to said coupler a sum signal of the M-sequence code, which is the force as a transmission signal is constituted by a switch circuit to be transmitted to the power line. 4. A plurality of slave devices connected to a power line and one master device, wherein the master device and an M-sequence code for spread spectrum modulation generated in the slave device by the same clock pulse. First and second M-series code generation circuits for respectively generating M-series codes of the same code pattern, and the phases of clock pulses supplied to the first and second M-series code generation circuits are sequentially shifted in response to an external request. Clock control circuit, a correlator for obtaining the correlation between the received signal supplied from the power line through the combiner and the M-sequence code output from the second M-sequence code generation circuit, and the correlation output from the correlator. A synchronization control circuit that controls the clock control circuit until it is generated and sequentially shifts the phase of the M-sequence code output from the second M-sequence code generation circuit. A phase shift control circuit for sequentially shifting the phase of the M-sequence code generated from the first M-sequence code generation circuit during the period in which the correlation output is generated from the correlator, and the first M-sequence code generation circuit A demodulator that demodulates the received spread spectrum modulated signal supplied from the combiner using the generated M-sequence code to output the received signal and stop the operation of the phase shift control circuit by the received signal. A spread spectrum power line carrier communication device characterized by being configured. 5. The spread spectrum power line carrier communication device according to claim 4, wherein the transmission slave device is identified by the output signal of the phase shift control circuit when the reception signal from the demodulator is generated. 6. The clock pulse used in each slave device and master device is generated in synchronization with AC power flowing through a power line used as a transmission path. The spread spectrum power line carrier communication device described.