JPH0654280A - Liquid crystal video display device - Google Patents

Abstract

PURPOSE:To prevent the break of a liquid crystal display panel due to an abnor mal input signal by detecting the abnormality of a vertical synchronizing signal inputted from the outside to perform switching to an internal vertical synchroniz ing signal generating means. CONSTITUTION:Input terminals 2 to 6 to which a video signal and horizontal and vertical synchronizing signals are inputted independently of one another are provided, and an HD presence/absence detecting circuit 22 detects the presence or the absence of a horizontal synchronizing signal HD, and a VD abnormal input detecting circuit 24 detects the abnormal input of a vertical synchronizing signal VD. Consequently, a control circuit 26 outputs a VD switching signal for selection of the signal of an internal VD oscillating circuit 28 to a VD switching circuit 27 if a horizontal synchronizing signal regarded as abnormal is inputted to the vertical synchronizing signal terminal 6. That is, a terminal a-c of the VD switching circuit 27 is turned on to input the vertical synchronizing signal VD to a clock generator 30 when the normal vertical synchronizing signal VD is inputted, putted, but a terminal b-c of the VD switching circuit 27 is turned on to input a signal INTVD outputted from an internal VD oscillating circuit 28 to the clock generator 30 when an abnormal signal is inputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal image display device used in a video device such as a television receiver and a display monitor, and more particularly to a liquid crystal device having an input terminal capable of separately inputting a video signal and horizontal and vertical synchronizing signals. The present invention relates to a liquid crystal image display device for preventing damage to a liquid crystal panel due to reverse connection of horizontal and vertical synchronizing signals in the image display device.

[0002]

2. Description of the Related Art A liquid crystal display panel is constructed, for example, as shown in FIG. In the figure, a liquid crystal display panel 31
The upper pixel is driven by a matrix of horizontal scanning drivers 51 and 52 and vertical scanning drivers 53 and 54. The vertical scanning drivers 53 and 54 are the liquid crystal panel 31.
The horizontal scanning drivers 51 and 52 are mounted on the upper and lower sides of the liquid crystal panel and are driven alternately for each pixel. Then, the video signal in the horizontal direction 1H period is fed to the upper horizontal scanning driver H by the horizontal sampling clock CLDU.
Sampling is performed by U and by the lower horizontal scanning driver HL at the sampling clock CLDL.

FIG. 9 shows an equivalent circuit for one pixel on the liquid crystal display panel 31. For the sampled data, a signal voltage corresponding to each pixel is applied to the source side of a TFT (thin film transistor) on one horizontal line. Next, the vertical scanning driver simultaneously turns on the TFTs on one horizontal line, and a video signal for each line is applied to the liquid crystal. By repeating such an operation in a horizontal cycle, an image for one field is displayed on the liquid crystal panel. An image is expressed by repeating the above operation in field units in a vertical cycle. The signal applied to the liquid crystal is a signal inverted every 1H as shown in FIG. 10, and the liquid crystal is AC driven by the signal inverted every 1H.

FIG. 7 is a block diagram of a conventional example. In this conventional example, the video signal system is omitted. In the figure,
1 is an input terminal board, 2-6 respectively G: green video signal, B: blue video signal, R: red video signal, H _D: the horizontal synchronizing signal, V _D: an input terminal for the vertical synchronizing signal. The horizontal and vertical synchronizing signals H _D and V _D have different levels depending on the connected equipment, and since the levels are originally small, they are input to the waveform shaping circuit 7 and converted to the TTL level.
Horizontal synchronizing signal H _D converted to TTL level is input to the phase comparator 8. The phase comparator 8 compares the phases of the divided signals HPLL obtained from the horizontal synchronizing signal H _D frequency divider 15, these two signals the next stage a differential signal corresponding to the phase difference of the loop filter 13 To a low pass filter (hereinafter referred to as LPF) 9 in FIG. This LPF9
Outputs the difference signal as a control voltage V _LPF and inputs it to the V _REF terminal of a gain control D / A converter (hereinafter referred to as GCD / A converter) 11.

On the other hand, 10 is a loop filter 1 together with the LPF 9, GCD / A converter 11 and adder 12.
3 level shift D / A converter (hereinafter L
It is an SD / A converter) and controls the center frequency of a voltage controlled oscillator (hereinafter referred to as VCO) 14 by digital data given from a control circuit 26. Although not shown, a reference voltage or the like is input to the V _REF terminal of the LSD / A converter 10.

The LSD / A converter 10 and the GCD / A converter 11 are both multiplication type D / A converters that output the product of the input voltage input to the V _REF terminal and the digital value of the D / A converter. Is configured.
Therefore, the GCD / A converter 11 can control the pull-in range by the digital data supplied from the control circuit 26.

The outputs of the LSD / A converter 10 and the GCD / A converter 11 are input to the adder 12 and combined, and the combined control voltage V _CT is input to the VCO 14. The VCO 14 outputs the clock CLK1 corresponding to this voltage based on the control voltage V _CT , and the frequency divider 1
5 and the horizontal clock generator 29.

This frequency divider 15 has a set frequency division ratio (N).
The clock CLK1 input in accordance with is divided, and the divided signal HPLL is fed back to the phase comparator 8. As a result the final horizontal sync signal H _D and of the divided signal HPLL phase is matched by the loop is repeated, the clock CLK1 synchronized in phase with the horizontal synchronizing signal H _D is outputted. That is, this loop is a phase locked loop (PLL) circuit, and the horizontal synchronizing signal H when locked is
_D , the output signal HPLL of the frequency divider 15 and the frequency of the clock CLK1 from the VCO 14 are f _HD ,
If f _HPLL and f _CLK1 , then f _HD = f _HPLL = 1 / N · CLK
It becomes ₁ [Hz].

When paying attention to the control voltage V _LPF from the _{LPF 9} , the window comparator circuit 21 determines the voltages in the locked and unlocked ranges of the PLL circuit.
By monitoring with, it is possible to determine whether the PLL circuit is locked or unlocked. That is, the range in which the PLL circuit is locked, as seen from the control voltage V _LPF, is as shown in FIG. Therefore, the lower limit voltage V2 and the upper limit voltage V1 are created by the resistors 16, 17, and 18 in FIG. 7 (0 <V2 <V1 <Vcc). The upper limit voltage V1 is input to the − side of the first comparator 19, and the lower limit voltage V2 is input to the + side of the second comparator 20. Then, the control voltage V _{LP F} from the LPF 9 is input to the + side of the first comparator 19 and the − side of the second comparator 20.

As a result of the above, the output states of the first and second comparators 19 and 20 are as shown in FIG. That is, in FIG. 12, when both outputs are low level, the PLL circuit is in a locked state. Further, when only the first comparator 19 is at the High level, a frequency higher than the pull-in range of the PLL (range in which the PLL circuit is locked) is not input and the PLL is not locked, and the divided signal HPLL is in the pull-in range. It runs on the higher frequency outside. Further, when only the second comparator 20 is at the high level, it is when the frequency lower than the pull-in range of the PLL is input and the lock is not made.
The frequency-divided signal HPLL self-runs at a lower frequency outside the pull-in range. This includes the case when there is no input signal.

The above first and second comparators 19 and 2
The output of 0 is input to the input port 23, and the control circuit 26 determines the state of the PLL circuit by reading the input port 23. The judgment result is shown in FIG. 29 and 30 are the clock CLK1 from the VCO 14 and the divided signal HP
A horizontal / vertical clock generator that generates and outputs a horizontal clock and a vertical clock required for driving the liquid crystal panel 31 based on LL and the vertical synchronizing signal V _D.

FIG. 14A shows a horizontal system clock, and FIG. 14B shows a vertical system clock.
Explaining the horizontal clock of (A), CLDU, CL
DL is an upper horizontal scanning driver (HU) 5
1. A sampling clock for the lower horizontal scanning driver (HL) 52. These clocks are 180
It can be seen that the phase is shifted, and the upper and lower one pixels are alternately sampled as in the liquid crystal panel shown in FIG. SPDU and SPDL are sampling start pulses of the upper horizontal scanning driver (HU) 51 and the lower horizontal scanning driver (HL) 52, respectively, and are phase-shifted by half a clock of the sampling clock CLD. All of these signals are synchronized in phase with the horizontal synchronizing signal H _D, produced by counting down the clocks CLK1 from VCO14 counter or the like.

The vertical system clocks shown in FIG. 1B will be described. CLSL represents the acquisition clock of the left vertical scanning driver 53, CLSR represents the acquisition clock of the right vertical scanning driver 54, and these clocks are It can be seen that the phases are shifted by 180 ° with respect to each other, and one line on the left side and one line on the right side are alternately captured as in the liquid crystal panel 31 shown in FIG. SPSL and SPSR are sampling start pulses for the left vertical scanning driver 53 and the right vertical scanning driver 54, respectively. These pulses are then shifted one line phase, these signals generates a divided signal HPLL from the frequency divider 15 counts down at the counter or the like, to result in H _D signals are synchronized in phase.

Although not shown in the drawing, the video signal is divided into an upper horizontal scanning driver 51 and a lower horizontal scanning driver 52 and input to the liquid crystal display panel 31.

[0015]

If the external horizontal synchronizing signal and the vertical synchronizing signal supplied to the input terminal are mistakenly reversely connected, the PLL circuit does not lock, but the clock CLK1 from the VCO and the frequency divider are used. Frequency division signal from PLL
Oscillates at the free-running frequency, so that each clock of the horizontal system becomes a clock synchronized with the free-running frequency and drives the upper and lower horizontal scanning drivers without any problem. However, when the horizontal synchronizing signal H _D in the vertical synchronizing signal V _D input terminal of a vertical system clock generator is input, the sampling start pulse (SPS) has been outputted every one vertical period in each horizontal period Since the timing is not normal, some vertical scanning drivers can be driven but the remaining vertical scanning tribers can not be driven,
A fatal drawback of damaging the liquid crystal display panel occurs.

[0016]

In order to solve the above problems, the present invention provides a vertical synchronizing signal input terminal in a liquid crystal image display device having an input terminal capable of separately inputting a video signal and horizontal and vertical synchronizing signals. A vertical synchronizing signal abnormality input detecting means for detecting that a horizontal synchronizing signal is connected to the internal synchronizing signal, an internal vertical synchronizing signal generating means for internally generating a vertical synchronizing signal, and the vertical synchronizing signal abnormality input detecting means for connecting the input terminal. When an abnormal input of the vertical sync signal supplied from the outside via the external vertical sync signal is detected, the vertical sync signal for driving the liquid crystal display panel is supplied from the internal vertical sync signal generating means from the signal supplied from the input terminal. And a switching means for switching to the vertical synchronizing signal.

In addition to the above configuration, when the vertical synchronization signal abnormality input detecting means detects an abnormality in the vertical synchronization signal supplied from the outside through the input terminal, the abnormality input of the vertical synchronization signal is notified based on the detection output. The notification means is provided.

[0018]

Therefore, according to the present invention, when an abnormality in the vertical synchronizing signal is detected by the vertical synchronizing signal abnormality input detecting means as in the case where the horizontal synchronizing signal and the vertical synchronizing signal are mistakenly reversely connected, the liquid crystal display panel The vertical synchronizing signal for driving the liquid crystal display panel is switched by the switching means from the signal supplied from the outside to the internal vertical synchronizing signal generated by the internal vertical synchronizing signal generating means, and the liquid crystal display panel is driven without any problem.

When the vertical sync signal abnormality input detecting means detects an abnormality in the vertical sync signal supplied from the outside,
The detection output operates the notification means to notify the above abnormality.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. The same parts as those of the conventional example are designated by the same reference numerals and the description thereof will be omitted. FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, 22 and 24 is a circuit for discriminating the reverse connection of the horizontal and vertical synchronizing signals H _D, V _D which is the gist of the present invention. 22 is a H _D presence detecting circuit for detecting the presence or absence of the horizontal synchronizing signal H _D, Figure 2
It has a structure as shown in FIG.

In FIG. 2A, first, the horizontal synchronizing signal H _D
Is input to the horizontal frequency dividing signal 55, the horizontal synchronizing signal H
_{Divide D} by two. Since the duty ratio of this frequency-divided signal is 50%, when this frequency-divided signal is smoothed by the smoothing circuit 56, its output C becomes approximately 2.5V. This is input to the window comparator circuit 57.

The window comparator circuit 57 is shown in FIG.
As shown in (b), when the voltage from the reference voltage Vb to Va is input, the output D is set to the high level, and otherwise the output is the low level. Therefore, when there is an input signal, the output D of the window comparator 57 becomes high level as shown in FIG. When there is no input signal, the input of the window comparator 57 changes from 0V to 5V as shown in FIG. 3B, and the output D becomes low level. And for the input of the window comparator 57 becomes 0V or 5V is divide-by-2 circuit is due to edge trigger, because it can eliminate from the state in which the horizontal synchronizing signal H _D is input, high or low, i.e. It becomes 0V or 5V.

Therefore, even if the vertical synchronizing signal V _D is input to the terminal of the horizontal synchronizing signal H _D , the window comparator 5
The reference voltages Va and Vb are set so that the output of 7 becomes high level.
By setting can of detection not or not any signal to the terminal of the horizontal synchronizing signal H _D is input.
The output of the H _D presence detecting circuit 22 (Comp
3) and the outputs (Comp1, Com) of the window comparator circuit 21 for detecting lock / unlock of the PLL circuit.
An abnormal input of the horizontal synchronizing signal can be detected by p2). That has been input any signal to the H _D terminal, PL
If the L circuit is not locked, it can be discriminated that it is not a normal signal, resulting in an abnormal input.

Reference numeral 24 denotes a V _D abnormal input detection circuit for detecting an abnormal input of the vertical synchronizing signal V _D , the details of which are shown in FIG. FIG. 4 shows a circuit for detecting whether a normal signal is input to the vertical synchronizing signal V _D terminal. Figure 5
The operation will be described with reference to FIGS. 5A and 5B. First, when the normal vertical synchronizing signal V _D is input as shown in A of FIG. As shown in FIG. 5 (a), a pulse B of about 25 μsec is output from the rising of the vertical synchronizing signal V _D. When this pulse B is smoothed by the smoothing circuit 59, 25 μsec in one vertical period is very short, and therefore, even if smoothing is performed, FIG.
It becomes almost zero as indicated by C in (a). Therefore, if this is input to the comparator 60, the output is as shown in FIG.
As shown in D of (a), it becomes low level.

[0025] When the abnormal signal of the horizontal synchronizing signal H _D such as shown in A shown in FIG. 5 (b) to the vertical synchronizing signal V _D terminal is inputted, the high-definition mode, as shown in A shown in FIG. 5 (b) One horizontal period is 29.63 μsec, and the output B of the one-shot multivibrator circuit 58 is shown in FIG.
As shown in (b), it rises at the front end of A above,
The pulse has a pulse width of μsec. When this is smoothed by the smoothing circuit 59, as shown in C of FIG.
When the reference voltage Vc is set to about 2V, the output of the comparator 60 can attain a high level as indicated by D in FIG. 5B.

Therefore, it is possible to detect whether the normal vertical synchronizing signal V _D is input to the vertical synchronizing signal V _D terminal or the horizontal synchronizing signal H _{D which} is considered to be an abnormal input. The pulse width of the one-shot multivibrator circuit 58 is set to about 25 μsec because the horizontal period of the high-definition mode is 29.63 μsec.
It must be smaller than this, and if it is too small, the smoothed voltage will be small. Also NTSC-H
In the D converter mode (NTSC signal processed at double speed), the horizontal period is 31.78 μsec.
If a pulse of 5 μsec is smoothed, it is slightly less than 4 V (3.8 to 4.
0V). Therefore, the reference voltage is 0V and 4V
It is preferable to set it to about 2V which is in the middle of the range.

The output Comp1 of the window comparator circuit 21 for detecting the lock / unlock of the PLL circuit.
And Comp2 output Co of the H _D presence detecting circuit 22
The mp3 and the output Comp4 of the V _D abnormal input detection circuit 24 are output to the input port 23, and by observing the signal output to the input port 23 with the control circuit 26, it is possible to determine what signal is input. . That is,
Horizontal as shown in FIG. 6, the vertical synchronizing signal H _D, V _D respectively horizontal synchronizing signal to the terminal H _D and the vertical synchronizing signal V _D is entered correctly, when the PLL is locked each output Comp
1 to 4 are 0, 0, 1, 0, and horizontal and vertical synchronization signals H
_{When D} and V _D are reversely connected, each output Comp1.
4 becomes 0, 1, 1, 1 and can be judged by the control circuit.

Therefore, when it is determined that the connection is reversed, the control circuit 26 first outputs a V _D switching signal for selecting the signal of the internal V _D oscillation circuit 28 to the V _D switching circuit 27. That is, on the terminal a-c of V _D switching circuit 27 when the normal vertical synchronizing signal V _D is inputted, although the vertical synchronizing signal V _D is inputted as it is to the vertical system clock 30 abnormality signal Is input, the INTV _D signal output from the internal V _D oscillation circuit 28 is input to the vertical clock generator 30, and the V _D switching circuit 27 turns on terminals bc. Has become.

[0029] Next, the control circuit 26 is compared with the state of the signal output to the input port 23, when it detects that the horizontal synchronizing signal H _D and the vertical synchronizing signal V _D to the input terminals 5 and 6 are reversely connected A control signal and control data are output to the display circuit 25, and the reversely connected contents are displayed on the display screen while blinking. Further, the control circuit 26 outputs an audio control signal indicating the content of the reverse connection to the audio circuit 32, and notifies the content of the reverse connection by the left speaker 33 and the right speaker 34 by sound.

Furthermore, the LCD high-definition display device has high-definition mode (HD) and NTSC-HD mode (NT
In the case of the double scan method capable of displaying two types of modes (one in which the SC signal is processed at double speed), LE
L for displaying the high-definition mode by the D drive circuit 35
LED37 to display ED36 or NTSC-HD mode
Is selectively driven to display the current mode with an LED. Now, when it is detected by the above circuit that the horizontal and vertical synchronizing signals are reversely connected, the control circuit 26 outputs the L signal.
HD LED 36 of ED circuit 35 and NTSC-HD L
By blinking the ED 37, it is possible to inform that the reverse connection is made by using the LEDs 36 and 37.

With the above configuration, the horizontal,
When the vertical sync signal is reversely connected, the user can be informed of the state displayed by the contents displayed on the screen and blinking or sound of a display device such as an LED. In addition, although the above embodiment describes the liquid crystal high-definition display device, it is not limited to the high-definition display device and can be widely used in the liquid crystal image display device.

[0032]

Since the present invention has the above-described structure, the liquid crystal display panel is damaged even when the vertical synchronizing signal input from the outside becomes abnormal as in the case where the horizontal synchronizing signal and the vertical synchronizing signal are reversely connected. There is nothing to do. In addition, since the abnormality of the vertical synchronizing signal is notified, it becomes easy to deal with the abnormality.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a main part in FIG.

FIG. 3 is an operation explanatory diagram of FIG. 2.

FIG. 4 is a configuration diagram of another main part in FIG.

FIG. 5 is an operation explanatory diagram of FIG. 4;

FIG. 6 is an operation explanatory diagram of FIG. 1.

FIG. 7 is a configuration diagram of a conventional example.

FIG. 8 is an explanatory diagram of a liquid crystal display panel.

FIG. 9 is a configuration diagram of picture elements of a liquid crystal display panel.

FIG. 10 is an operation explanatory diagram of FIG. 8;

11 is an operation explanatory diagram of the PLL circuit in FIG. 7.

12 is an explanatory diagram of the operation of the window comparator circuit in FIG.

13 is an explanatory diagram of the operation of the window comparator circuit in FIG. 7.

14 is an explanatory diagram of the operation of FIG.

[Explanation of symbols]

 2, 3 and 4 Video signal input terminal 5 Horizontal sync signal input terminal 6 Vertical sync signal input terminal 24 Vertical sync signal abnormal input detection circuit 25 Display circuit 26 Control circuit 27 Vertical sync signal switching circuit 28 Internal vertical sync signal oscillation Circuit 31 Liquid crystal display panel 32 Audio circuit 35 LED circuit

Claims (3)

[Claims] 1. A vertical synchronizing signal for detecting that a horizontal synchronizing signal is connected to an input terminal of a vertical synchronizing signal in a liquid crystal image display device having an input terminal capable of separately inputting a video signal and a horizontal and vertical synchronizing signal. Abnormal input detecting means, internal vertical synchronizing signal generating means for internally generating a vertical synchronizing signal, and abnormal input of a vertical synchronizing signal supplied from outside via the input terminal by the vertical synchronizing signal abnormality input detecting means. And a switching means for switching the vertical synchronizing signal for driving the liquid crystal display panel from the signal supplied from the input terminal to the vertical synchronizing signal supplied from the internal vertical synchronizing signal generating means. LCD video display device. 2. The liquid crystal image display device according to claim 1, wherein when the vertical synchronizing signal abnormality input detecting means detects an abnormality in a vertical synchronizing signal externally supplied through an input terminal, the vertical synchronizing signal is detected based on the detected output. A liquid crystal image display device, comprising a notification means for notifying an abnormal input of a synchronization signal. 3. The liquid crystal display device according to claim 1,
When the horizontal sync signal abnormality detecting means for detecting that the vertical sync signal is connected to the input terminal of the horizontal sync signal detects an abnormality of the horizontal sync signal supplied from the outside through the input terminal, or When the synchronization signal abnormality input detection means detects an abnormality in the vertical synchronization signal supplied from the outside through the input terminal, the notification means is provided to notify the abnormality input of each synchronization signal based on the detected output. Liquid crystal image display device characterized by.