JPH0653964A - Serial i/o control system - Google Patents

Abstract

PURPOSE:To provide a serial I/O control system capable of reducing control signal lines on a data bus and easily constituting an output part in the serial I/O. CONSTITUTION:Between the shift register 4 of the serial I/O and a data transmission terminal SOUT, a latch 5 set or reset when a transmission permitting signal SEN outputted from a control circuit 2 is disenabled is provided and output data is turned to 'H' at the time of transmission prohibition. Also, a P channel output inhibiting mode is provided in the data transmission terminal SOUT, 'H' data are outputted after transmission data output completion in the P channel output inhibiting mode and a network is turned to a floating state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial I / O control system which is connected to a large number of networks and used in N-channel open drain.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram showing an example of a conventional serial I / O control method when operating with an internal clock. In the figure, reference numeral 1 is a synchronous clock generation circuit, which outputs a first clock CLK1 as a synchronous clock.
Reference numeral 2 denotes a control circuit for controlling transmission / reception, which outputs a transmission permission signal SEN and a reception permission signal by judging a transmission condition and a reception condition to permit the operation of the synchronous clock generation circuit 1 and also a clock output permission signal. CEN is output and the value of the first clock CLK1 is permitted to be output to the outside. Reference numeral 3 denotes a composite gate as a switching means for generating a second clock CLK2 from the first clock CLK1 output from the synchronous clock generation circuit 1 and the clock output enable signal CEN output from the control circuit 2, and the first clock Whether to output the value of CLK1 to the outside is switched based on the clock output enable signal CEN. 4 is a shift register for shifting the rising data of the second clock CLK2, 5 is a latch for holding data from the "H" input to the next "H" input of the second clock CLK2, 6 is a data bus, 7a, 7b Is C
An output buffer including a MOS buffer, 11a is a 2-input gate circuit which outputs the second clock CLK2 from the composite gate 3 as it is when the transmission enable signal SEN output from the control circuit 2 is "H", and 11b is This is a 2-input gate circuit that inverts and outputs the data TD from the latch 5 when the transmission permission signal SEN is "H". Reference numeral 50 denotes a transmission permission signal line, which is the gate circuits 11a, 1
1b is connected. In addition to the above-mentioned functions, the control circuit 2 counts the output (first clock CLK1) of the synchronous clock generation circuit 1 when, for example, dedicated to clock synchronous serial communication (shift register 4 is used for both transmission and reception), The end of the clock synchronous serial communication is detected by stopping at a predetermined number. Further, by the clock output enable signal CEN, the transmission clock tC
It has a function of setting the output permitted state and the output prohibited state of the LK.

FIG. 10 shows the serial I / O shown in FIG.
2 is a configuration diagram in the case where a plurality of are connected via a network N composed of a clock line 13a and a data line 13b. In the figure, a clock line 13a and a data line 13b
Is pulled up to "H" level via pull-up resistors 12a and 12b. Units SIO1, SIO2 of unit serial I / O commonly connected to the network N composed of the clock line 13a and the data line 13b.
Each SIO3 includes a clock output terminal TCLK connected to the clock line 13a, and a data receiving terminal SIN and a data transmitting terminal SOUT connected to the data line 13b.

FIG. 12 is a block diagram showing a concrete example of the synchronous clock generating circuit 1. In the figure, the same parts as those in FIG. 9 are designated by the same reference numerals and the description thereof will be omitted. In the figure,
C0 is an internal clock such as an IC or a clock input from the outside, and is referred to as an internal clock C0 hereinafter. Reference numeral 14 is a frequency divider that divides the internal clock C0 to output an input clock C1, and 15 is supplied with the input clock C1 that is the output of the frequency divider 14, and based on the transmission enable signal SEN from the control circuit 2, The input clock C1 is divided into two to divide the first clock into the first clock.
It is a 1/2 frequency divider that outputs a clock CLK1. The frequency of the transmission clock tCLK output to the clock line 13a via the clock output terminal TCLK of FIG. 10 is set by dividing the frequency of the internal clock C0 in the synchronous clock generation circuit 1 configured as described above. It
13 is a schematic circuit diagram showing a specific example of the internal configuration of the 1/2 frequency divider 15, and FIG. 17 is a timing diagram of the 1/2 frequency divider 15. In each drawing, the same parts as those in FIG. 12 are designated by the same reference numerals and the description thereof will be omitted. 13 and 17, when the transmission enable signal SEN is "L", the output of the NAND gate 15a in the figure is fixed to "H", and the first clock CLK1 becomes "H". When the transmission enable signal SEN is "H", the output of the NAND gate 15a is inverted every time the input clock C1 rises, and the first clock CLK1 is obtained by dividing the input clock C1 by two.

FIG. 14 is a block diagram showing a concrete example of the shift register 4. In the figure, the same parts as those in FIG. 9 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 14, 1
6 is 1 bit of the shift register 4, 17 is a read buffer, 18 and 19 are OR gates, 20 and 21 are NAND gates forming the first flip-flop FF1, 22 and
Reference numeral 23 is an AND gate, 24 and 25 are NOR gates forming the second flip-flop FF2, and 26 and 27 are NOT gates.
Circuits 41, 42 and 43 are signal lines for a clock signal CLOCK, a write signal WRITE and a read signal READ. When the clock signal CLOCK is "H", the outputs of the OR gates 18 and 19 are "1", and NA
The data of the first flip-flop FF1 formed by the ND gates 20 and 21 is held. Further, since the AND gates 22 and 23 are enabled, the NOR gate 24,
The inverted data of the first flip-flop FF1 is input to the second flip-flop FF2 composed of 25. When the clock signal CLOCK is “L”,
The outputs of the D gates 22 and 23 become "0", the input is prohibited, and the data in the second flip-flop FF2 is held. Further, the OR gates 18 and 19 are enabled, and the input from the data receiving terminal SIN or the upper bit is held in the first flip-flop FF1. To facilitate understanding, FIG. 16 shows data movement timings at points D and E in the internal structure of 1 bit 16 of the shift register 4 shown in FIG. In the shift register 4 of FIG. 14, for example, when the write signal WRITE is set to "1" when the clock signal CLOCK is stopped, the data on the data bus is latched by the first flip-flop FF1. In the state where the data reception from the data receiving terminal SIN is completed and the clock signal CLOCK is stopped, the received data is held at the position of the point E,
By setting the read signal READ to "1", the received data is output on the data bus. Since the received data held at the point E is output to the read signal line 43 based on the read signal READ, the read buffer 17 is configured as an example shown in FIG.

The conventional serial I / O is configured as described above. For example, in FIG. 10, when the unit SIO1 transmits data and the unit SIO2 and the unit SIO3 perform reception, the unit SIO1 transmits the transmission clock tCL.
K is output, and the units SIO2 and SIO3 receive data in synchronization with this transmission clock tCLK. At this time, the clock and data outputs of the units SIO2 and SIO3 must be in a high impedance state. Similarly, when the unit SIO2 outputs data, the units SIO1 and SIO
The clock and data outputs of 3 must be in a high impedance state.

FIG. 11 is an operation timing chart showing an example of a conventional serial I / O control method. Hereinafter, a conventional serial I / O control method will be described with reference to FIGS. In the non-transmission state, the transmission permission signal SEN output from the control circuit 2 is "L". At this time, since the outputs of the gates 11a and 11b are "L", the output buffers 7a and 7b are in the off state, and the clock output terminal TCLK and the data transmission terminal SOUT are in the floating state. At this time, the clock line 13 on the network N
a and the data line 13b are the pro-up resistors 12a and 12b.
Becomes "H" state. In the transmission enable state, the control circuit 2 sets the transmission enable signal SEN to "H" to activate the synchronous clock generation circuit 1 and the gates 11a and 11b. The synchronous clock generation circuit 1 starts its operation when the transmission enable signal SEN becomes "H", and outputs the first clock CLK1. At almost the same time as the transmission permission signal SEN, the control circuit 2
Sets the clock output enable signal CEN to "H" to enable the composite gate 3. The composite gate 3 inverts the first clock CLK1 and outputs it as the second clock CLK2 when the clock output enable signal CEN is "H". First clock C
When LK1 is "L", the second clock CLK2 becomes "H", the gate 11a outputs "H", and the output buffer 7
a is turned on, and "L" is output to the clock output terminal TCLK. Conversely, when the first clock CLK1 is "H", the second clock CLK1
The clock CLK2 becomes "L" and the gate 11a becomes "L".
Is output, the output buffer 7a is turned off, and the clock output terminal TCLK output becomes floating. However, the pull-up resistor 12a of the network N pre-ups it to "H".
It will be in the same state as the output. The shift register 4 shifts data at the rising edge of the second clock CLK2 and latches it.
Output to. The second clock CLK2 of the latch 5 is "H"
The data is latched during the period, and the data is held and output as the data TD until the second clock CLK2 next becomes "H". When the data TD is "L", the output of the gate 11b becomes "H", the output buffer 7b is turned on, and "L" is output to the data transmission terminal SOUT. On the contrary, when the data TD is "H", the output of the gate 11b becomes "L", the output buffer 7b is turned off, and the data transmission terminal SOUT is output.
Becomes a floating state, but becomes equivalent to the case where "H" is output by being pulled up by the pull-up resistor 12b on the network N. The control circuit 2 uses the first clock CLK1
Is counted and, for example, the number of bits of the shift register 4 is n
Then, the clock output enable signal CEN is set to "L" at the rising edge of the nth clock to prevent the clock from being output, and the transmission enable signal SEN is set to "L" at the falling edge of the n + 1th clock to output the clock output terminal. TCLK
Also, the data transmission terminal SOUT is set in a floating state to prohibit the operation of the synchronous clock generation circuit 1. When the transmission enable signal SEN becomes "L", the synchronous clock generation circuit 1 stops its operation when the first clock CLK1 becomes "H". In FIG. 11, the “H” output state of the clock output terminal TCLK and the data transmission terminal SOUT is shown for the sake of convenience, but is externally equivalent to the floating state shown by the broken line.

[0008]

As described above, in the conventional serial I / O control method, the clock output terminal TCLK and the data transmission terminal SOU are generated by the transmission permission signal SEN.
Since T is in a floating state, a signal line such as the signal line 50 of the transmission permission signal SEN is required on the bus line, and gate circuits 11a and 11b are required in front of the output buffers 7a and 7b. There is a problem that the circuit scale of I / O becomes large.

The present invention has been made in order to solve the above-mentioned problems, and does not require the signal line on the bus line and the gate circuits 11a and 11b of the output section.
The purpose is to provide a control system of / O.

[0010]

A serial I according to the present invention.
The control method of / O has a P channel output prohibition mode in the data transmission terminal SOU, and outputs "H" data after the transmission data output is completed in this P channel output prohibition mode to put the network N in a floating state.

The serial I / O control method according to the present invention is a latch 5 which is set or reset when the transmission enable signal SEN output from the control circuit 2 is disabled between the shift register 4 and the data transmission terminal SOUT.
Is provided so that the output data becomes “H” when the transmission is prohibited.

The serial I / O control method according to the present invention is a transmission shift register 9 and a reception shift register 28.
In addition, the input of the transmission shift register 9 is fixed to "H", and "H" data is output after the transmission data output is completed.

The serial I / O control method according to the present invention is a transmission shift register 9 and a reception shift register 28.
And the stop bit generation circuit 8 is input, the output "H" of the stop bit generation circuit 8 is input to the transmission shift register 9, and the stop bit "H" is output after the transmission data is output.

[0014]

In the serial I / O control method according to the present invention, the data transmission terminal SOUT has the P channel output prohibition mode, so that the "L" data output to the network N is prohibited and the "H" data is prohibited. Can be output to bring the network N into a floating state.

In the serial I / O control method according to the present invention, the latch 5 provided between the shift register 4 and the data transmission terminal SOUT is set or reset when the transmission enable signal SEN is disabled. The output data can be made "H" when the transmission is prohibited.

In the serial I / O control method according to the present invention, by fixing the input of the transmission shift register 9 to "H", "H" data can be output after the completion of transmission data output.

In the serial I / O control system according to the present invention, the output "H" of the stop bit generation circuit 8 is input to the transmission shift register 9 to output the stop bit "H" after the transmission data is output. be able to.

[0018]

EXAMPLES Example 1. An embodiment of a serial I / O control method according to the present invention is shown in FIG. In the figure, the same parts as those in FIG. 9 of the related art are designated by the same reference numerals and the description thereof is omitted. In the figure, the latch 5 is configured to be in a reset state and output "L" when the transmission enable signal SEN supplied from the control circuit 2 through the signal line 51 is "L". Also, C
The second clock CLK1 and the data TD are supplied to the inputs of the output buffers 7a and 7b, which are MOS buffers, respectively. Further, the serial I / O according to the present invention
Has a P channel output prohibit mode at the data transmission terminal SOUT. The P-channel output prohibit mode is a well-known function provided in the data transmission terminal for prohibiting P-channel output of a CMOS buffer or the like depending on the application when the I / O port is also used as the serial I / O. is there. When the serial I / O according to the present invention is used by connecting to a plurality of networks N as in the conventional example, the P channel output such as a CMOS buffer is turned on and "L" data is output on the network N. In order to prevent this, after the transmission data output is completed in the P channel output prohibition mode, "H" data is output and the network N is put in a floating state.

FIG. 2 shows an operation timing chart for explaining this embodiment. The control method of serial I / O in this embodiment will be described below with reference to FIGS. The control circuit 2 is the Nth first clock CL shown in FIG.
When K1 is counted, the clock output enable signal CEN is set to "L". The composite gate 3 is supplied with the clock output enable signal CEN of "L", the second clock CLK2 becomes "L", the output buffer 7a is turned off, and the clock output terminal TCLK becomes floating. The control circuit 2 causes the (n + 1) th first clock CLK shown in FIG.
When 1 is counted, the latch 5 of FIG. 1 is reset by setting the transmission enable signal SEN to "L", and the data T
"L" is output to D. When the data TD is “L”,
Since the output buffer 7b is turned off, the data transmission terminal SO
The UT becomes floating. At this time, the data transmission terminal SOUT is in the P channel output prohibition mode,
Although the output of "L" data is prohibited and the output becomes floating, it becomes equivalent to the case where "H" is output by being pulled up on the network N by the pull-up resistor 12b shown in FIG. The clock output terminal TCL shown in FIG.
The K and "H" output states of the data transmission terminal SOUT are shown in practice for convenience, but are externally equivalent to the floating state shown by the broken line.

According to this embodiment, since the output to the network N can be controlled to be turned on and off only by the data,
The gate size of the serial I / O can be reduced without using the gate circuits 11a and 11b of the conventional example.

Example 2. Another embodiment of the serial I / O control system according to the present invention is shown in FIG. In the figure, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. FIG. 3 shows an example in which the present invention is applied to a serial I / O of a shared type for clock synchronous serial communication and asynchronous serial communication. The serial I / O transmission unit includes a transmission clock generation circuit 1a, a transmission control circuit 2a, and a transmission shift register 9
However, the reception clock generation circuit 1b, the reception control circuit 2b, and the reception shift register 28 are separately provided in the reception unit, and the transmission shift register 9 has stop bits used for asynchronous serial communication. A generation circuit 8 is provided. 10 is the first clock CLK
It is an inverting circuit for inverting 1 and supplying it to the stop bit generating circuit 8, the transmission shift register 9, and the latch 5. In FIG. 3, 29 is a control bit for switching between clock synchronous serial communication and asynchronous serial communication, and 3
0 is the second clock C according to the output of the control bit 29.
This is a reception clock switching circuit that switches between LK2 and the output CLK3 of the reception clock generation circuit 1b and supplies it to the reception register 28 as the reception clock RCLK.

The operation of switching between clock synchronous serial communication and asynchronous serial communication in this embodiment will be described. For example, when the content of the control bit 29 is set to "0" and clock synchronous serial communication is selected, the reception clock switching circuit 30 causes the second clock CLK2
To enable. At this time, the reception clock RCLK has the same phase as the transmission clock tCLK. Also, control bit 2
When the content of 9 is set to “1” and the asynchronous serial communication is selected, the reception clock switching circuit 30 validates the third clock CLK3 which is the output of the reception clock generation circuit 1b,
Transmission and reception are independent and operate asynchronously. At this time, the third
The clock CLK3 and the reception clock RCLK have the same phase. Further, when the reception control circuit 2b receives the start bit of asynchronous serial communication from the data reception terminal SIN, it outputs the reception permission signal REN to the reception clock generation circuit 1b to start the operation of the reception clock generation circuit 1b.

Here, the function of the stop bit generating circuit 8 will be described. Conventionally, two methods can be considered as a method of stopping the transmission clock tCLK output by the serial I / O at a predetermined number. In the first method, a counter is provided in the transmission control circuit 2a and the transmission clock t
CLK or the second clock CLK2 or the first clock
There is a method of directly counting the clock CLK1 and stopping the transmission clock generation circuit 1a when the number of clocks reaches a predetermined number. The second method is to lower the lower bits of the transmission data in the transmission shift register 9 when the transmission is stopped. This is a method of setting a predetermined value by a control signal such as CEN and stopping the transmission clock generation circuit 1a when the contents of all bits of the transmission shift register 9 become the same by the transmission clock tCLK. The first method described above has a small number of bits of the counter when the number of clocks can be converted into a binary number as in the case of 8-bit clock synchronization. For example, in the case of 8 bits, the overflow of the 3-bit counter can be used as an end signal, However, if the number of clocks changes depending on the mode, such as asynchronous serial communication, the number of bits in the counter will increase, and the number of clocks required for each mode will be decoded from the counter to generate the end signal. However, there is a drawback that the circuit pattern becomes large. Since the second method is premised on the second embodiment, the stop bit generation circuit 8 is composed of a shift register having a reset function or an initial setting function.

By constructing the transmission shift register 9 from this type of shift register, the second method is carried out as shown in the schematic diagrams of FIGS. FIG. 5 shows when transmission is stopped (before transmission), and FIG. 6 shows when transmission is completed. Figure 5,
In FIG. 6, SB1 and SB2 are stop bits and PB.
Is a parity bit, STB is a start bit, 5 is the above latch, 9 is a transmission shift register having a reset function, and 60 is a gate circuit which outputs the content of each bit and outputs a transmission end signal F based on its predetermined value. is there. The broken line arrow in the drawing indicates that the bypass circuit can be bypassed by selecting the number of stop bits (2 or 1), the presence or absence of parity, etc. according to the transmission mode. When the transmission is started from the state of FIG. 5, the transmission data is sequentially shifted, and the start bit STB, the 8-bit data D0 to D7, the parity bit PB, the stop bit SB.
Among the bits 1 and SB2, the bits lower than the transmission data are sequentially reset to a predetermined value (for example, "0"). The gate circuit 60 of FIG. 6 is supplied with the values of these bits (all “0” in FIG. 6) and the inversion of the transmission clock, and the final gate 60a of this gate circuit 60 supplies the value of the stop bit SB1 (for example, “0”). 1 ") is detected, the transmission end signal F is enabled, and the transmission control circuit 2a supplied with the transmission end signal F sets the transmission enable signal SEN to" L "to stop the transmission clock generation circuit 1a and The output enable signal CEN also becomes "L",
Output of the transmit clock is prohibited.

In the present embodiment, the stop bit generation circuit 8 is made effective also in the case of clock synchronous serial communication,
After the data transmission is completed, the first clock C that is not output to the outside
By outputting a stop bit by the inversion clock of LK1, "H" is output to the network N to bring it into a floating state. In the example shown in FIG. 6, the stop bit SB1 is used as the end detection data, but the final data TD can always be "H" by using the two stop bits SB1 and SB2.

The operation of the clock synchronous serial communication in this embodiment is the same as in the first embodiment. This is almost the same as the above, and the different points will be described below. In addition, in order to facilitate comparison with FIG. 2,
FIG. 4 shows an example of an operation timing chart of data transmission by clock synchronous serial communication in this embodiment. In the figure, the same parts as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted. When the predetermined value of the stop bit SB1 is detected by the control method shown in FIGS. 5 and 6 and the output of the transmission clock is prohibited, the value of the stop bit SB2 is changed by the inverted clock of the (n + 1) th first clock CLK1. Is output to the data TD, and the network N is brought into a floating state.

According to this embodiment, the conventional gate circuits 11a and 11b are provided on the bus line of the serial I / O transmitter.
Becomes unnecessary, and the signal line 50 of the transmission permission signal SEN
Becomes unnecessary, and the circuit scale can be reduced.

Example 3. Another embodiment of the serial I / O control method according to the present invention is shown in FIG. In the figure, the same parts as those in FIGS. 1 and 3 are designated by the same reference numerals and the description thereof will be omitted. In the figure, 40 is a switch for switching the input of the shift register 4 between the data receiving terminal SIN and "H" data input, and 41 is a power supply for supplying "H" data.

When serial communication is performed in the conventional network N shown in FIG. 10, the transmitting serial I / O only receives the data transmitted by itself from the data receiving terminal SIN. Therefore, the data receiving terminal SIN is not always required. It may not be connected to the shift register 4. When transmitting, the input of the shift register 4 is connected to the “H” data input by switching the switch 40, and after the data transmission is completed, the clock CLK1 that is not output to the outside
This "H" input data is output by the inversion clock of. As a result, "H" can be output to the network N to bring it into a floating state, and the same effect as that of each of the above embodiments can be obtained.

In this embodiment, the input may be fixed at "H" only when data is transmitted. In the case of data reception, the transmission unit becomes high impedance by setting the transmission data to all bits "H". Therefore, when writing the transmission data to the shift register 4, check whether the written data is all bits "H". Then, the input may be switched according to the result. FIG. 8 is a configuration diagram showing a specific example of the input switching circuit for performing the above procedure. In the figure, 42 is an AND circuit, 43 is a latch, 44 is an input switching circuit, and 45 is a shift register write signal line. The input switching circuit 44 makes the input data of the data receiving terminal SIN valid only when the data written in the shift register 4 is all "H". When all the bits are not "H", the input of the shift register 4 is fixed to "H". Further, when bit control is performed for transmission and reception, if the latch 43 is configured by a programmable control bit, the AND circuit 42 input to the latch 43 becomes unnecessary. When the data of all bits “H” is output as the transmission data, the network N is in a floating state after the transmission is completed because the final transmission data is “H”. When reception and transmission are performed by the same shift register 4, since the end detection cannot be performed by the internal data as described above, the end detection is performed by the counter in the control circuit 2. Therefore, in the case of data transmission, if the number of transmission clocks tCLK is n and the first clock CLK1 is configured as n + 1 as shown in FIG. 2, the "H" data first captured by the shift register is the final data. , And the network N stops in a floating state.

[0031]

According to the invention of claim 1, the data transmission terminal has the P channel output prohibition mode, and in the P channel output prohibition mode, "H" data is outputted after the transmission data output is completed, and the network is floated. Since it is in the state, the gate circuit of the output section is unnecessary and the circuit scale of the serial I / O can be reduced.

According to the second aspect of the present invention, a latch that is set or reset when the transmission enable signal output from the control circuit is disabled is provided between the shift register and the data transmission terminal. Since it is configured to be "H", the gate circuit of the output section is unnecessary, and the serial I / O circuit scale can be reduced.

According to the third aspect of the present invention, the transmission shift register and the reception shift register are provided, the input of the transmission shift register is fixed to "H", and "H" data is output after the transmission data output is completed. With this configuration, the gate circuit of the output section is not required, the number of signal lines on the bus line is reduced, and the circuit scale of the serial I / O can be reduced.

According to the invention of claim 4, the transmission shift register, the reception shift register, and the stop bit generation circuit are provided, and the output "H" of the stop bit generation circuit is input to the transmission shift register for transmission. Since the stop bit "H" is output after the data is output, the wiring on the bus line can be reduced, the gate circuit of the output section can be omitted, and the configuration can be simplified to reduce the serial I / O circuit scale. realizable.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a serial I / O control system according to the present invention.

FIG. 2 is an operation timing chart for explaining the embodiment of FIG.

FIG. 3 is a block diagram showing another embodiment of the serial I / O control method according to the present invention.

FIG. 4 is an operation timing chart for explaining the embodiment of FIG.

FIG. 5 is a schematic diagram showing when transmission is stopped in a specific example of a stop bit generation circuit according to the present invention.

FIG. 6 is a schematic diagram showing the end of transmission in a specific example of a stop bit generation circuit according to the present invention.

FIG. 7 is a block diagram showing another embodiment of the serial I / O control method according to the present invention.

FIG. 8 is a configuration diagram showing a specific example of an input switching circuit according to the present invention.

FIG. 9 is a block diagram showing an example of a conventional serial I / O control method.

FIG. 10 is a configuration diagram when a plurality of conventional serial I / Os are connected via a network.

FIG. 11 is an operation timing chart for explaining a conventional serial I / O control method.

FIG. 12 is a block diagram showing a specific example of a conventional synchronous clock generation circuit.

13 is a schematic circuit diagram showing an example of an internal configuration of the 1/2 frequency divider shown in FIG.

FIG. 14 is a block diagram showing a specific example of a conventional shift register.

15 is a circuit diagram showing an example of an internal configuration of the read buffer shown in FIG.

FIG. 16 is a diagram showing a data movement timing in a specific example of a conventional shift register.

FIG. 17 is a timing chart for explaining the operation of the ½ frequency divider shown in FIG.

[Explanation of symbols]

 1 Synchronous clock generation circuit 2 Control circuit 3 Composite gate 4 Shift register 5 Latch SOUT Data transmission terminal SEN Transmission enable signal

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[Procedure amendment]

[Submission date] November 2, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 1

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0002

[Correction method] Change

[Correction content]

[0002]

2. Description of the Related Art FIG. 9 is a block diagram showing an example of a conventional serial I / O control method when operating with an internal clock. In the figure, reference numeral 1 is a synchronous clock generation circuit, which outputs a first clock CLK1 as a synchronous clock.
Reference numeral 2 denotes a control circuit for controlling transmission / reception, which outputs a transmission / reception permission signal SEN by judging transmission conditions and reception conditions, permits the operation of the synchronous clock generation circuit 1 and outputs a clock output permission signal CEN. , Above first
Permitting the value of the clock CLK1 to be output to the outside. Reference numeral 3 denotes a second clock CLK2 based on the first clock CLK1 output from the synchronous clock generation circuit 1 and the clock output enable signal CEN output from the control circuit 2.
With a composite gate as a switching means for generating, the value of the first clock CLK1 is switched to the outside or not based on the clock output enable signal CEN. Reference numeral 4 is a shift register for shifting the rising data of the second clock CLK2, and 5 is the second clock CL.
A latch for holding data from the "H" input of K2 to the next "H" input, 6 is a data bus, 7a and 7b are output buffers including CMOS buffers, and 11a is the transmission enable signal SEN output from the control circuit 2. Is "H", a 2-input gate circuit that outputs the second clock CLK2 from the composite gate 3 as it is, 11b is a transmission enable signal SE
This is a 2-input gate circuit that inverts and outputs the data TD from the latch 5 when N is "H". Also, 50
Is connected to the gate circuits 11a and 11b by a transmission permission signal line. In addition to the above-mentioned functions, the control circuit 2 counts the output (first clock CLK1) of the synchronous clock generation circuit 1 when, for example, dedicated to clock synchronous serial communication (shift register 4 is used for both transmission and reception), The end of the clock synchronous serial communication is detected by stopping at a predetermined number. Further, it has a function of setting the output enable state and the output disable state of the transmission clock tCLK by the clock output enable signal CEN.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction content]

FIG. 11 is an operation timing chart showing an example of a conventional serial I / O control method. Hereinafter, a conventional serial I / O control method will be described with reference to FIGS. In the non-transmission state, the transmission permission signal SEN output from the control circuit 2 is "L". At this time, since the outputs of the gates 11a and 11b are "L", the output buffers 7a and 7b are in the off state, and the clock output terminal TCLK and the data transmission terminal SOUT are in the floating state. At this time, the clock line 13 on the network N
a and the data line 13b are pull-up resistors 12a and 12b.
Becomes "H" state. In the transmission enable state, the control circuit 2 sets the transmission enable signal SEN to "H" to activate the synchronous clock generation circuit 1 and the gates 11a and 11b. The synchronous clock generation circuit 1 starts its operation when the transmission enable signal SEN becomes "H", and outputs the first clock CLK1. At almost the same time as the transmission permission signal SEN, the control circuit 2
Sets the clock output enable signal CEN to "H" to enable the composite gate 3. The composite gate 3 inverts the first clock CLK1 and outputs it as the second clock CLK2 when the clock output enable signal CEN is "H". First clock C
When LK1 is "L", the second clock CLK2 becomes "H", the gate 11a outputs "H", and the output buffer 7
a is turned on, and "L" is output to the clock output terminal TCLK. Conversely, when the first clock CLK1 is "H", the second clock CLK1
The clock CLK2 becomes "L" and the gate 11a becomes "L".
Is output, the output buffer 7a is turned off, and the clock output terminal TCLK output becomes floating. However, the pull-up resistor 12a of the network N pre-ups it to "H".
It will be in the same state as the output. The shift register 4 shifts data at the rising edge of the second clock CLK2 and latches it.
Output to. The second clock CLK2 of the latch 5 is "H"
The data is latched during the period, and the data is held and output as the data TD until the second clock CLK2 next becomes "H". When the data TD is "L", the output of the gate 11b becomes "H", the output buffer 7b is turned on, and "L" is output to the data transmission terminal SOUT. On the contrary, when the data TD is "H", the output of the gate 11b becomes "L", the output buffer 7b is turned off, and the data transmission terminal SOUT is output.
Becomes a floating state, but becomes equivalent to the case where "H" is output by being pulled up by the pull-up resistor 12b on the network N. The control circuit 2 uses the first clock CLK1
Is counted and, for example, the number of bits of the shift register 4 is n
Then, the clock output enable signal CEN is set to "L" at the rising edge of the nth clock to prevent the clock from being output, and the transmission enable signal SEN is set to "L" at the falling edge of the n + 1th clock to output the clock output terminal. TCLK
Also, the data transmission terminal SOUT is set in a floating state to prohibit the operation of the synchronous clock generation circuit 1. When the transmission enable signal SEN becomes "L", the synchronous clock generation circuit 1 stops its operation when the first clock CLK1 becomes "H". In FIG. 11, the “H” output state of the clock output terminal TCLK and the data transmission terminal SOUT is shown for the sake of convenience, but is externally equivalent to the floating state shown by the broken line.

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Claims (4)

[Claims] 1. A synchronous clock generating circuit, a switching means for switching whether or not to output the synchronous clock output from the synchronous clock generating circuit to the outside, and a data shift on the network in synchronization with the synchronous clock. In a serial I / O provided with a shift register for outputting and a control circuit for outputting a transmission permission signal and a reception permission signal by judging a transmission condition and a reception condition and permitting the operation of the synchronous clock generation circuit. Serial I / O, characterized in that it has a P-channel output prohibit mode at the data transmission terminal and outputs "H" data after the completion of transmission data output in the P-channel output prohibit mode to put the network in a floating state. Control method. 2. A latch which is set or reset when the transmission enable signal output from the control circuit is disabled is provided between the shift register and the data transmission terminal so that output data becomes "H" when transmission is prohibited. The serial I / O control method according to claim 1, wherein 3. A transmission shift register and a reception shift register are provided, wherein the input of said transmission shift register is fixed to "H", and "H" data is output after completion of transmission data output. The serial I / O control method according to claim 1, wherein 4. A transmission shift register, a reception shift register, and a stop bit generation circuit, wherein the output “H” of the stop bit generation circuit is input to the transmission shift register, and after the transmission data is output, the stop bit “H” is output. The serial I / O control method according to claim 1, wherein H "is output.