JPH0653499A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the gate length of gate electrode in a transistor for checking the characteristics placed on the periphery of a chip from thining as compared with the gate length of transistor constituting an internal circuit of the chip. CONSTITUTION:Diffusion layer 2 of a characteristics checking transistor placed on the periphery of a chip 3 has area equal to that of the diffusion layer of a transistor constituting inner circuit. Consequently, gate length of a gate electrode 1 can be matched stably with the gate length of a transistor constituting an inner circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a characteristic checking transistor in the peripheral portion of a chip.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional characteristic checking transistor exists independently in the peripheral portion of a chip 3, and has a threshold voltage V _T and an on-current I which are important indicators of semiconductor characteristics.
_ON , gate length L, etc. are measured. Reference numeral 1 is a gate electrode, and 2 is a diffusion layer.

The transistor built inside the chip is
Since various circuits are configured respectively, at the end of the previous process, V
Important parameters such as _T , I _ON and L cannot be directly measured.

By the way, the values of V _T , I _ON and L obtained by measuring the characteristic checking transistor have been used as values for simulation and the like.

On the other hand, when the chip size is reduced in order to improve the chip performance, the transistors inside the chip forming the circuit are also reduced. However, since the check transistor existing in the peripheral portion of the chip is independent of the circuit, it hardly changes.

As a result, the gate width W of the checking transistor is 3 as compared with the transistor forming the internal circuit.
It has four times the size.

The gate electrode is patterned as shown in FIG. That is, first, after forming the field oxide film 6 on the silicon substrate 7, the polycrystalline silicon 5 is grown and the photoresist 4 is applied (FIG. 4A). After that, the photoresist 4 is exposed and developed to pattern the gate electrode (FIG. 4B). Further, etching is performed by RIE to form a gate electrode of polycrystalline silicon (FIG. 4).
(C)). After the etching is completed, the photoresist is removed.

[0008]

In the conventional characteristic checking transistor, the area of the diffusion layer is 10 times or more that of the transistor inside the chip. Therefore, when the gate electrode 1 is formed by patterning the polycrystalline silicon 5 with the photoresist 4 as shown in FIG. 4, the area of the diffusion layer 2 formed between the field oxide films 6 is large in the characteristic checking transistor. Therefore, the photoresist 4 becomes thin on the diffusion layer in FIG. 4A, and when the photoresist 4 is exposed in FIG. 4B, overexposure occurs and the gate length on the photoresist becomes thin.

As a result, when etching by RIE, the gate length L of the transistor having a small diffusion layer inside the chip is L.
And the gate length L of the characteristic checking transistor,
There is a problem that L of the characteristic checking transistor becomes thin by about 0.1 μm.

An object of the present invention is to provide a semiconductor device in which the gate length of the characteristic checking transistor is prevented from becoming smaller than the gate length of the circuit constituting transistor inside the chip.

[0011]

In order to achieve the above-mentioned object, a semiconductor device according to the present invention is a semiconductor device in which a characteristic checking transistor is provided in a peripheral portion of a chip, and a diffusion layer of the characteristic checking transistor is provided. Has an area equal to that of a diffusion layer of a transistor forming a circuit inside the chip.

[0012]

Since the characteristic checking transistor has the same diffusion layer area as the transistor existing inside the chip, the gate lengths of both transistors are the same and stable characteristics are exhibited.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a plan view showing Embodiment 1 of the present invention. In FIG. 1, the gate electrode 1 of the characteristic checking transistor is formed in the peripheral portion of the chip 3. Further, the diffusion layer 2 of the characteristic checking transistor has the same area as that of the circuit forming transistor inside the chip 3.

By using the diffusion layer having this structure, it is possible to prevent thinning of the resist when applying the photoresist,
The gate length L will be stabilized.

(Second Embodiment) FIG. 2 is a plan view showing a second embodiment of the present invention. In this embodiment, the diffusion layer 2 of the characteristic checking transistor is formed in an elongated shape. With the structure of the diffusion layer 2 shown in FIG. 2, the gate length L is stabilized and the gate width W remains large. Of course, in this case, the diffusion layer 2 of the characteristic checking transistor has the same area as that of the circuit forming transistor inside the chip 3.

Therefore, there is an advantage that the stabilization of the gate length L can be ensured and the previously measured data such as the _ON current I _ON can be used as it is.

[0018]

As described above, according to the present invention, since the characteristic checking transistor existing in the peripheral portion of the chip has the same diffusion layer area as the transistor forming the circuit inside the chip, the gate length thereof is set to the inside of the chip. The effect is that the gate length of the transistor can be stably matched.

[Brief description of drawings]

FIG. 1 is a plan view showing a first embodiment of the present invention.

FIG. 2 is a plan view showing a second embodiment of the present invention.

FIG. 3 is a plan view showing a conventional example.

FIG. 4 is a cross-sectional view showing a manufacturing process for forming a gate electrode.

[Explanation of symbols]

 1 gate electrode 2 diffusion layer 3 chip 4 photoresist 5 polycrystalline silicon 6 field oxide film 7 silicon substrate

Claims (1)

[Claims] 1. A semiconductor device having a characteristic checking transistor provided in the peripheral portion of a chip, wherein a diffusion layer of the characteristic checking transistor has an area equal to that of a transistor forming a circuit inside the chip. A semiconductor device characterized by: