JPH0653276A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To mount semiconductor chips at higher density and improve heat conductivity and perform property test easily, concerning a semiconductor device where a plurality of semiconductor chips are arranged in three dimensions. CONSTITUTION:A semiconductor chip 32 is positioned in the opening of a tape carrier 34, and the electrode pads 33a of the semiconductor chips 32 and the connection leads 38 made intensively at one side of the tape carrier 34 are electrically connected. And, test pads 39 are made respectively at the ends of the connection leads 38.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a plurality of semiconductor chips are three-dimensionally arranged.

In recent years, in order to increase the capacity and increase the density of semiconductor devices, a semiconductor device in which semiconductor chips are three-dimensionally arranged to increase the density is being developed. Further, it is desired to increase the density and to improve various conditions such as insulation.

[0003]

2. Description of the Related Art Conventionally, as a semiconductor chip having a plurality of semiconductor chips arranged three-dimensionally, one described in US Pat. No. 5,025,306 (hereinafter, referred to as a first conventional example), 4706166 (hereinafter, referred to as a second conventional example) is known. Are known.

Therefore, FIG. 5 shows a diagram for explaining a conventional semiconductor device having a three-dimensional structure. The semiconductor device 11 of FIG.
In the first conventional example, a film 13 of insulating adhesive polyimide or the like is provided on a semiconductor chip 12 having an electrode 12a formed on the surface thereof, and a predetermined wiring 14a is patterned on the film 13. The formed tape lead 14 of polyimide or the like is provided.

The electrode 12a of the semiconductor chip 12
And one end of the wiring 14a on the corresponding tape lead 14 are electrically connected by the bump 16 (see FIG. 6) to form one element. In this case, the other end of the wiring 14a becomes a lead for external connection.

FIG. 6 shows a diagram for explaining the structure of one chip shown in FIG. As shown in FIG. 6A, the tape lead 14 is fixed on the semiconductor chip 12 via the film 13. At this time, the tape lead 14
One end 14b of the upper wiring 14a is gathered on one side of the semiconductor chip 12, and the other end 14c is electrically connected to the electrode 12a on the semiconductor chip 12 via the bump 16.

In this case, as shown in FIG. 6B, the tape lead 14 is adhered onto the film 13, and as shown in FIG. 6C, the wiring 14a is adhered onto the film 13. There are cases.

Returning to FIG. 5, a plurality of elements formed as shown in FIG. 6 are formed, each of which is three-dimensional (three-dimensional) via a spacer 15 of an insulating adhesive film such as polyimide. The three-dimensionally mounted semiconductor device 11 is formed.

Therefore, FIG. 7 is a diagram for explaining the assembly and mounting of FIG. As shown in FIG. 7A, the semiconductor device 11 mounted three-dimensionally in FIG. 5 is in a state in which the end portions 14c of the wiring 14a are arranged on the one surface 17 and led out. When the end face of this one face 17 is polished, as shown in FIG. 7B, a rectangular parallelepiped semiconductor device (module) 11 in which the end faces of the end portions 14c of the wiring 14a are exposed in an array on the surface.
Is formed. That is, in the semiconductor device 11 of the three-dimensional module, the tape leads 14 are used to lead out the electrical connection leads from the electrodes 12 a on the semiconductor chip 12 to one end portion.

Then, as shown in FIG. 7C, a plurality of semiconductor devices 11 are mounted on the mother board 18. As shown in FIG. 7D, the mother board 18 has a substrate 18
The pad 18c is formed on the wiring layer 18b laminated on the a, and the pad 18c and the wiring 14 of the semiconductor device 11 are formed.
The end portion 14c is mounted by welding.

Next, FIG. 8 shows a diagram for explaining another conventional semiconductor device having a three-dimensional structure. The semiconductor device 21 of FIG. 8A is shown in the above-described second conventional example, and the semiconductor chip 22 is formed by collecting electrical wirings 22a at one end in advance. A plurality of the semiconductor chips 22 are stacked with an adhesive or the like to form the semiconductor device 21, and the surface of the wiring 22a serves as an access surface, and the cross section of the wiring 22a is exposed in an array.

This state is shown in FIGS. 8B and 8C,
If the same semiconductor chips 22 are stacked, the wiring 22
The arrangement configuration of a is the same, and the same signal line (for example, a power supply line or a ground line) is arranged linearly in the stacking direction.

Therefore, it becomes easy to form the linear bus line 22b (FIG. 8B) between the same wirings 22a. That is, the wiring 22a is etched so as to project from one side of the semiconductor chip 22, an insulating coating is applied on the wiring 22a, and only the desired wiring material is lithographically exposed to form a stacked bus line 22b by vapor deposition or the like. It is for mutual connection.

Therefore, FIG. 9 shows a diagram for explaining the mounting of FIG.

A semiconductor device 21 in which the semiconductor chips 22 are stacked and modularized as described above is shown in FIG.
9B, the state of the assigned signal line on the surface of the wiring 22a is shown in FIG.

Then, the surface of the wiring 22a of the modularized semiconductor device 21 is mounted on a mother board (FIG. 9 (C)) 23 having a predetermined pattern formed thereon, and is connected to the pattern by bumps or the like. It is mounted (FIG. 9 (D)).

[0017]

However, in the first conventional example (FIG. 5), the wiring 22a is led out on the semiconductor chip 22 by the tape lead 14, so that when the three-dimensional module is formed, the stacked semiconductor chips are stacked. It is difficult to improve the degree of integration due to the insulating spacer 15 between 22.

Further, since the above-mentioned tape lead 14 is generally made of polyimide, there is a problem that the thermal conductivity of each semiconductor chip 22 is lowered and the heat dissipation is poor due to the modularization.

Further, in the above-mentioned semiconductor device 11, there is a problem that it is not possible to measure the characteristics of each semiconductor chip 22 in advance and select only good products.

On the other hand, since the semiconductor device 21 of the second conventional example (FIGS. 8 and 9) is stacked in a bare chip state, it is not possible to perform a sufficient individual electrical test. Therefore, in the case of a high-density module including a large number of semiconductor chips 22, non-defective chips cannot be selected in advance, leading to a reduction in yield. For this reason, it is possible to incorporate a redundant element in advance and invalidate the defective element in the test of the entire module, but there is a problem that the number of steps becomes complicated and it is not suitable for mass production.

Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device having a higher density, good heat conduction, and an easy characteristic test.

[0022]

SUMMARY OF THE INVENTION The above-mentioned problems are solved by packaging semiconductor chips having a predetermined number of electrode pads arranged in a predetermined number in a three-dimensional manner, and arranging them on one side surface of the package from the electrode pads. In the semiconductor device in which the end surface of the connection lead is exposed, a predetermined portion is opened to position the semiconductor chip, and the end portion of the connection lead connected to the electrode pad is formed on one side. This can be solved by providing each tape carrier, and can be solved by appropriately forming a test pad for testing the semiconductor chip at the end of the connection lead of the tape carrier.

[0023]

As described above, the semiconductor chip is located in the opening portion of the tape carrier, and the electrode pads of the semiconductor chip and the connection leads collectively formed on one side of the tape carrier are electrically connected. Then, a plurality of these are stacked and packaged, and the end faces of the connection leads are exposed on one side surface of the package.

That is, when stacking the semiconductor chips, it is not necessary to interpose a spacer or the like between the chips, so that it is possible to improve the heat conduction, thereby increasing the number and increasing the density. Become.

Further, since the test pads are formed at the ends of the connection leads of the tape carrier, it is possible to easily perform the characteristic test of each semiconductor chip even after stacking.

[0026]

FIG. 1 is a block diagram of the first embodiment of the present invention. In FIG. 1A, on the semiconductor chip 32 such as a highly integrated memory, the electrode pads 3 gathered on one side.
A predetermined number of 3a are formed, and, for example, two holding pads 33b are formed at both ends of the opposite side.

On the other hand, in FIG. 1B, the both ends of the tape carrier 34 made of, for example, polyimide are
The sprocket holes 35a are formed, and the guide holes 35b are formed at the four corners. Also, tape carrier 3
4, an opening 36 is formed in the central portion, and holding leads 37 extending at both ends (preferably two) of one side of the opening 36 are formed, and a predetermined number (semiconductor chip) is formed on the opposite side. Corresponding to the number and position of 32 electrode pads 33a)
Connection leads 38 are formed so as to extend and are gathered on one side of the tape carrier 34. Then, the test pad 3 is attached to the end portion of the connection lead 38 on the tape carrier 34.
9 are formed respectively. The connecting lead 38 is C
Sn (tin) plating is applied on the u (copper) foil.

Therefore, in FIG. 1C, the semiconductor chip 32 is positioned in the opening 36 of the tape carrier 34, and the ends of the holding leads 37 and the holding pads 33b are connected and fixed by thermocompression bonding with solder bumps or the like. And the end of each connection lead 38 and the electrode pad 33a are
It is electrically connected and fixed by thermocompression bonding with a u (gold) bump or the like. As a result, one semiconductor element 40 is formed.

In the above embodiment, the electrode pad 33a is used.
Although the case where the above is formed on only one side of the semiconductor chip 32 is shown, it may be formed on the opposite side or the adjacent side. In this case, the connection leads 38 on the tape carrier 34 are laid and gathered on one side. Further, in this way, the holding pad 33b and the holding lead 37 can be omitted.

The semiconductor element 40 thus formed is
The test pads 39 on the tape carrier 34 can be utilized to perform a complete electrical characterization test. With this,
Burn-in, high temperature test, and low temperature test can also be performed. That is, it is possible to perform a characteristic test on the tape carrier 34 before the individual semiconductor chips 32 are stacked.

Next, FIG. 2 shows a view for explaining the case of stacking in FIG. 2A, the semiconductor element 40 in FIG. 1 has an insulating layer 41 made of epoxy resin or the like on the surface of the semiconductor chip 32 (the surface on which the electrode pads 33a are formed). Then, these semiconductor elements 40 are attached to the guide holes 35 formed in the tape carrier 34.
A plurality of layers are aligned and stacked by b. That is, the insulating layer 41 is intended to insulate the semiconductor chips 32 from each other.

In this case, the spacers 42 are arranged between the tape carriers 34 so that the vertical pitches of the connection leads 38 in the semiconductor element 40 are accurate.

Then, the periphery of the semiconductor chips 32 of the stacked semiconductor elements 40 is molded with a molding resin 43 to perform packaging. Subsequently, the holding lead 37 and the connecting lead 38 extending from the side surface of the package are cut and removed, and the surface of the connecting lead 38 is AA.
Polish to the part.

As a result, as shown in FIG. 2B, a semiconductor device 31 is formed in which the end faces of the connection leads 38 are arranged in an array on the polished surface, that is, one side surface of the package. . For example, the dimensions of the end face of the connecting lead 38 are 0.2 to 0.3 mm in the horizontal direction and 0.03 mm in the vertical direction.

Next, FIG. 3 shows a sectional view of another embodiment of FIG. In FIG. 3A, an insulating layer 41a of an insulating oxide film such as SiO ₂ is formed on the back surface of the semiconductor chips 32 of the stacked semiconductor elements 40, and connecting leads 38 between the semiconductor chips 32 when stacked are formed. It is intended to insulate the semiconductor chip 32. This also allows
As compared with FIG. 2A, the distance between the semiconductor elements 40 can be narrowed, and the thickness can be reduced.

Further, in FIG. 3B, the insulating layer 4 is formed by applying a coating of polyimide or the like on portions other than the electrode pads 32a and the holding pads 33b on the surface of the semiconductor chip 32.
1b is formed. This prevents a short circuit between the connection lead 38 and the edge portion of the semiconductor chip 32 when stacked.

As described above, when the semiconductor chips 32 are stacked as shown in the above embodiment, it is not necessary to interpose a spacer or the like between the chips, and heat conduction can be improved, thereby increasing the number of chips. Therefore, higher density can be achieved, and high yield and low cost can be achieved.

FIG. 4 is a block diagram of the second embodiment of the present invention. 4A and 4B, a wide portion 38a is formed in an intermediate portion of the connection lead 38 in FIG. 1, and the terminal material 44 is formed on the wide portion 38a in a conductive state with the connection lead 38.
Is provided.

In this case, the connection lead 38 is Sn-plated, and the terminal material 44 is, for example, a copper alloy, iron-N.
There are i alloys, tin-lead alloys (solder) and the like, which can be fused by appropriately plating them with gold or tin.

Then, as shown in FIG. 2 or 3, the layers are stacked and molded, and the terminal material 44 is polished. Then, as shown in FIG. 4C, the end surfaces of the terminal material 44 and the connection lead 38 are on one side of the package. Be expressed.

Therefore, for example, at a pitch of 0.5 mm, 0.25 m □
Since the end face of the semiconductor device 31 is exposed, the semiconductor device 31 can be easily mounted.

When the terminal material 44 is provided, in addition to fusion bonding, as shown in FIG. 4 (D), a hole 38b is formed in the wide portion 38a.
May be formed, and the terminal material 44 may be mechanically caulked, or may be provided by ball bonding with a wire bonder as shown in FIG.

[0043]

As described above, according to the present invention, the semiconductor chip is positioned in the opening portion of the tape carrier, and the connection lead is formed by appropriately combining the electrode pad of the semiconductor chip and one side of the tape carrier to form the test pad. And are electrically connected, and a plurality of these are stacked and packaged to expose the end faces of the connection leads on one side surface of the package, thereby making it possible to improve heat conduction with higher density. The characteristic test can be easily performed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a case of stacking in FIG.

FIG. 3 is a sectional configuration diagram of another embodiment of FIG.

FIG. 4 shows a block diagram of a second embodiment of the present invention.

FIG. 5 is a diagram for explaining a conventional semiconductor device having a three-dimensional structure.

FIG. 6 is a diagram for explaining a configuration of one chip of FIG.

FIG. 7 is a diagram for explaining assembly and mounting of FIG. 5;

FIG. 8 is a diagram illustrating another conventional semiconductor device having a three-dimensional structure.

FIG. 9 is a diagram for explaining the implementation of FIG. 8;

[Explanation of symbols]

 31 semiconductor device 32 semiconductor chip 33a electrode pad 33b holding pad 34 tape carrier 35b guide hole 37 holding lead 38 connection lead 39 test pad 40 semiconductor element 41, 41a, 41b insulating layer 42 spacer 43 mold resin 44 terminal material

Claims (7)

[Claims] 1. A semiconductor chip (32) on which a predetermined number of electrode pads (33a) are formed is three-dimensionally arranged and packaged, and the electrode pads (32) are packaged on one side surface of the package (43). 33a) is a semiconductor device in which end faces of connection leads (38) are exposed, the semiconductor chip (32) is located by opening a predetermined portion, and the connection is connected to the electrode pad (33a). A semiconductor device, comprising: tape carriers (34) each having an end portion of a lead (38) integrated on one side. 2. A holding pad (33b) is formed on the semiconductor chip (32), and the tape carrier (34) is connected to the holding pad (33b) to hold the semiconductor chip (32). The semiconductor device according to claim 1, wherein the holding lead (37) is formed. 3. A test pad (3) which is tested at the end of the connection lead (38) of the tape carrier (34) and which is removed after the test.
9. The semiconductor device according to claim 1 or 2, characterized in that the semiconductor device (9) is formed. 4. The semiconductor according to claim 1, wherein the tape carrier (34) is provided with a predetermined number of guide holes (35b) for position alignment when the semiconductor chips (32) are stacked. apparatus. 5. A terminal material (44) electrically connected to the connection lead (38) is provided at an end surface portion of the connection lead (38) exposed on one side surface of the package (43). The semiconductor device according to claim 1. 6. An insulating layer (41, 41a, 41b) is formed on at least one of a front surface and a back surface of the semiconductor chip (32) on which the electrode pad (33a) is formed. Item 6. The semiconductor device according to items 1 to 5. 7. A semiconductor chip (32) on which a predetermined number of electrode pads (33a) are formed is three-dimensionally arranged and packaged, and the electrode pads (32) are provided on one side surface of the package (43). 33a) is a method for manufacturing a semiconductor device in which end faces of connection leads (38) are exposed, and an opening portion (36) of a tape carrier (34) formed by consolidating the connection leads (38) on one side. The semiconductor chip (32) is positioned on the semiconductor chip (32)
Connecting the electrode pad (33a) and the connection lead (38), and stacking a predetermined number of the semiconductor chips (32) connected to the tape carrier (34) for packaging. (43) a step of polishing one side surface to expose an end face of the connection lead (38), and a method of manufacturing a semiconductor device, comprising: