JPH0653114A - Reduction projection aligner - Google Patents

Reduction projection aligner

Info

Publication number
JPH0653114A
JPH0653114A JP4206350A JP20635092A JPH0653114A JP H0653114 A JPH0653114 A JP H0653114A JP 4206350 A JP4206350 A JP 4206350A JP 20635092 A JP20635092 A JP 20635092A JP H0653114 A JPH0653114 A JP H0653114A
Authority
JP
Japan
Prior art keywords
wafer
reticle
stage
reduction projection
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4206350A
Other languages
Japanese (ja)
Inventor
Junichi Sekine
順一 関根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP4206350A priority Critical patent/JPH0653114A/en
Publication of JPH0653114A publication Critical patent/JPH0653114A/en
Pending legal-status Critical Current

Links

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  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To make focusing possible even if a wafer, a semiconductor substrate, has an unevenness larger than a focus depth and to form an image of a pattern of a reticle accurately and to transfer the image onto the wafer. CONSTITUTION:This is a reduction projection aligner which transfers a reduced pattern of a reticle 3 onto a wafer 5. On an X-Y stage 6 on which the wafer 5 is mounted, at least three electrostriction elements 9 are located with balance. Then, voltage is applied to these electrostriction elements 9 in stages from a driving power supply 7 and the X-Y stage 6 is vibrated up and down larger than a difference in level of an uneven surface of the wafer 5 and a projecting section of the uneven surface is focused on a recessed section accurately for forming an image of the reticle 3 and then for transferring the image onto the wafer 5 accurately. This equipment is especially effective for a projection lens with a large aperture diameter.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体基板に電気回路
パターンを転写する縮小投影露光装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reduction projection exposure apparatus for transferring an electric circuit pattern onto a semiconductor substrate.

【0002】[0002]

【従来の技術】図2は従来の縮小投影露光装置の一例に
おける構成を示す図である。従来、この種の縮小投影露
光装置は、例えば、図2に示すように光源から放射され
た光を単波長化する照明系1と、電気回路パターンがあ
る倍率で拡大して形成されるレティクル3と、単波長化
した光をレティクル3を通して照射するための光学系2
と、半導体基板であるウェーハ5を置くためのXYステ
ージ6と、レティクル3の電気回路パターンをXYステ
ージ6上のウェーハ5に縮小投影する縮小レンズを有し
ている。
2. Description of the Related Art FIG. 2 is a diagram showing a configuration of an example of a conventional reduction projection exposure apparatus. Conventionally, a reduction projection exposure apparatus of this type includes, for example, an illumination system 1 for converting light emitted from a light source into a single wavelength as shown in FIG. 2, and a reticle 3 formed by enlarging an electric circuit pattern at a certain magnification. And an optical system 2 for irradiating single-wavelength light through the reticle 3.
And an XY stage 6 for placing the wafer 5 which is a semiconductor substrate, and a reduction lens for reducing and projecting the electric circuit pattern of the reticle 3 onto the wafer 5 on the XY stage 6.

【0003】この縮小投影露光装置では、照明系1から
の光を光学系2に通して、レティクル3に照射し、ある
倍率(10倍又は5倍)に拡大された電気回路パターン
を投影する。この投影された電気回路パターンは縮小レ
ンズ4を通して元の大きさに縮小され(1/10又は1
/5)、XYステージ6上に置いたウェーハ5の一領域
面に結像し、電気回路パターンを転写する。
In this reduction projection exposure apparatus, the light from the illumination system 1 is passed through the optical system 2 to irradiate the reticle 3 to project an electric circuit pattern enlarged to a certain magnification (10 times or 5 times). The projected electric circuit pattern is reduced to the original size through the reduction lens 4 (1/10 or 1).
/ 5), an image is formed on an area surface of the wafer 5 placed on the XY stage 6, and the electric circuit pattern is transferred.

【0004】そして、XYステージ6をXY方向に移動
して、ウェーハの各領域に位置決めし、各領域にパター
ン光を照射させ、ウェーハ全面にパターンが転写される
まで前述の動作を繰返して行う。
Then, the XY stage 6 is moved in the XY directions to be positioned in each region of the wafer, each region is irradiated with pattern light, and the above-described operation is repeated until the pattern is transferred onto the entire surface of the wafer.

【0005】このような縮小投影露光装置の投影光学系
によって得られる解像度Rとそのときの焦点深度DOF
は、光学系のNA(開口数)と露光波長λから便宜的に R=kaλ/NA DOF=±kbλ/NA2 で与えられる。ここでkakbはレジスト材料自身の解
像力やプロセスの制御性で決まる定数である。
The resolution R obtained by the projection optical system of such a reduction projection exposure apparatus and the depth of focus DOF at that time
Is conveniently given by R = kaλ / NA DOF = ± kbλ / NA 2 from the NA (numerical aperture) of the optical system and the exposure wavelength λ. Here, kakb is a constant determined by the resolution of the resist material itself and the controllability of the process.

【0006】[0006]

【発明が解決しようとする課題】この従来の縮小投影露
光装置では、前述に示したように解像度を上げる(Rを
小さくする)ためにレズ開口数NAを大きくすると、焦
点深度DOFは小さくなる。近年、半導体基板に形成さ
れる電気回路パターンはより微細化し、また、多くの製
造プロセスを経るため、その表面の凹凸が形成され、そ
の断面構造が複雑なものになってきた。微細化対応で解
像度を上げるため、レンズ開口数NAを大きくすると焦
点深度が小さくなり、場所により焦点が合わず正しく露
光できなくなる問題があった。
In this conventional reduction projection exposure apparatus, the depth of focus DOF becomes smaller as the lesbian numerical aperture NA is increased in order to increase the resolution (reduce R) as described above. In recent years, electric circuit patterns formed on a semiconductor substrate have become finer, and many manufacturing processes have been performed, so that surface irregularities are formed and the cross-sectional structure becomes complicated. When the lens numerical aperture NA is increased in order to increase the resolution in response to miniaturization, the depth of focus becomes smaller, and there is a problem that the focus cannot be adjusted depending on the location and correct exposure cannot be performed.

【0007】本発明の目的は、表面が凹凸があっても焦
点合うパターンを結像し、正しく露光出来る縮小投影露
光装置を提供することである。
An object of the present invention is to provide a reduction projection exposure apparatus which can form a focused pattern even if the surface has irregularities and can perform correct exposure.

【0008】[0008]

【課題を解決するための手段】本発明の縮小投影露光装
置は、光源から放射された光を単波長化する照明源と、
電気回路パターンがある倍率で形成されるレティクル
と、単波長化される前記光をレティクルに照射するため
のコンデンサレンズと、半導体基板を載置するXYステ
ージと、前記レティクルのパターンを縮小して前記ウェ
ーハに投影するレンズと、前記XYステージの分割され
た部分に挟まれ配置される電歪素子と、この電歪素子に
周期的に電圧を印加する駆動電源とを備えている。
A reduction projection exposure apparatus according to the present invention is an illumination source for converting light emitted from a light source into a single wavelength.
A reticle formed by an electric circuit pattern with a certain magnification, a condenser lens for irradiating the reticle with the light that is converted into a single wavelength, an XY stage on which a semiconductor substrate is mounted, and a pattern of the reticle are reduced to reduce the reticle. It is provided with a lens for projecting onto a wafer, an electrostrictive element sandwiched between the divided parts of the XY stage, and a drive power source for periodically applying a voltage to the electrostrictive element.

【0009】[0009]

【実施例】次に本発明について図面を参照して説明す
る。
The present invention will be described below with reference to the drawings.

【0010】図1は本発明の一実施例における縮小投影
露光装置の構成を示す図である。この縮小投影露光装置
は、図1に示すように、レティクル3のパターンが転写
されるウェーハ5を載置するXYステージ6に電歪素子
9を挟み込み、この電歪素子9に周期的に電圧を印加す
る駆動電源7を設けたことである。
FIG. 1 is a view showing the arrangement of a reduction projection exposure apparatus according to an embodiment of the present invention. In this reduction projection exposure apparatus, as shown in FIG. 1, an electrostrictive element 9 is sandwiched between an XY stage 6 on which a wafer 5 onto which a pattern of a reticle 3 is transferred is placed, and a voltage is periodically applied to the electrostrictive element 9. That is, the drive power supply 7 for applying the voltage is provided.

【0011】それ以外は従来と同じように、この縮小投
影露光装置は、照明源1より発生する照明光を集束する
コンデンサレンズ2と、集光される光を透過させるとと
もにパターンが形成されるレティクル3と、レティクル
3を透過した光像を縮小してウェーハ5に結像する投影
レンズと、ウェーハ5を載置するXYステージ6とを有
している。
Other than this, the reduction projection exposure apparatus is similar to the conventional one, and the reduction projection exposure apparatus has a condenser lens 2 for converging the illumination light generated from the illumination source 1 and a reticle for transmitting the condensed light and forming a pattern. 3, a projection lens for reducing an optical image transmitted through the reticle 3 to form an image on the wafer 5, and an XY stage 6 on which the wafer 5 is mounted.

【0012】また、XYステージ6に挟み込まれる電歪
素子9は・三ケ所に均等に配置され、XYステージ面を
光軸に対して重直になるように保たれている。勿論これ
ら電歪素子9は同じ特性をもっている。そして、その特
性である電圧による厚み方向の寸法変化範囲は、必要と
される焦点深度以上にすることである。例えば、現時点
の露光装置で言えば、少なくとも1.5μm以上あれば
十分である。このような寸法変化であれば、通常のセラ
ミック圧電材で十分得られる。一方、この電歪素子9を
駆動する駆動電源7は、段階的に電圧を発生するもので
あって、低周波パレス電圧発生器である。このことは、
XYステージ6に載置されたウェーハ5の高さを周期的
に変えることである。例えば、一露光ショット当り、X
Yステージ6を数10回程度振動させることである。こ
のような低周波パルス電圧発生器は公知技術によって容
易に得られる。
Further, the electrostrictive elements 9 sandwiched between the XY stage 6 are evenly arranged in three places, and the XY stage surface is kept so as to be straight with respect to the optical axis. Of course, these electrostrictive elements 9 have the same characteristics. Then, the range of dimensional change in the thickness direction due to the voltage, which is a characteristic thereof, is to be equal to or larger than the required depth of focus. For example, in the case of the exposure apparatus at the present time, at least 1.5 μm or more is sufficient. With such a dimensional change, an ordinary ceramic piezoelectric material can be sufficiently obtained. On the other hand, the drive power supply 7 for driving the electrostrictive element 9 is a low-frequency Palace voltage generator that generates voltage stepwise. This is
This is to periodically change the height of the wafer 5 placed on the XY stage 6. For example, X per exposure shot
That is, the Y stage 6 is vibrated about tens of times. Such a low frequency pulse voltage generator can be easily obtained by a known technique.

【0013】次に、この縮小投影露光装置の動作を、例
えば、ウェーハに0.35μmの凹凸がある例で説明す
る。まず、図示していないアライメト機構によって、光
軸合せと投影レンズ4とウェーハの凹部と凸部の平均的
な焦点距離を設定する。次に、駆動電源7に厚み方向の
寸法変化量を0.35μm、振動数100を設定する。
次に、XYステージ6を移動させウェーハ5を位置決め
する。次に、制御部8の指令信号により照明源1を動作
させるとともに駆動電源7を動作させ、ウェーハ5に露
光転写する。このことにより、振動の向きが変る時点で
ステージ6の停止時間でそれぞれの凹凸部の焦点が合う
ので、正確にパターンが結像される。また、停止時間の
ときだけレジストが感光するので、必要に応じて照射時
間を伸ばしてレジストを感光させる。
Next, the operation of this reduction projection exposure apparatus will be described, for example, in the case where the wafer has irregularities of 0.35 μm. First, an alignment mechanism (not shown) is used to set the optical axis alignment and the average focal length of the projection lens 4 and the concave and convex portions of the wafer. Next, the dimensional change amount in the thickness direction is set to 0.35 μm and the frequency 100 is set to the driving power supply 7.
Next, the XY stage 6 is moved to position the wafer 5. Next, the illumination source 1 is operated and the drive power supply 7 is operated in accordance with the command signal from the control unit 8, and the wafer 5 is exposed and transferred. As a result, when the vibration direction changes, the concave and convex portions are focused during the stop time of the stage 6, so that the pattern is accurately imaged. Also, since the resist is exposed only during the stop time, the irradiation time is extended as necessary to expose the resist.

【0014】[0014]

【発明の効果】以上説明したように本発明は、XYステ
ージに電歪素子を挟み、この電歪素子を駆動させる電源
を設け、XYステージを上下振動させることによって、
表面に凹凸があっても焦点を合せて正確に結像されたパ
ターンを転写できるという効果がある。
As described above, according to the present invention, the electrostrictive element is sandwiched between the XY stage, the power source for driving the electrostrictive element is provided, and the XY stage is vibrated vertically.
Even if there is unevenness on the surface, there is an effect that it is possible to transfer the imaged pattern accurately by focusing.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例における縮小投影露光装置の
構成を示す図である。
FIG. 1 is a diagram showing a configuration of a reduction projection exposure apparatus according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 照明源 2 コンデンサレンズ 3 レティクル 4 投影レンズ 5 ウェーハ 6 XYステージ 7 駆動電源 8 制御部 9 電歪素子 1 Illumination Source 2 Condenser Lens 3 Reticle 4 Projection Lens 5 Wafer 6 XY Stage 7 Drive Power Supply 8 Controller 9 Electrostrictive Element

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 光源から放射された光を単波長化する照
明源と、電気回路パターンがある倍率で形成されるレテ
ィクルと、単波長化される前記光をレティクルに照射す
るためのコンデンサレンズと、半導体基板を載置するX
Yステージと、前記レティクルのパターンを縮小して前
記ウェーハに投影するレンズと、前記XYステージの分
割された部分に挟まれ配置される電歪素子と、この電歪
素子に周期的に電圧を印加する駆動電源とを備えること
を特徴とする縮小投影露光装置。
1. An illumination source for converting light emitted from a light source into a single wavelength, a reticle formed by an electric circuit pattern at a certain magnification, and a condenser lens for irradiating the reticle with the single wavelength converted light. , X for mounting semiconductor substrate
A Y stage, a lens for reducing the pattern of the reticle and projecting it onto the wafer, an electrostrictive element sandwiched between the divided parts of the XY stage, and a voltage is periodically applied to the electrostrictive element. A reduction projection exposure apparatus, comprising:
JP4206350A 1992-08-03 1992-08-03 Reduction projection aligner Pending JPH0653114A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4206350A JPH0653114A (en) 1992-08-03 1992-08-03 Reduction projection aligner

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4206350A JPH0653114A (en) 1992-08-03 1992-08-03 Reduction projection aligner

Publications (1)

Publication Number Publication Date
JPH0653114A true JPH0653114A (en) 1994-02-25

Family

ID=16521859

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4206350A Pending JPH0653114A (en) 1992-08-03 1992-08-03 Reduction projection aligner

Country Status (1)

Country Link
JP (1) JPH0653114A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000045067A1 (en) * 1999-01-28 2000-08-03 Active Control Experts, Inc. Method and device for vibration control
US6791098B2 (en) 1994-01-27 2004-09-14 Cymer, Inc. Multi-input, multi-output motion control for lithography system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6791098B2 (en) 1994-01-27 2004-09-14 Cymer, Inc. Multi-input, multi-output motion control for lithography system
US6959484B1 (en) 1994-01-27 2005-11-01 Cymer, Inc. System for vibration control
WO2000045067A1 (en) * 1999-01-28 2000-08-03 Active Control Experts, Inc. Method and device for vibration control

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