JPH0652959B2 - Time division multiplex switching system - Google Patents

Description

The present invention relates to a time division multiplex switching system, and more particularly to a configuration of a time division multiplex switching system that multipurposely handles various types of traffic at various speeds.

[Prior Art] With the diversification of various terminal devices in recent years, it has been required to accommodate not only voice signals but also wideband signals such as data, facsimile, and image signals in a communication network interconnecting these various terminal devices. Has been done.

Digital exchanges, which are widely used at present, usually handle voice signals as digital signals of 64 kb / s and use this as the basic transmission rate. Therefore, for a signal having a band exceeding 64 kb / s, N transmission channels of 64 kb / s are simultaneously occupied to 64 kb / s × N (N ≧ 1) and accommodated in the exchange.

FIG. 3 is a block diagram of a conventional time division multiplex switching system. In this time division multiplex switching system, the call signals multiplexed on the incoming highway are transmitted by the time division multiplex time switch T.
Is written to the output highway according to the read address supplied from the time switch control memory CM which holds the exchange information of the time slot, and the desired exchange processing is performed. The counter CNT supplies a write address for sequentially writing the call signal on the incoming highway into the time division multiplex time switch T. At the same time, the read address is supplied to the time switch control memory CM. In the time switch control memory CM, replacement information of time slots for performing desired replacement processing is written from the processor PROC. Therefore, the content of the read address of the time switch control memory CM supplied by the counter CNT becomes the read address of the time division multiplex time switch T when reading the call signal on the outgoing highway.

In the conventional time division multiplex switching system as described above,
A case of exchanging a signal having a band N times (N ≧ 1) times the basic transmission speed (hereinafter referred to as N times call) will be described with reference to FIG.

Fig. 4 shows the basic transmission rate (64 kb /
5 shows an operation example in the case of exchanging a signal having a band of 4 times (256 kb / s) of s). In this example, the signals of the 0th, 4th, 8th, and 12th time slots on the incoming highway are exchanged with the 10th, 14, 18, 22 time slots on the outgoing highway.

Here, assuming that the contents of the 0th time slot are D ₀ , the contents of the 4th time slot are D ₄ , ..., Based on the operation principle shown in FIG. 3, the contents of the time slots D ₀ , D ₄ ,
D ₈ and D ₁₂ are respectively 0 of the time division multiplex time switch T.
It is written in the address 4, address 8, address 8, and address 12.

Therefore, in order to exchange the signals of the contents D ₀ , D ₄ , D ₈ , D ₁₂ of the time slot to the 10, 14, 18, 22 time slots on the outgoing highway, the time switch control memory C
A value of 0 is assigned to the 10th address of M, 4 is assigned to the 14th address, 8 is assigned to the 18th address, and 12 is assigned to the 22nd address from the processor PROC.

This time switch control memory CM must be updated without fail when setting / releasing a call path. Generally, when setting / releasing a call of N times the basic transmission rate, the total N addresses of the time switch control memory CM are set. I have to update.

[Problems to be solved by the invention]

In the conventional technique described above, when a signal having a wide band, that is, a signal having a large value of N is to be exchanged, the processing time of the processor is increased due to the update of the time switch control memory CM, and the processing capacity of the exchange is reduced. There is a drawback that. This is because when setting / releasing a call, it is necessary to update the contents of address N of the time switch control memory CM, and this processing must be performed by the call processing software of the processor PROC. This is because it increases almost in proportion to the value of N.

It is an object of the present invention to provide a time division multiplex switching system that eliminates such drawbacks.

[Means for solving problems]

The present invention relates to a time switch control memory for holding time slot exchange information, a time division multiplex time switch for writing a multiplexed call signal and reading a call signal according to a read address supplied from the time switch control memory, A switch control memory having a processor for providing time slot exchange information for performing exchange processing, and using N time slots on a time division multiplex highway, N times (N ≧ 1) times the basic transmission rate. In a time division multiplex switching system for exchanging signals for N-times calls having a band, at the time of setting and releasing the N-times call, the bandwidth N of the N-times call received from the processor and the outgoing side maximum on the output highway are set. The time switch control memo is calculated from the youngest time slot number and the interval between adjacent time slots on the outgoing highway. From the processor, calculating the renewal address of the packet, the bandwidth N of the N-times call received from the processor, the ingress lowest numbered time slot number on the input highway, and the interval between adjacent time slots on the ingress highway. A control device having a function of calculating the update data of the time switch control memory and updating the time switch control memory with this calculated value at the same time is provided between the processor and the time switch control memory.

[Action]

According to the present invention, various information of N times call (bandwidth N, the youngest time slot number on the incoming highway, the interval between adjacent time slots on the incoming highway, the youngest time on the outgoing highway). The update address and update data of the time switch control memory for setting / releasing the N-fold call are calculated from the slot number and the interval between adjacent time slots on the outgoing highway), and the time switch control memory is updated with this calculated value. A control device with a function for
When the processor is opened, the processor gives the various information to the control device, and the time switch control memory is updated from the control device, so that the load on the processor can be reduced and the processing capacity can be improved.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a block diagram of each block in an embodiment of a time division multiplex switching system of the present invention. In this embodiment, a control unit CONT is provided between the time switch control memory CM and the processor PROC in the conventional example shown in FIG. 3, and the time division multiplex time switch T, the time switch control memory CM and the counter are provided. The operation principle of CNT is the same as that of the conventional example shown in FIG.

Further, the operation for exchanging a signal having a band of, for example, four times the basic transmission rate is also shown in FIG. 4 except that the replacement information written in the time switch control memory CM is input from the control unit CONT. This is the same as the conventional example.

In the example of FIG. 4, between the input side time slot, the output side time slot, the address of the time switch control memory CM, and the data, the address of the time switch control memory CM corresponds to the output side time slot. Of data corresponds to the incoming time slot.

Therefore, when the incoming time slot and outgoing time slot are determined in the exchange of the N-fold call, the k-th (0 ≦ k ≦ N−1) write address WA _k and write data WD _{k of the} time switch control memory CM are determined. Can be expressed as follows.

WA _k = O ₀ + m ₁ k (0 ≦ k ≦ N−1) …… Formula WD _k = I ₀ + m ₂ k (0 ≦ k ≦ N−1) …… Formula Here, N: for the basic transmission rate Bandwidth O ₀ : Youngest time slot number on outgoing highway I ₀ : Youngest time slot number on incoming highway m ₁ : Interval between adjacent time slots on outgoing highway m ₂ : incoming It is the interval between adjacent time slots on the side highway. In the example of FIG. 4, these values are N = 4, O ₀
= 10, I ₀ = 0, m ₁ = m ₂ = 4.

Therefore, when setting / restoring N-fold call, the control device CO
The NT calculates the write address and write data of the total N sets of time switch control memories CM according to the formula, and updates the time switch control memory CM with these values. In this case, since the processor PROC gives only the above-mentioned information of N, O ₀ , I ₀ , m ₁ , and m ₂ , the load of the call processing software of the processor PROC can be reduced.

FIG. 2 shows the configuration of the control device CONT that executes the above-mentioned functions. In the figure, REG is a holding circuit, SEQC
ONT indicates a control circuit, and ADD indicates an adder circuit.

A procedure for calculating the write address WA _k and the write data WD _k of the time switch control memory CM in this control device CONT will be described using equations.
The processor PROC uses the bus to hold circuits REGn.
Set the value of the bandwidth N for the basic transmission rate to.

Next, in the same manner, the holding circuit REGo is supplied with the youngest time slot number O ₀ on the output highway.
Setting the distance m ₁ of the time slot adjacent on egress highway m _1.

On the other hand, the holding circuit REGi is set to the youngest time slot number I ₀ on the incoming highway, and the holding circuit REGm ₂ is set to the interval m ₂ between adjacent time slots on the incoming highway. The processor PROC, after setting these pieces of information, sends a start signal to the control circuit SEQCONT via the bus.

The control circuit SEQCONT that receives the start signal is the holding circuit R.
Holding circuits REGo and REG are provided to EG1 and REG2, respectively.
Initialize the contents of i (ie, O ₀ and I ₀ ).

The adder circuit ADD1 adds the contents of the holding circuit REG1 and the contents of the holding circuit REGm ₁ and the result is again REG1.
With the function to return to the input of. For addition circuit ADD2 also holding circuit REG2, REGM ₂ operates similarly in response to the holding circuit REG1, REGM ₁ respectively.

Therefore, each time the holding circuit REG1 receives the load signal from the control circuit SEQCONT, the content of the holding circuit REG1 becomes O ₀ , O _0.
+ M ₁ , O ₀ + 2m ₁ , ..., O ₀ + (N−1) m ₁
And changes. Further, the content of the holding circuit REG2 is I ₀ ,
_{I 0 + m 2, I 0} + 2m 2, ........., I 0 + (N-1)
It changes to m ₂ . Therefore, with this configuration, the above equation,
This means that the write address WA _k and the write data WD _{k of} the time switch control memory CM represented by the formula can be calculated.

The control circuit SEQCONT calculates WA _k and WD _k and sends them to the time switch control memory CM, and at the same time controls the write signal WE to the CM to control WA _k.
Write the data WD _k to the address.

With the procedure described above, the update processing of the time switch control memory CM accompanying the setting / restoring of the N-fold call is achieved.

〔The invention's effect〕

As described above, according to the present invention, the update processing of the time switch control memory associated with the setting / release of the N-fold call is performed by the control device C.
Since the processing is performed by the ONT, the load on the processor PROC can be reduced, and the processing capacity of call processing can be increased.

For example, when the processing time is roughly estimated for a wideband signal when N = 10, the conventional method requires 10 steps. On the other hand, according to the present invention, the bandwidth of N times call (N = 1
0), the lowest time slot number on the incoming highway,
Just by setting the information of the interval between adjacent time slots on the incoming highway, the smallest time slot number on the outgoing highway, and the interval between adjacent time slots on the outgoing highway in total to the controller. Well, it can be realized with 5 steps which is half of the conventional example. This effect becomes greater as the value of the bandwidth N increases.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a time division multiplex exchange system of the present invention, FIG. 2 is a diagram showing a configuration of a control unit CONT in FIG. 1, and FIG. 3 is a time division multiplex exchange in a conventional example. FIG. 4 is a diagram showing the contents of a time division multiplex time switch and a time switch control memory when a signal having a band four times the basic transmission rate is exchanged. T ...... time division multiplexing time switch CM ...... time switch control memories CNT ...... counter PROC ...... processor CONT ...... controller _{REG1, REG2, REGm 1, REGm} 2, REG
o, REGi, REGn ... Holding circuit SEQCONT ... Control circuit ADD1, ADD2 ... Addition circuit

Claims (1)

[Claims] 1. A time switch control memory for holding time slot replacement information, a time division multiplex time switch for writing a multiplexed call signal and reading the call signal according to a read address supplied from the time switch control memory. A time switch control memory having a processor for providing time slot exchange information for performing exchange processing, and using N time slots on a time division multiplex highway, N times the basic transmission rate (N ≧ 1) In a time division multiplex switching system for exchanging signals of N-times call having a bandwidth of N, the bandwidth N of the N-times call received from the processor and the outgoing side on the output highway at the time of setting and releasing the N-times call The time switch control method is calculated from the youngest time slot number and the interval between adjacent time slots on the outgoing highway. The memory update address is calculated, and the bandwidth N of the N-times call received from the processor, the ingress lowest numbered time slot number on the input highway, and the interval between adjacent time slots on the ingress highway are calculated. A control device having a function of calculating update data of the time switch control memory and updating the time switch control memory with the calculated value at the same time is provided between the processor and the time switch control memory. Division multiplex switching system.