JPH0652699A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a circuit system for an on-chip test having the large degree of juxtaposition and capable of specifying the position of a defective memory by arranging a test circuit dispersed in a lattice shape within a memory array. CONSTITUTION:A memory mat 13 is composed of M0,..., M48 and a test is performed simultaneously. The column of sense amplifiers 11 is provided between the respective memory mat 13 and a dispersively arranged test circuit 12 is arranged on the intersection of the column of sense amplifiers 11 and a word line lining part 15. As to the operation of the device, the same data are written on the corresponding position of the M0-M48 of the memory mat 13 first. Next, these data are read, whether the data are coincident in the column direction is outputted to coincidence lines Y0-Y2 and whether the data are coincident in the row direction is outputted to coincidence lines X0-X6. A specifying circuit for defective memory position 14 detects the memory simultaneously discorded with both Y- and X-coincidence detecting lines and specifies where the real error is present.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having an on-chip test circuit system having a large degree of parallelism and capable of simultaneously specifying a defective memory position.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits, especially dynamic random access memories (hereinafter referred to as DRAMs), have been
The degree of integration is increasing. At that time, how to reduce the test time due to the increase of the storage capacity is the DRAM.
Is becoming an important factor in cost reduction. Therefore, it is becoming more common to try to reduce the test time by using an on-chip test circuit or the like.

FIG. 4 is a block diagram of a semiconductor integrated circuit having a conventional 32-bit parallel test system. The outline of the operation of this system will be described. First, all the same data is written from the test circuit 43 outside the memory array to the corresponding positions of the memory mats 0, ..., 31 (41). Next, at the time of test reading, data is simultaneously read from each memory mat 41 to the test circuit 43. Test circuit 43
Then, it is checked whether all these data match. If there is a mismatch, it is determined that the chip has a defect. Here, 42 indicates a sense amplifier.

[0004]

However, in the conventional 32-bit parallel test circuit system described above, (1) the degree of parallelism is limited by the number of read wires from the memory array section to the test circuit 43 and the size of the test circuit. Therefore, the parallelism cannot be increased so much, and (2) the position of the defective memory cannot be specified in principle.

In view of the above problems, the present invention provides a semiconductor integrated circuit having an on-chip test circuit system which has a large degree of parallelism and can simultaneously specify a defective memory position.

[0006]

In order to solve the above problems, the semiconductor integrated circuit of the present invention has means for reading out test results independently in the row and column directions, and the position of the defective memory from the test results. And a means for specifying.

[0007]

According to the present invention, with the above-described structure, the parallel test can be simultaneously executed in the two directions of the row direction and the column direction by the change in the potential of the detection line, and the defective memory position can be specified from these results.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram of a semiconductor integrated circuit using the XY parallel test system according to an embodiment of the present invention.

In FIG. 1, X0, ..., X6 are row-direction coincidence detection lines, and Y0, ..., Y2 are column-direction coincidence detection lines. M0, ..., M48 (13) are test memory mats that perform simultaneous operation, that is, a set of memories of a certain size, for example, 32K bits. A sense amplifier row 11 is provided between each memory mat 13, and the distributed arrangement test circuit 1 is provided at the intersection of the sense amplifier row 11 and the word line lining area 15.
2 are arranged. Reference numeral 14 is a defective memory position specifying circuit for inputting the row direction coincidence detection line and the column direction coincidence detection line to specify the defective memory position. A column block 16 has two memory sets 13 in the column direction, for example, M0 and M0 'as one block.

The operation of the semiconductor integrated circuit of this embodiment will be briefly described. First, all simultaneous test memory arrays M0-M4
The same data is written in the corresponding positions of 8.

Next, the data in each of the simultaneous test memory arrays are read out at the same time. Whether the data match in the column direction corresponds to the Y detection line, and the data in the row direction corresponds to the X detection line. Is output to. For example, M
0, M3, ..., M40, M43, and M46 indicate whether the corresponding data in the memory are the same or not, which is output to the Y0 coincidence detection line. At the same time, for example, it is output to the X0 coincidence detection line whether the data in the corresponding memories of M0, M1 and M2 are the same. The defective memory position specifying circuit 14 can be used to specify where the true error is from the outputs of the coincidence detection lines.

The principle is as shown in the table of FIG.
This is because when there is a defect in the memory array at the intersection of X2 and Y1, that is, when there is a defect in M7, a mismatch signal is detected on the match detection line of X2 and Y1. The defective memory location specifying circuit 14 placed in such a peripheral can be easily configured by a logic circuit such as AND.

In the description of this embodiment, the number of Y detection lines is 3, the number of X detection lines is 6, and the number of simultaneous test mats, that is, the number of simultaneous test bits is 48. However, these run on the memory array. Therefore, the number can be easily increased. That is, unlike the conventional example, there is a feature that the parallel test degree can be easily increased. Further, as shown in this embodiment, there is a feature that the defective position can be easily identified.

Next, an example of the test circuits distributed in the memory array will be described with reference to FIG. This drawing is a block diagram of the distributed arrangement test circuit in the embodiment. The operation will be briefly described with reference to FIG. All MOS transistors in this figure are N-type. The X, Y coincidence detection line is also used as an X, Y data read line.

First, the write operation will be described. The write operation is performed according to the following procedure.

(W1) The write control line 31 and the column selection line 32 corresponding to the address transit to 1 level.

(W2) When write data is set to the X coincidence detection line / X read line (X, X '), the write control transistor 33 and the column switch 39 activated by the column selection line 32 are used. Then, the data is written in the sense amplifier 38. This will be further written to the memory cell.

Next, the normal reading operation will be described. The normal read operation is performed according to the following procedure.

(R1) The X coincidence detection line / X read line (X, X ') is precharged to one level.

The column selection line 32 corresponding to the (R2) address is activated, and the amplification result of the signal from the memory cell is output to the local data line 34 via the column switch 39. At this time, when the data of 1 is read,
The local data line D becomes 1 level and the local data line D ′ becomes 0 level.

(R3) Next, the column block selection line 35
Becomes 1 level, the X read transistor 36 is activated. As a result, when 1 data is read, X is discharged to 0 level. This is further amplified by peripheral circuits and read out as data.

Next, the operation during the test will be described. The test operation is performed by the following procedure.

(T1) If the expected value of the data in the memory cell is 1, that is, 1 if the memory cell is normal,
X ′ is precharged to the level 1 and X is precharged to the level 0. On the contrary, when the expected value is 0, X'is precharged to 0 level and X is precharged to 1 level.

The column selection line 32 corresponding to the (T2) address is activated, and the amplification result of the signal from the memory cell is passed through the column switch 39 to the local data line 34.
Is output to. At this time, when 1 data is read out, the local data line D becomes 1 level and D ′ becomes 0 level.

(T3) Next, the column block selection line 35
Becomes 1 level, the X read transistor 36 is activated. As a result, when the data of 1 is read out correctly, X has been precharged to the level of 0, so that the potential of X does not change. Also, X'is precharged to the level of 1, but since D'is at the 0 level, the read transistor connected to X'and D'is not conducting, so X'also Also, it does not discharge.

However, when the data of 0 is erroneously read out due to a defective cell, X'is discharged to the level of 0. The X coincidence detection lines are all common in the X direction. That is, the potentials of the coincidence detection lines X and X'are maintained only when all the read data from the memory array connected to the same X coincidence detection line are correct. Will be discharged to a level. Y
The operation of the coincidence detection line is almost the same. In this way, coincidence detection can be realized simultaneously in a plurality of X and Y directions.

[0027]

As described above, according to the present invention, the detection line having the expected value 1 in the first direction and the detection line having the expected value 0 in the first direction are provided.
A first means for changing the potential of the detection line in the first direction according to the signal value read out, a sense amplifier means for amplifying the signal of the memory cell, and a specific output among the outputs from the sense amplifier means. For transferring the signal from the transfer means to the input of the means for changing the potential of the detection line, the detection line of the expected value 1 in the second direction, and the detection line of the second direction. The potential of the detection line having the expected value 0 and the potential of the detection line in the second direction are changed according to the read signal value, and the signal from the transfer unit is set to the potential of the second detection line. And a means for connecting to the input of the means for changing, wherein the means for changing the potentials of the first and second detection lines are arranged in the intersection area of the sense amplifier row and the word line lining portion. By this, row direction and column direction In two directions can be executed in parallel simultaneously tested, these results can identify the defective memory location.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a principle for identifying a true error portion in the embodiment.

FIG. 3 is a configuration diagram of a distributed arrangement test circuit in the same embodiment.

FIG. 4 is a block diagram of a semiconductor memory device using a conventional 32-bit parallel test circuit system.

[Explanation of symbols]

 11 sense amplifier row 12 distributed arrangement test circuit 13 memory mat 14 defective memory position specifying circuit 15 word line lining section 16 column block

Claims (9)

[Claims] 1. A semiconductor memory device in which test circuits are arranged in a memory array in a grid pattern. 2. A semiconductor memory device, wherein the test circuit according to claim 1 is arranged in an intersection region of a sense amplifier row and a word line lining portion. 3. A semiconductor memory device comprising: means for reading out test results independently in a row direction and a column direction; and means for specifying a defective memory location from the test results. 4. A semiconductor memory device according to claim 3, wherein the means for obtaining a test result is distributed in a memory array. 5. A semiconductor memory device according to claim 3, wherein the means for obtaining a test result is arranged at an intersection region between the sense amplifier row and the word line backing portion. 6. The potentials of the detection line having the expected value 1 in the first direction, the detection lines having the expected value 0 in the first direction, and the potentials of the detection lines in the first direction are changed according to the read signal value. First means and sense amplifier means for amplifying the signal of the memory cell;
Of the outputs from the sense amplifier means, means for transferring a specific output, means for connecting the signal from the means for transferring to the input of means for changing the potential of the detection line,
A detection line having an expected value of 1 in the second direction, a detection line having an expected value of 0 in the second direction, and a second means for changing the potential of the detection line in the second direction according to the read signal value. And a means for connecting a signal from the transferring means to an input of a means for changing the potential of the second detection line. 7. A semiconductor integrated circuit in which the detection line according to claim 6 is also used for reading data. 8. A semiconductor memory device, wherein the means for changing the potentials of the first and second detection lines according to claim 6 is arranged at an intersection region of a sense amplifier row and a word line lining portion. 9. The semiconductor memory device according to claim 6, further comprising means for specifying the position of the defective memory by outputs from the detection line in the first direction and the detection in the second direction. A semiconductor memory device having.