JPH04276398A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To decrease the labor of test pattern preparation for device test in consideration of the mutual interference by arranging regularly the unit of the same circuit configuration to a semiconductor substrate and providing a unit selecting means. CONSTITUTION:Each unit MU including a memory cell array MCA, an X selector XSEL, a sense amplifier array SAA, a Y selector YSEL, a reading amplifier RAMP, a writing amplifier WAMP and an electrode pat group TPAD for test which are the same in the circuit way, arrange the direction to a semiconductor substrate 2 and are arranged regularly in the matrix way can consider that the interference condition at the mutual section of the bit line and at the mutual section of the peripheral circuit and bit line is the same. Then, the test pattern for the device test in consideration of the mutual interference can be made common while the interference conditions of the test pattern are the same. Then, the labor of the test pattern preparation for the device test in consideration of the mutual interference can be decreased, and the test time can be shortened.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a technique for facilitating device testing of the memory device, and is a technique that is effective when applied to, for example, DRAM (dynamic random access memory). It is related to.

0002

2. Description of the Related Art Conventionally, in a device test of a semiconductor memory device such as a DRAM, it is necessary to evaluate the function of each memory cell in order to improve the reliability of the device. In this case, a method is usually used in which a test pattern is written in each memory cell, read out, and compared with an expected value. When reading data from a memory cell, all memory cells sharing the selected word line are normally set to a selected state and the data is output to the bit line. Therefore, when focusing on a specific memory cell, depending on the logical value of the data read from the surrounding memory cells, it may be affected by capacitive coupling noise between bit lines, or the sense amplifier or main amplifier may be affected by capacitive coupling noise. Mutual interference, such as noise generated in peripheral circuits affecting a particular bit line, must be taken into account. An example of a document describing DRAM is US Pat. No. 3,969,706.

0003

[Problem to be Solved by the Invention] Conventionally, however, insufficient consideration has been given to reducing the interference between bit lines and the influence of peripheral circuit operations, so it has been difficult to reduce the number of bits that are similar to the bit in the vicinity of the bit of interest. The inventor discovered that there is a problem in that it is necessary to perform a device test by generating a test pattern for each bit of interest, which takes time and effort not only to create the test pattern but also to test the device. . This is particularly noticeable in a memory with a large storage capacity such as a DRAM.

An object of the present invention is to provide a semiconductor device that contributes to reducing the effort required to create test patterns for device testing, taking into account interference between bit lines and between peripheral circuits and bit lines due to differences in logical values of stored information. Its purpose is to provide integrated circuits. Another object of the present invention is to provide a semiconductor memory device that contributes to shortening device test time in consideration of the interference.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0006]

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows.

That is, a plurality of memory cells arranged in a matrix, selection means for selecting a memory cell, and means for amplifying data read from the selected memory cell or data to be written to the selected memory cell. A plurality of unit units having the same circuit configuration are regularly arranged in a matrix on one semiconductor substrate, and
A semiconductor memory device is constructed by providing unit selection means for selecting data input/output to a desired unit.

Furthermore, in order to operate the respective unit units in parallel in a device test and to make the results of the parallel operation available in parallel in the device test, a It is preferable to provide electrode pads on the semiconductor substrate in advance.

When considering the case where a device test is performed with the chip sealed, the test is performed with the chip sealed with the electrode pad or the lead terminal connected to it exposed to the outside, and then the electrode It is preferable to further seal the exposed portion of the pad and package it in a completely sealed state.

0010

[Operation] According to the above-mentioned means, each unit that is identical in circuit and laid out with the same peelings can be connected between bit lines and the surrounding area if the layout conditions for the surroundings are almost the same. It is now possible to assume that the interference conditions between circuits and bit lines are the same, and this means that test patterns for device tests that take such mutual interference into account can be created using common test patterns for devices with the same interference conditions. This contributes to reducing the effort required to create test patterns for device testing that takes such mutual interference into account, as well as shortening test time. Furthermore, enabling the information obtained by the parallel operation of the unit units to be outputted to the outside in parallel for each unit via the electrode pads also contributes to further shortening the device test time in consideration of the interference. .

[0011]

Embodiment FIG. 1 shows a layout configuration of a DRAM 1 which is an embodiment of a semiconductor memory device according to the present invention, and FIG.
The block diagram is shown in . DRA shown in each figure
Although not particularly limited, M is formed on one semiconductor substrate 2 such as a silicon substrate by a known MOS type semiconductor integrated circuit manufacturing technique.

In the figure, MU is a unit, and includes a memory cell array MCA in which a plurality of dynamic memory cells are arranged in a matrix, an X selector XSEL for selecting a word line coupled to a selection terminal of a memory cell,
A sense amplifier array SAA provided on each bit line to detect and amplify data read to the bit line.
, Y selector YSEL, Y selector YS for selecting the bit line to which the data input/output terminal of the memory cell is connected.
A read amplifier RAMP such as a main amplifier that amplifies the data of the memory cell selected by EL, a write amplifier WAMP that drives the bit line selected by the Y selector YSEL according to the write data, an input of the write amplifier WAMP, and an input of the read amplifier RAMP. It includes a test electrode pad group TPAD coupled to the output. Although not particularly limited, the memory cell is a so-called one-transistor type composed of a selection transistor and a storage capacitor connected in series with the selection transistor, and one transistor is connected to the non-inverted bit line and the inverted bit line of the complementary bit line which adopts a folded type. Data input/output terminals of memory cells are coupled alternately every other or every second memory cell. The X selector XSEL includes address signal decoding logic and a driving circuit that drives the word line according to the decoding result. The Y selector YSEL includes address signal decoding logic and a switch circuit that selects a bit line according to the decoding result. As shown in FIG. 1, the unit units MU each have the same circuit configuration and the same layout configuration, and are arranged in a regular pattern with uniform peeling in the areas above and below the center of the semiconductor substrate 1. are arranged in a matrix.

At the center of the semiconductor substrate 1, there are a unit selector USEL1 for selecting the unit MU located above, a unit selector USEL2 for selecting the unit MU located below, and unit selectors USEL1, USEL2. A data input/output buffer DBUFF for inputting and outputting data with the outside via
The address signal supplied from the outside is converted into an internal complementary address signal, and the X selector XSEL and Y selector YS
Address input buffer AB for supplying to EL, unit selector USEL1, and unit selector USEL2
A control block CBLK is formed that includes a UFF, a timing controller that generates various internal timing signals based on external control signals, and the like.

A group of electrode pads OP for external connection such as bonding pads or bump electrodes is provided at the peripheral edge of the semiconductor substrate 1.
AD is placed. This electrode pad group OPAD is
It is coupled to the data input/output buffer DBUFF, address input buffer ABUFF, and control block CBLK.

In the DRAM 1 of this embodiment, when an external address signal is supplied to the address buffer ABUFF in a non-address multiplex format in a data read operation, the upper plurality of complementary internal address signals corresponding to the external address signal are The bit is given to the X selector XSEL to select the memory cell array M of each unit MU.
In CA, a predetermined word line corresponding to the address signal is brought into a selected state, and the information stored in the memory cell whose selection terminal is coupled to the word line is read out to the corresponding bit line. At this time, the sense amplifiers included in the sense amplifier array SAA detect and amplify the minute potential difference between the complementary bit lines, and refresh the information stored in the memory cell. Then, at a predetermined timing when the amplification operation by the sense amplifier array SAA is finalized, the complementary bit line selection operation by the Y selector YSEL is started. The data on the selected complementary bit line is transferred to the read amplifier RA.
The amplified data is amplified by the MP, and the amplified data selected by the unit selectors USEL1 and USEL2 is supplied to the data input/output buffer DBUFF and output to the outside. In the case of a write operation, data supplied from the outside to the data input/output buffer DBUFF is transmitted to the memory cell array via unit selectors USEL1, USEL2 and Y selector YSEL, and at that time
Written into the memory cell selected by SEL.

Next, a device test method for the DRAM 1 will be explained with reference to FIG. D shown in Figure 1
For example, RAM1 has 30 units M as shown in FIG.
As an example, a case where U1 to MU30 are included. When evaluating the functionality of each memory cell during device testing,
A test pattern is written into each memory cell, read out, and compared with an expected value. For the test pattern used for this, data read from the memory cell of interest onto the bit line is caused by capacitive coupling between the bit lines with data read from the peripheral memory cells onto the bit line. Mutual interference must be taken into consideration, such as being affected by noise caused by noise generated by the sensor, or by noise generated in peripheral circuits such as a sense amplifier or readout amplifier.

At this time, since each unit MU is identical in circuit and internal circuit layout, mutual interference within the unit and mutual interference with surrounding units can be separated. You can think of
For units having the same mutual interference conditions with surrounding unit units, it is sufficient to create a test pattern by considering one unit as a representative unit. For example, in the case of Fig. 3, the unit M is surrounded entirely by unit units.
For each of U7, MU8, and MU9, the interference conditions between the units are the same, so one of them is focused on as a representative, and the interference conditions inside the unit and the interference conditions for the outside are considered. If a test pattern is created by
It is shared by U7, MU8, and MU9. Similarly, for the unit units MU2, MU3, MU4, the test pattern formed focusing on any one of them is shared by the three units, and the test pattern for the unit units MU12, MU4 is
13. Regarding MU14, a test pattern formed focusing on one of them is shared by the three units, and a test pattern formed focusing on one of the units MU1 and MU5 is also shared. The pattern is shared by the two unit units, and the unit units MU6 and MU
A test pattern formed focusing on any one of unit units MU11 and MU15 is shared by the two units, and a test pattern formed focusing on any one of unit units MU11 and MU15 is shared between the two units. It will be shared by the unit. Furthermore, the lower unit units MU16 to MU30 are peripheral circuits USEL1, USEL2, DBUFF, ABUFF.
, CBLK, and the unit units MU1 to MU15.
Since the test pattern has a symmetrical layout configuration, the test patterns obtained focusing on the unit units MU1 to MU15 can also be used for the lower unit units.

Therefore, the DRAM 1 as a whole has the above 6
By forming a test pattern by focusing on different types of unit units, it is possible to obtain a test pattern for the DRAM 1 that takes into account interference between bit lines and the influence of operations of peripheral circuits. This facilitates the creation of test patterns, reduces the number of test patterns required for memory cell function testing of the entire DRAM 1, and reduces test time.

Furthermore, since the DRAM 1 of this embodiment has a test electrode pad group TPAD for each unit, the read data obtained by the parallel operation of each unit M1 to M30 is transferred to the individual test electrodes. Pad group T
By importing the data from the PAD into the tester in parallel, it is possible to further shorten the test time.

Although the above-mentioned functional test of the memory cell can be performed in the wafer state, it is preferable to adopt a packaging method as shown in FIG. 4 in order to be able to perform the function test in the packaged state as well. That is, chip-shaped DRAM1
When molding with resin 3, an opening 4 is formed in the center of the mold.
is formed, and the test lead terminal group 5 coupled to the test electrode pad group TPAD is exposed to the outside through the opening 4 thereof. During testing, the test lead terminal group 5 and the lead terminal group 6 coupled to the electrode pad group OPAD are used. After the test results confirm that the product is good, the opening 4 is closed and sealed with a lid 7 made of resin.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof. stomach.

For example, in the above embodiment, the unit MU
The configuration includes the X selector You can decide which functional blocks to include. Further, the DRAM is not limited to the non-address multiplex format, but may be an address multiplex format that supplies X addresses and Y addresses in a time-sharing manner. Furthermore, the arrangement of the unit units is not limited to the above embodiments, and the arrangement of the unit units with respect to the chip is not limited to the upper and lower two-division layout, but can also be arranged in a four-division or six-division layout, or It is also possible to arrange them left and right or radially. Furthermore, the layout positions of data input/output buffers, address input buffers, etc. are not limited to the center of the chip, but can also be placed at the edges of the chip if noise during operation does not locally affect them.

[0023] In the above explanation, the invention made by the present inventor will be mainly explained in relation to the field of application, DRA, which is the background of the invention.
Although the present invention has been described for the case where it is applied to M, the present invention is not limited thereto, and can be applied to other storage devices having dynamic type memory cells such as pseudo-static RAM, static type RAM, and even ROM. can. Further, the semiconductor memory device of the present invention is not limited to a single memory, but can also be applied to an on-chip memory such as a microcomputer.

The present invention can be widely applied to conditions requiring at least a functional test of memory cells.

[0025]

Effects of the Invention The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, unit units having the same circuit configuration and the same circuit layout are regularly arranged in a matrix on one semiconductor substrate, and data input/output to a desired unit is selected. By providing a unit selection means to do this, if the layout conditions with respect to the surroundings are substantially the same, the interference state between bit lines or between a peripheral circuit and a bit line can be considered to be the same. This makes it possible to standardize test patterns for device tests that take such mutual interference into consideration for devices with the same interference conditions, and thereby allows devices that take such mutual interference into consideration. This can contribute to reducing the labor involved in creating test patterns for testing and shortening test time.

[0027]Furthermore, by making it possible to externally output information obtained by the parallel operation of the unit units in parallel via the electrode pads, it also contributes to shortening the device test time in consideration of the interference. can do.

By providing a group of test electrode pads for each unit, it is possible to input the read data obtained by the parallel operation of each unit into the tester from the individual test electrode pads in parallel. This can further reduce device testing time.

[Brief explanation of the drawing]

FIG. 1 is an overall layout configuration diagram of a DRAM according to an embodiment of the present invention.

FIG. 2 is a block diagram corresponding to the DRAM of FIG. 1;

FIG. 3 is a general example layout of a unit for explaining the effect of a device test on the DRAM of FIG. 1;

FIG. 4 is an explanatory diagram of an example of a DRAM package state in which a group of test electrode pads is made conductive to the outside.

[Explanation of symbols]

1 DRAM 2 Semiconductor substrate MU Unit unit MCA Memory cell array XSEL X selector YSEL Y selector RAMP Read amplifier WAMP Write amplifier TPAD Test electrode pad group USEL1, USEL2 Unit selector DBUF
F Data input/output buffer ABUFF Address input buffer 3 Resin 4 Opening 5 Test lead terminal group 6 Lead terminal group 7 Lid

Claims (3)

[Claims] 1. A plurality of memory cells arranged in a matrix, selection means for selecting a memory cell, and means for amplifying data read from the selected memory cell or data to be written to the selected memory cell. A plurality of unit units having the same circuit configuration are regularly arranged in a matrix on one semiconductor substrate with the same orientation, and a unit for selecting data input/output to a desired unit unit. A semiconductor memory device comprising selection means. 2. The semiconductor memory device according to claim 1, wherein each of the unit units has an electrode pad that can be electrically connected to a selected memory cell within the unit. 3. The semiconductor memory according to claim 2, wherein the electrode pad or the lead terminal electrically connected thereto is exposed to the outside and sealed, and then packaged in a completely sealed state. Device.