JPH0652375A - Ic card - Google Patents

Abstract

PURPOSE:To prevent power from being wastefully consumed when the output terminal of a decoder circuit not being connected to memory is brought into contact with another output terminal, a pad, or a power source, etc., in an IC card provided with plural memory and the decoder circuit to select the memory. CONSTITUTION:Three-state output buffers 3 are provided among the output terminals Y0'-Y7' of the decoder circuit 1 and among the output terminals CS1-CS8 of a decode IC 2, respectively. A decoder output control circuit 8 controls the operations of the three-state output buffers 3 based on signals inputted from input terminals D, E, and sets the output terminals CS5-CS8 not being connected to memory ICs 11-14 on the output terminals CS1-CS8 at high impedance states.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC card having a decode circuit for selecting a specific memory integrated circuit from a plurality of memory integrated circuits based on a decode signal.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing an example of a conventional IC card. It is assumed that the IC card shown in FIG. 5 can contain a maximum of eight memory ICs.

The IC card shown in FIG. 5 has a decoding circuit 1
Decoding IC 52 with built-in memory and memory ICs 11-14
And a memory group 7 composed of. Further, the memory group 7 can be composed of one to a maximum of eight memory ICs as constituent elements according to the required memory capacity. The decode circuit 1 inputs the decode signals A, B, C which are 3-bit decode signals and the control signal EN 'which is a 1-bit control signal, and outputs eight output terminals Y0' to Y7 '. Respectively output output signals. The output terminals Y0 'to Y7' of the decoding circuit 1 and the output terminals CS1 to CS8 of the decoding IC 52 are directly connected to each other one to one. Then, the output terminal CS1 of the decode IC 52
To CS4 are memory ICs 11 to 14 in the memory group 7.
Are connected to the chip select terminals CS 'of the above in a one-to-one manner.

Next, the operation of the conventional IC card configured as described above will be described. The decode signals A, B, C input by the decode circuit 1 are usually a part of the address signal in this IC card. The decode circuit 1 is based on the decode signals A, B and C which are the address signals.
Selects one of the memory ICs 11 to 14. Further, the control signal E input to the decoding circuit 1
N ′ is used when, for example, all the memory ICs in the memory group 7 are placed in a standby state.

FIG. 6 is a truth table for the decode circuit 1 showing the relationship between the decode signals A, B, C and the control signal EN 'and the states of the output terminals Y0' to Y7 '.

[0006]

However, in the above-mentioned conventional IC card, the output signal of the decoding circuit is
It is directly output to the outside of the IC that incorporates the decoding circuit. Therefore, even when the memory capacity of the IC card is small and there is an output terminal of the decoding circuit to which the memory IC is not connected, a "high" or "low" signal is always output to all the output terminals of the decoding circuit. Has been done. At this time, the decoding circuit 1 not connected to the memory IC
Output terminal or the memory I connected to this output terminal
If the pad for connecting C contacts another terminal, pad, or the like, a current path is formed and power is wastefully consumed. In particular, when the data stored in the memory is held by the battery built in the IC card, the life of the battery is shortened.

The present invention has been made in view of the above problems, and in an IC card having a plurality of memories and a decode circuit for selecting the memories, the output terminals of the decode circuits not connected to the memories are It is an object of the present invention to provide an IC card that can prevent unnecessary power consumption even if it comes into contact with other output terminals, pads, power supplies, or the like.

[0008]

An IC card according to the present invention has a plurality of memory integrated circuits and a decode circuit for selecting a specific memory integrated circuit from these memory integrated circuits based on a decode signal. The IC card is characterized by including a control circuit that puts an output terminal of the decoding circuit, which is not connected to the memory integrated circuit, into a high impedance state.

In the present application, the read-only memory (ROM) is a UVEPROM that can be erased and electrically written by ultraviolet rays, an OTPROM that can be written only once, and an electrically rewritable E ² PROM.
It also includes a writable read-only memory such as a flash E ² PROM that can be electrically erased and written electrically.

[0010]

In the IC card according to the present invention, control is performed in an IC card having a plurality of memory integrated circuits and a decode circuit for selecting a specific memory integrated circuit from these memory integrated circuits based on a decode signal. By inputting the decode signal, the circuit can bring a predetermined output terminal of the decode circuit into a high impedance state. Therefore, the control circuit
The output terminal of the decoding circuit which is not connected to the memory integrated circuit can be brought to a high impedance state. That is, in the IC card according to the present invention, the output terminals of the decode circuits to which the memory integrated circuits are not connected can be brought into a high impedance state, so that the output terminals of the decode circuits not connected to these memory integrated circuits are Even if other output terminals, pads, power supplies, etc. are contacted, it is possible to prevent a short circuit.

In this case, the output terminal to be in the high impedance state may be determined by a signal given from the outside of the integrated circuit incorporating the decoding circuit, or the high impedance state may be determined based on the address bus and the data bus. The output terminal to be set may be determined. Further, the output terminal to be in the high impedance state may be determined based on the data written in the read-only memory.

By using a PROM or the like capable of erasing and writing data as the read-only memory, a PROM or the like can be used to change the output terminal to be in a high impedance state.

[0013]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 shows an IC according to the first embodiment of the present invention.
It is a block diagram which shows a card. In addition, in FIG.
The same components as those of the conventional IC card shown in FIG. 5 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the IC card according to the first embodiment shown in FIG. 1, components different from the conventional IC card shown in FIG. 5 are added with a 3-state output buffer 3 and a decoder output control circuit 8 in the decode IC 2. It is the part that is being done. As shown in FIG. 1, the output terminal Y of the decoding circuit 1
0'-Y7 'and output terminals CS1 to C of the decode IC2
A 3-state output buffer 3 is provided between S8 and S8. Each control terminal 4 of these 3-state output buffers 3 has an output terminal EN1 to EN of a decoder output control circuit 8.
8 are connected to each. Further, the first input end of the decoder output control circuit 8 is connected to the input terminal D of the decode IC 2, and the second input end of the decoder output control circuit 8 is connected to the input terminal E of the decode IC 2. There is.

FIG. 3 is a circuit diagram showing a configuration example of the decoder output control circuit 8 in FIG. As shown in FIG.
The decoder output control circuit 8 includes a NOR circuit 31, an inverter 32, and a NAND circuit 33.

Next, the operation of the IC card according to the first embodiment constructed as described above will be described. Figure 2
The logic levels of the input terminals D and E and the decode I in FIG.
It is a table which shows the relationship with the state of the output terminals CS1-CS8 of C2. However, in FIG. 2, the case where control is possible is indicated by ◯, and the case where the impedance is forcibly set to high impedance is indicated by Hz. The decoder output control circuit 8 controls the states of the output terminals CS1 to CS8 based on the signals input from the input terminals D and E as shown in the table of FIG. The operation of the IC card according to the first embodiment will be described in more detail below.

The 3-state output buffer 3 outputs its input as it is when a "high" signal is applied to its control terminal 4 and does not depend on its input when a "low" signal is applied to its control terminal 4. Output end is high impedance (H
z) state.

When a "high" signal is applied to the input terminal D and a "low" signal is applied to the input terminal E, the logic levels of the output terminals CS1 to CS4 of the decoding IC 2 are respectively as shown in FIG. Output terminals Y0 'to Y3' have the same logic level, and the output terminals CS5 to CS8 are forcibly fixed to the high impedance state.

As a result, the IC card according to the present embodiment applies the "high" signal to the input terminal D and the "low" signal to the input terminal E, so that the memory IC is not connected and is in the open state. Output terminal CS5
CS8 can be fixed in a high impedance state. Therefore, the IC card according to the present embodiment is a memory IC
Even if the output terminal of the decoding IC that is not connected to the output terminal comes into contact with another output terminal, a pad, a power supply, or the like, it is possible to prevent waste of power consumption.

FIG. 4 shows an IC according to the second embodiment of the present invention.
It is a block diagram which shows a card. In addition, in FIG.
The same components as those of the IC card shown in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the IC card according to the second embodiment shown in FIG. 4, components different from those of the IC card according to the first embodiment shown in FIG. 1 are writable and read-only instead of the input terminals D and E. The memory 43, an address bus 44 and a data bus 45 are provided. An address bus 44 and a data bus 45 are connected to the writable read-only memory 43. Further, the output end of the writable read-only memory 43 is connected to the input end of the decoder output control circuit 8.

Next, the operation of the IC card according to this embodiment constructed as described above will be described. The writable read-only memory 43 corresponds to the data input from the address bus 44 and the data bus 45 and corresponds to the decode IC.
Information for setting a predetermined output terminal of the 42 output terminals CS1 to CS8 to a high impedance state is stored in advance. Then, the decoder output control circuit 8 outputs a signal for controlling the 3-state output buffer 3 based on the output signal of the writable read-only memory 43, and a desired output terminal among the output terminals CS1 to CS8 of the decoding IC 42. To high impedance state.

The writable read-only memory 43
Writing information to the memory can be easily realized by connecting part of the address bus 44 and the data bus 45 to the writable read-only memory 43.

As a result, the IC card according to the present embodiment has the same function as the IC card according to the first embodiment, and the number of terminals can be reduced by the amount that the input terminals D and E are unnecessary. it can.

[0026]

As described above, according to the IC card of the present invention, a plurality of memory integrated circuits and a decode circuit for selecting a specific memory integrated circuit from these memory integrated circuits based on the decode signal. In the IC card having the above, since the output terminals of the decoding circuit which is not connected to the memory integrated circuit and is in the open state can be set to the high impedance state, these output terminals can be connected to other output terminals, pads or Even if it comes into contact with a power source or the like, it is possible to prevent a short-circuit state and prevent unnecessary power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram showing an IC card according to a first embodiment of the present invention.

2 is a table showing a relationship between logic levels of input terminals D and E in FIG. 1 and states of output terminals CS1 to CS8 of a decode IC 2;

3 is a circuit diagram showing a configuration example of a decoder output control circuit 8 in FIG.

FIG. 4 is a block diagram showing an IC card according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing an example of a conventional IC card.

6 is a truth table of the decoding circuit 1 in FIG.

[Explanation of symbols]

 1; Decode circuit 2; Decode IC 3; 3-state output buffer 7; Memory group 8; Decoder output control circuit

Claims (3)

[Claims] 1. An IC card having a plurality of memory integrated circuits and a decode circuit for selecting a specific memory integrated circuit from these memory integrated circuits based on a decode signal, wherein the output terminal of the decode circuit includes: An IC card having a control circuit that puts an output terminal, which is not connected to the memory integrated circuit, in a high impedance state. 2. A decode integrated circuit, which is one integrated circuit having the decode circuit and the control circuit, wherein the decode integrated circuit is based on a signal externally applied to the control circuit. The IC card according to claim 1, wherein an output terminal not connected to the integrated circuit is brought into a high impedance state. 3. The IC card according to claim 1, further comprising a read-only memory that stores data that controls the control circuit.