JPH0652254A - Device for generating transistor model parameter - Google Patents

Abstract

PURPOSE:To improve the accuracy of a circuit design by exactly generating a transistor model parameter of transistors of various shapes used for a circuit simulator. CONSTITUTION:The shape information of a transistor to be derived is inputted in a transistor shaped input part 2. A model parameter of a reference transistor is stored in a reference transistor model parameter storage part 3, and a joining area, depth of doping, sheet resistance, channel width, channel length, etc., are stored in a process and mask design data storage part 4, as process and mask design data of the reference transistor. When information of a transistor of a new shape is inputted, the difference to the new transistor is detected from the joining area, etc., of the reference transistor, and from this difference information, a new transistor model parameter is calculated by a new transistor model parameter calculating part 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is mainly used for analog circuit design and is used for simulating transistor parameters, and relates to a transistor model parameter generating device.

[0002]

2. Description of the Related Art The shape of a transistor used in a general integrated circuit (IC) is not a single shape as shown in FIG. The length and width of the emitter, the number of stripes, etc.) and the shape of the base (the length of the base, the number of stripes, etc.) differ. Therefore, it can be said that there are basically infinite types of transistor shapes to be integrated into an IC.

By the way, when designing an analog circuit,
SPICE is used as a simulation tool. When SPICE defines and inputs a transistor model parameter that expresses the characteristics of a transistor, it is possible to simulate the circuit design using this transistor model parameter and obtain data such as the characteristics of the circuit.

Here, the above-mentioned transistor model parameters must be prepared in advance according to the shapes of various transistors used in the circuit. However, since the transistor shapes exist infinitely as described above, all of them are required. Can't prepare.

This is because in order to prepare the transistor model parameters, a large number of transistors must be actually measured and their typical values must be used as the transistor model parameters. The reason why the transistor model parameter is created in this way is that the transistor model parameter has a great influence on the accuracy of the simulation result. Especially in a high frequency IC, the transistor model parameter is accurately obtained in order to fully utilize the performance of the transistor. It is necessary. Attempting to prepare a large number of transistor model parameters results in a large amount of time and labor for prototyping, measuring, and verifying a dedicated IC.

Therefore, it is not possible to prepare all the transistor model parameters for each transistor in accordance with the shapes of all the transistors that can be used under such conditions, and at most several types are prepared. Therefore, in the above SPICE, the circuit performance is not ensured in some cases because the circuit is simulated and designed using these prepared limited transistor model parameters.

In order to avoid such a problem, when designing a circuit in which a transistor having a shape different from the transistor shape of the transistor model parameter prepared in advance is used, the area is calculated by the internal calculation of SPICE. From the transistor model parameter of the transistor shape prepared by using the factor, the transistor model parameter of another transistor shape is calculated, and the simulation is performed (the model parameter of the internal calculation using this area factor is Called pseudo transistor model parameters). This internally calculated pseudo transistor model parameter is created using only the emitter area ratio of the transistor, and the transistor shape and changing factors that change the parts other than the emitter by changing the emitter area are taken into consideration. Absent.

FIG. 4B is an explanatory diagram showing the difference in shape between the transistor T1 represented by the pseudo transistor model parameter and the actual transistors T2 and T3. That is, it is assumed that the basic transistor model parameter of the transistor T0 is prepared. Here, assuming that a transistor having a double area is used in the circuit, the transistor model parameter of the transistor having a double area is not prepared in SPICE. Therefore, the transistor model parameter of the transistor T0 is used to create the parameter of the transistor having a double area. The transistor hypothesized by SPICE is simply the connection of two transistors T0 like the transistor T4. I am imagining such a model, and I am creating pseudo transistor model parameters from this. Then, the circuit design is simulated using the transistor model parameters.

However, the transistor having an area twice as large as that actually formed in the IC is usually devised to reduce the IC chip area, and usually has a shape like the transistors T2 and T3. With such a shape,
It is clear that the values of the parasitic resistance and the parasitic capacitance are different from the parameters of the shape of the transistor T4. Therefore, the pseudo transistor model parameter virtualized by SPICE does not match the actual transistor. If there is an error in the value of the parasitic resistance or the parasitic capacitance, a great adverse effect will appear especially in a high frequency circuit.

[0010]

As described above, according to the conventional circuit design method, there are few kinds of prepared transistor shapes (transistor model parameters), the circuit design is restricted, and the pseudo transistor model parameters are set. It was inaccurate when created.

Therefore, the present invention provides a transistor model parameter generation device which can accurately create transistor model parameters of transistors of various shapes used in a circuit simulator and is useful for improving the accuracy of circuit design. The purpose is to do.

[0012]

According to the present invention, a reference transistor serving as a reference is set, a model parameter of the reference transistor is measured, and further, process data of the reference transistor and mask design data are collected as a reference. Based on the reference transistor information holding means held as a transistor model parameter, the transistor shape input means for inputting new transistor information regarding the shape of a new transistor to be obtained, and the new transistor information and the reference transistor information, at least an emitter between both transistors. And a means for calculating the model parameter of the transistor shape by a process including a calculation using the base junction area ratio, the resistance width of the new transistor, and the resistance length.

[0013]

By the above means, it is possible to obtain the model parameter of the transistor of any shape actually used,
Accurate simulation of circuit design.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. 1 is
SPICE's input file importer, SPICE
The input of the input file is performed, and the transistor shape input unit 2 inputs the transistor shape used in the circuit. Here, a measured reference transistor model parameter storage unit 3 and a reference transistor model parameter process and mask design data storage unit 4 are prepared.

The reference transistor model parameter is, for example, each parameter of a plurality of reference transistors prepared in SPICE (this parameter may be further added). Further, the process of the reference transistor model parameter model and the mask design data are
Factors of the reference transistor design (eg emitter width,
Emitter length, number of emitters, number of bases, depth, junction area,
It is data showing the doping depth, sheet resistance, channel width, channel length, etc.).

Therefore, when the target transistor shape is input, using the reference transistor model parameters, the process of the transistor model, and the mask design data, the input transistor shape is how the reference transistor is changed. You can judge whether there is. That is, it is possible to determine how the input transistor shape is obtained by modifying the emitter width, the emitter length, the number of emitters, the number of bases, etc. of the reference transistor. These data are expressed as a ratio with the element of the reference transistor.

When the target transistor shape is input, for example, as shown in FIG. 2, a model name is set and the transistor type, emitter width, number of emitters, number of bases, etc. are input as data. . The example of FIG. 2 shows an example in which the transistor type (NPN), emitter width, emitter depth, number of emitters, and single-base transistor shape are designated.

Therefore, when the target transistor shape is input, the new transistor model parameter calculation unit 5
Then, the difference between the new transistor and the reference transistor is grasped, and various model parameters of the new transistor are calculated by the new transistor model parameter calculation unit 5. Transistor model parameters to be obtained include IS (saturation current), IKF (forward knee current), ISE (non-ideal base-emitter current), VAR.
(Reverse direction Early voltage), IKR (reverse direction knee current),
RB (base series resistance at zero bias), IRB (base current at which base resistance becomes 1/2 (RB + RBM)), RBM (base bulk resistance), RE (emitter resistance), RC (collector resistance), CJE ( Base-emitter capacitance at zero bias: parasitic capacitance), TF (forward transit time),
There are ITF (current-dependent parameter of TF), CJC (base-collector junction capacitance at zero bias), CJS (collector substrate capacitance at zero bias), and the like.

After the model parameter of the new transistor is obtained by the calculation unit 5, the circuit processing is performed by the analysis processing unit 7 via the normal SPICE processing data input unit 6. Next, an example of the number of elements calculated by the new transistor model parameter calculation unit 5 will be described. First, the parasitic capacitance (CJE) of the transistor is calculated as follows. Generally, the capacitance of the pn coupling is expressed by the following equation.

Cj = A [(qεN _A N _D ) / {2 (N _A + N _D )}] ^1/2 1 / (ψ0 -V _D) ^1/2 Here, A is the junction area of the junction, N _A and N _D are the doping densities, V _D is the junction bias voltage, ψ 0 is the built-in potential, q is the electron charge, and ε is the allowable value of silicon.

As can be seen from the above equation, it is clear that CJE is proportional to the junction area A of the emitter and the base. Therefore, the CJE of the new transistor can be obtained by obtaining the area ratio of the junction area data of the reference transistor and the junction area of the new transistor and multiplying it by the CJE of the reference transistor. Here, when determining the junction area, more accurate parameters can be obtained by setting not only the planar area but also the data in the depth direction of the emitter from the transistor shape model name and incorporating it in the calculation element.

CJC and CJS can be obtained by the same method. At this time, since CJC and CJS have junctions having different doping densities, these junctions are calculated separately.

Next, the method of calculating the parasitic resistance will be described using the example of RC. RC is a collector resistance, which is the total resistance from the collector contact of the transistor to the base-collector junction. An example of the npn transistor is shown in FIG. As you can see from this transistor, RC consists of three resistance parts, deep n + part, nepi part and buri.
This is the ed layer section. These resistances can be calculated from the sheet resistance and the width and length of the portion. RC here
Is calculated by dividing it into RC1 to RC4 shown in the figure. RC = RC1 + RC2 + ((((RC4 + RC3) // RC4) + RC3) // RC4) RC1 = rc1 * (RN + depth / RN + width) RC2 = rc2 * (rcb length / rburied width) RC3 = rc2 * (rbb length / rburied width) RC4 = rc3 * (rb b depth / rburied width)

Where rc1 is the sheet resistance of deep n +, rc
2 is the sheet resistance of the buried layer, rc3 is the sheet resistance of n-epi, RN + depth is the depth of deep n +, the length from the surface of n-epi to the surface of the buried layer, and RN + width is deep n +.
Width, rcb length is the length from collector to base,
rburied width is the width of the buried layer, rrb length is the length from base to base, and rrb depth is the depth of n-epi from the bottom of the base to the top of the buried layer.

The collector resistance RC can be obtained as described above. The same method can be used to obtain shapes other than those shown here. Similarly, RB, RBM and RE can be obtained from the sheet resistance, width and length. Next, an example of the saturation current IS will be described. Is can be expressed as the following equation. Is = qAD _n (n _i ) ² / Q _B where A is the emitter-base junction area, Q _B is the number of impure atoms per unit base area, n _i is the intrinsic carrier concentration, and D is
_n is the diffusion constant of electrons in the base region.

As can be seen from this equation, IS is CJE
It is clear that it is proportional to the emitter-base junction area A as well as. Therefore, IS can be obtained by calculating the emitter-base junction area ratio of the desired new transistor and the reference transistor. This method uses IKF, I
SE, VAR, IKR, ITF, and IRB are also proportional to the emitter-base junction area, and can be obtained from the junction area ratio with the reference transistor.

As mentioned above, this embodiment is based on SPIC.
It is used as a pre-processing system for E and can calculate transistor model parameters of any shape. In the past, transistor model parameters for all transistor shapes were not prepared at the time of design, so circuit design was constrained and circuit performance could not be brought out sufficiently.However, by using the above system, circuit performance It is possible to perform a simulation that can sufficiently bring out Further, conventionally, it took a lot of time to measure a transistor model parameter, but with the above system, a transistor model parameter having a desired shape can be obtained in a short time.

[0029]

As described above, according to the present invention, a transistor model parameter of a transistor having various shapes used in a circuit simulator can be accurately created, and a device useful for improving the accuracy of circuit design is obtained. be able to.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a transistor shape input method.

FIG. 3 is a transistor explanatory diagram for explaining an example of calculating parameters of a new transistor.

4A to 4C are explanatory views of various transistor shapes.

[Explanation of symbols]

1 ... Input file importing unit, 2 ... Transistor shape input unit, 3 ... Reference transistor model parameter storage unit, 4
... Process and mask design data storage unit, 5 ... New transistor model parameter calculation unit, 6 ... SPICE processing data input unit, 7 ... Analysis processing unit.

Claims (1)

[Claims] 1. Setting a reference transistor as a reference,
A reference transistor information holding unit that measures the model parameter of the reference transistor and further holds the process data of the reference transistor and the mask design data as a reference transistor model parameter, and a new transistor regarding the shape of the new transistor to be obtained. A transistor shape input means for inputting information, and a process including a calculation using at least the emitter-base junction area ratio between the both transistors, the new transistor resistance width, and the resistance length from the new transistor information and the reference transistor information. And a means for calculating a model parameter of the transistor shape, the transistor model parameter generating apparatus.