JPH0651272A - Method for driving liquid crystal display - Google Patents

Method for driving liquid crystal display

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Publication number
JPH0651272A
JPH0651272A JP24181291A JP24181291A JPH0651272A JP H0651272 A JPH0651272 A JP H0651272A JP 24181291 A JP24181291 A JP 24181291A JP 24181291 A JP24181291 A JP 24181291A JP H0651272 A JPH0651272 A JP H0651272A
Authority
JP
Japan
Prior art keywords
voltage
scanning
period
liquid crystal
positive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24181291A
Other languages
Japanese (ja)
Inventor
Yasuhiro Shigeno
安広 滋野
Masayuki Ikehara
雅幸 池原
Shuichi Seyama
秀一 瀬山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hosiden Corp
Original Assignee
Hosiden Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hosiden Corp filed Critical Hosiden Corp
Priority to JP24181291A priority Critical patent/JPH0651272A/en
Publication of JPH0651272A publication Critical patent/JPH0651272A/en
Pending legal-status Critical Current

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  • Liquid Crystal Display Device Control (AREA)

Abstract

PURPOSE:To restrain brightness from being lowered and the flicker phenomenon from arising by superimposing a positive or negative pulse of width shorther than one scanning period on the driving voltage of the signal, or scanning, electrode of an XY matrix liquid crystal display. CONSTITUTION:At least one positive or negative pulse whose duration is shorter than one scanning period T/m (T is frame length and (m) is the number of scanning electrodes) is superimposed on a signal voltage VXi ((i)=1 to (n)) or a scanning voltage VYj ((j)=1 to (m)) for every scanning period. To superimpose the pulse on the scanning voltage VYj, however, the superimposing is carried out only during a non-selective period in a frame period, and the selective period can be omitted. This is the case where a positive or negative pulse whose width is T/4m and whose amplitude is slightly smaller than V(V= V0-V1=V1--V2=V3-V4=V4-V5) is superimposed on the voltage especially during the non-selective period of the scanning voltage VYj.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、XY単純マトリック
ス液晶表示装置の駆動方法に関し、特にその輝度の低下
とフリッカー現象を軽減させたものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method for an XY simple matrix liquid crystal display device, and more particularly to a method for reducing the decrease in brightness and flicker phenomenon.

【0002】[0002]

【従来の技術】液晶表示装置の駆動方法としてよく知ら
れている電圧平均化法を図7〜図9を参照して簡単に説
明する。液晶パネル1は液晶層及びそれを挾持する一対
の基板2,3よりなり、その基板2の内面に横方向に走
査電極(コモン電極)Y1 〜Y 6 が形成され、基板3の
内面に信号電極(セグメント電極)X1 〜X6 が形成さ
れる。走査電極Y1 〜Y6 と信号電極X1 〜X6 との交
差部分が表示ドット(画素)となる。
2. Description of the Related Art Well known as a method for driving a liquid crystal display device.
The voltage averaging method used is briefly explained with reference to FIGS. 7 to 9.
Reveal The liquid crystal panel 1 includes a liquid crystal layer and a pair of holding the liquid crystal layer.
It consists of two substrates 2 and 3, and runs laterally on the inner surface of the substrate 2.
Inspection electrode (common electrode) Y1~ Y 6Is formed on the substrate 3
Signal electrode (segment electrode) X on the inner surface1~ X6Formed
Be done. Scan electrode Y1~ Y6And signal electrode X1~ X6Exchange with
The difference portion becomes a display dot (pixel).

【0003】走査電極Y1 〜Y6 には選択電圧及び非選
択電圧が順次印加される。全ての走査電極を走査するに
要する時間を1フレームという。また各走査電極Yj
走査(選択)されている期間に、そのj行の画素に表示
すべき高レベルまたは低レベルの信号電圧(点灯電圧ま
たは非点灯電圧)が全ての信号電極X1 〜X6 に同時に
印加される。
A selection voltage and a non-selection voltage are sequentially applied to the scan electrodes Y 1 to Y 6 . The time required to scan all the scanning electrodes is called one frame. Further, during the period in which each scan electrode Y j is scanned (selected), the high-level or low-level signal voltage (lighting voltage or non-lighting voltage) to be displayed in the pixels in the j-th row is applied to all the signal electrodes X 1 to X 1 . Simultaneously applied to X 6 .

【0004】図7において第2列の画素のうち、
2,1 ,D2,3 ,D2,5 を非点灯、D2,2,D2,4 ,D
2,6 を点灯させる場合、点灯画素D2,4 の印加電圧V
2,4 を信号電圧VX2,走査電圧VY4とともに図8に、ま
た非点灯画素D2,3 の印加電圧V2,3を信号電圧VX2
走査電圧VY3とともに図9にそれぞれ示す。フレーム期
間F1 では、走査電極Yj の選択電圧=V0 ,非選択電
圧=V4 であり、 信号電極Xi に印加する点灯電圧=
5 ,非点灯電圧=V3 である。またフレーム期間F2
では、走査電極Yj の選択電圧=V5 ,非選択電圧=V
1 であり、また信号電極Xi に印加する点灯電圧=
0 ,非点灯電圧=V2 である。なお、 V0 −V1 =V1 −V2 =V;V3 −V4 =V4 −V5 =V=aVLCD (1) V0 −V5 =VLCD (2) である。フレーム期間F1 とF2 では画素Di,j に印加
される電圧 Vi,j =VXi−VYj (3) の極性が反転され、所謂交流駆動が行われる。図8,図
9の例から分かるように、画素が点灯状態になるか非点
灯状態になるかは、その画素の存在する走査電極に選択
電圧が印加されているときに、信号電極に点灯電圧が印
加されているか、非点灯電圧が印加されているかによっ
て決まる。
Of the pixels in the second column in FIG. 7,
D 2,1 , D 2,3 , D 2,5 are not lit, D 2,2 , D 2,4 , D
When lighting 2,6 , the applied voltage V of the lighting pixel D 2,4
2,4 the signal voltage V X2, scanning voltage V Y4 with 8, also applied voltage V 2,3 of the signal voltage V X2 unlit pixel D 2,3,
It is shown in FIG. 9 together with the scanning voltage V Y3 . In the frame period F 1 , the selection voltage of the scanning electrode Y j is V 0 , the non-selection voltage is V 4 , and the lighting voltage applied to the signal electrode X i is
V 5 and non-lighting voltage = V 3 . Also, the frame period F 2
Then, the selection voltage of the scan electrode Y j = V 5 , the non-selection voltage = V
1 and the lighting voltage applied to the signal electrode X i =
V 0 , non-lighting voltage = V 2 . Incidentally, V 0 -V 1 = V 1 -V 2 = V; is V 3 -V 4 = V 4 -V 5 = V = aV LCD (1) V 0 -V 5 = V LCD (2). In the frame periods F 1 and F 2 , the polarity of the voltage V i, j = V Xi −V Yj (3) applied to the pixel D i, j is inverted and so-called AC driving is performed. As can be seen from the examples of FIGS. 8 and 9, whether a pixel is in a lighting state or a non-lighting state depends on the lighting voltage applied to the signal electrode when the selection voltage is applied to the scan electrode in which the pixel exists. Is applied or a non-lighting voltage is applied.

【0005】信号電極及び走査電極にそれぞれ印加する
電圧VXi及びVYjの波形を形成する基になる電圧V0
5 は、図10に示す液晶表示装置内の液晶駆動電圧発
生回路4で発生される。これらの電圧のうちV0
2 ,V3 ,V5 の各電圧がセグメントドライバ5に供
給され、そこで信号電極Xi (i=1〜n)を駆動する
電圧VXiが作られる。また、同電圧発生回路4より電圧
0 ,V1 ,V4 ,V5 がコモンドライバ6に供給さ
れ、そこで走査電極Yj (j=1〜m)に印加する電圧
Yjが作られる。
The voltage V 0 to be the basis for forming the waveforms of the voltages V Xi and V Yj applied to the signal electrode and the scan electrode, respectively.
V 5 is generated by the liquid crystal drive voltage generating circuit 4 in the liquid crystal display device shown in FIG. Of these voltages, V 0 ,
The voltages V 2 , V 3 , and V 5 are supplied to the segment driver 5, and the voltage V Xi for driving the signal electrodes X i (i = 1 to n) is generated therein. Further, the voltages V 0 , V 1 , V 4 , and V 5 are supplied from the voltage generation circuit 4 to the common driver 6, and the voltage V Yj to be applied to the scan electrodes Y j (j = 1 to m) is generated therein.

【0006】図11に示すのは、i列の画素を全て点灯
させるときの信号電圧VXi,走査電圧VYj及び画素D
i,j に印加される電圧Vi,j =VYj−VXiを示してい
る。また図12には、i列の1行からm行までの画素D
i,1 〜Di,m を交互に点灯、非点灯、させるときの信号
電圧VXi,走査電圧VYj及び画素Di,j の印加電圧V
i,j=VYj−VXiを示している。なお、図11及び図1
2ではVi,j の極性を図8,図9及び(3) 式と逆にとっ
ている。
FIG. 11 shows a signal voltage V Xi , a scanning voltage V Yj and a pixel D when all the pixels in the i-th column are turned on.
The voltage V i, j = V Yj −V Xi applied to i, j is shown. Further, in FIG. 12, the pixels D from the 1st row to the mth row of the i-th column
Signal voltage V Xi , scanning voltage V Yj and applied voltage V of pixel D i, j when i, 1 to D i, m are alternately turned on and off
i, j = V Yj −V Xi . Note that FIG. 11 and FIG.
In FIG. 2, the polarity of V i, j is reversed from that of FIGS. 8, 9 and (3).

【0007】[0007]

【発明が解決しようとする課題】液晶パネルを駆動する
場合のフレーム周波数f=1/T(Tはフレーム期間)
は通常16〜100Hz程度であるが、走査電極の数mが
多い場合には、1本の走査電極を走査(選択)している
時間が短くなる。また、従来の一般型の液晶パネルは応
答速度が400〜500mSと遅いので、図13Bに示す
ように1回の走査だけでは光透過率Tが僅かしか立ち上
がらず、走査を何回も繰り返して立ち上がる。選択パル
スによって光透過率が最大値Tmax まで立ち上がった後
は、透過率Tはある程度減少するが、次の走査によって
再び最大値Tmax まで立ち上がる。このようにして点灯
時の輝度が保持される。
A frame frequency f = 1 / T (T is a frame period) when driving a liquid crystal panel.
Is usually about 16 to 100 Hz, but when the number m of scanning electrodes is large, the time for scanning (selecting) one scanning electrode becomes short. In addition, since the response speed of the conventional general type liquid crystal panel is as slow as 400 to 500 mS, the light transmittance T rises only slightly by one scan as shown in FIG. 13B, and the scan is repeated many times to rise. . After the light transmittance rises to the maximum value Tmax by the selection pulse, the transmittance T decreases to some extent, but rises again to the maximum value Tmax by the next scanning. In this way, the brightness at the time of lighting is maintained.

【0008】一方、応答速度が200mS以下の高速応答
型の液晶パネルでは、図13Cに示すように、一般型よ
り少ない走査回数で透過率Tは最大値Tmax に達する
が、次の走査までの間に大幅に減少してしまい、これに
より輝度が著しく低下し、フリッカー現象が発生する。
この発明は、時分割駆動される液晶パネルが走査電極数
の増加によって、1本の走査電極を走査する期間が短く
なると共に高速応答化されるために、輝度の低下及びフ
リッカー現象が発生するのを緩和させることを目的とし
ている。
On the other hand, in a high-speed response type liquid crystal panel having a response speed of 200 mS or less, as shown in FIG. 13C, the transmittance T reaches the maximum value Tmax with a smaller number of scans than the general type, but until the next scan. The brightness is significantly reduced, and thus the brightness is significantly reduced, and a flicker phenomenon occurs.
According to the present invention, a liquid crystal panel driven in a time-division manner has a shorter period for scanning one scan electrode due to an increase in the number of scan electrodes, and has a high-speed response. Therefore, a decrease in brightness and a flicker phenomenon occur. The purpose is to alleviate.

【0009】[0009]

【課題を解決するための手段】[Means for Solving the Problems]

(1) この発明では、XYマトリックス液晶表示装置の信
号電極または走査電極の駆動電圧に、1走査期間より短
い幅の正または負のパルスが1フレーム期間当たり少な
くとも1個重畳される。 (2) 上記(1)項において、各走査電極の駆動電圧に対
して、その走査電極の非選択期間においてパルスを重畳
させるのが好ましい。
(1) According to the present invention, at least one positive or negative pulse having a width shorter than one scanning period is superimposed on the drive voltage of the signal electrode or the scanning electrode of the XY matrix liquid crystal display device. (2) In the above item (1), it is preferable to superimpose a pulse on the drive voltage of each scan electrode during the non-selection period of that scan electrode.

【0010】[0010]

【実施例】この発明では信号電圧VXi(i=1〜n)ま
たは走査電圧VYj(j=1〜m)に、継続時間が1走査
期間T/m(Tはフレーム長、mは走査電極数)より短
い、正または負のパルスが1フレーム期間当たり少なく
とも1個重畳される。しかし、走査電圧VYjに重畳させ
る場合には、フレーム期間内の非選択期間のみに重畳す
ればよく、選択期間では省略してよい。
BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, the signal voltage V Xi (i = 1 to n) or the scanning voltage V Yj (j = 1 to m) is applied to one scanning period T / m (T is a frame length, m is a scanning period). At least one positive or negative pulse shorter than the number of electrodes is superimposed per frame period. However, when superposed on the scanning voltage V Yj , it may be superposed only on the non-selected period within the frame period and may be omitted during the selected period.

【0011】図2の実施例は、特に走査電圧VYjの非選
択期間に、パルス幅がT/4mで、振幅がV(V=V0
−V1 =V1 −V2 =V3 −V4 =V4 −V5 )よりや
ゝ小さな正及び負のパルスを重畳させた場合である。図
3にその波形を拡大して示す。図3で、非選択期間の走
査電圧VYjがハイレベルであるフレームF0 では、1走
査期間T/mをt0 〜t3 に4分割したとき、t1 ,t
2 の期間に振幅v1 ,v2 の正または負のパルスをそれ
ぞれ重畳させる。また、図3の非選択期間の走査電圧V
Yjが低レベルであるフレームF1 では、t1 ,t2 の期
間に振幅v1 ,v2 の負、正のパルスをそれぞれ重畳さ
せる。
In the embodiment of FIG. 2, the pulse width is T / 4 m and the amplitude is V (V = V 0) especially during the non-selection period of the scanning voltage V Yj.
-V 1 = V 1 -V 2 = V 3 -V 4 = V 4 -V 5 ). The waveform is enlarged and shown in FIG. In FIG. 3, in the frame F 0 in which the scanning voltage V Yj in the non-selection period is high level, when one scanning period T / m is divided into 4 from t 0 to t 3 , t 1 , t
Second period on the amplitude v 1, v 2 positive or negative pulse is superimposed, respectively. In addition, the scan voltage V in the non-selected period of FIG.
In the frame F 1 in which Yj is at a low level, negative and positive pulses with amplitudes v 1 and v 2 are superimposed during the periods t 1 and t 2 , respectively.

【0012】このような液晶駆動電圧発生回路4の一例
を図4に示す。電源電圧V+ IN,V- IN間の電圧を分圧抵
抗R1 〜R11により12の電圧レベルに分圧する。この
とき R1 +R2 =R3 +R4 =R8 +R9 =R10+R11 (4) とする。従って、 V0 −V1b=V1b−V2 =V3 −V4b=V4b−V5 (5) である。抵抗器R1 の一端p1 ,抵抗器R4 とR5 との
接続点p4 ,R7 とR8との接続点p7 ,抵抗器R11
一端p11は演算増幅器(オペアンプ)op1 ,op5,
6 ,op10の入力端子にそれぞれ接続され、各アンプ
より、電圧V0 ,V2 , V3 ,V5 が出力される。接続
点p2 ,p3 ,p10,p11はオペアンプop2 ,o
3 ,op8 ,op9 の入力にそれぞれ接続される。接
続点p4 ,p6,p7 はスイッチSW1 の可動接点a,
b,cにそれぞれ接続され、その固定接点dはオペアン
プop4 の入力に接続される。また接続点p9 ,p7
6 はスイッチSW2 の可動接点a,b,cに接続さ
れ、その固定接点dはオペアンプop7 の入力に接続さ
れる。
An example of such a liquid crystal drive voltage generating circuit 4
Is shown in FIG. Power supply voltage V+ IN, V- INThe voltage between
Anti-R1~ R11Divides the voltage into 12 voltage levels. this
When R1+ R2= R3+ RFour= R8+ R9= RTen+ R11 (4) Therefore, V0-V1b= V1b-V2= V3-V4b= V4b-VFive (5) Resistor R1One end p1, Resistor RFourAnd RFiveWith
Connection point pFour, R7And R8Connection point p with7, Resistor R11of
One end p11Is an operational amplifier (op amp)1, OpFive,o
p6, OpTenConnected to the input terminals of
Therefore, the voltage V0, V2, V3, VFiveIs output. Connection
Point p2, P3, PTen, P11Is the op amp2, O
p3, Op8, Op9Connected to each input. Contact
Continuation point pFour, P6, P7Is the switch SW1Movable contact a,
b and c, respectively, and their fixed contacts d are operational
PopFourConnected to the input of. Also connection point p9, P7
p6Is the switch SW2Connected to the movable contacts a, b, c of
The fixed contact d is an operational amplifier op.7Connected to the input of
Be done.

【0013】オペアンプop2 ,op3 ,op4 よりそ
れぞれ V1a=V1 +v1 ,V1b=V1 ,V1c=V1 −v2 (6) の電圧が得られ、アナログスイッチIC1 に供給され、
切換選択されて、それらのうちの一つの電圧V1 ′が出
力される。オペアンプop7 ,op8 ,op9 よりそれ
ぞれ V4a=V4 +v2 ,V4b=V4 ,V4c=V4 −v1 (7) の電圧が得られ、アナログスイッチIC2 に供給され、
切換選択されて、それらのうちの一つの電圧V4 ′が出
力される。アナログスイッチIC1 ,IC2 はスイッチ
制御回路CTLにより制御されて、切換動作が行われ、
図3に示したように従来の電圧V1 ,V4 に振幅が
1 ,v2 の正、負のパルスを重畳した波形が得られ
る。
Voltages V 1a = V 1 + v 1 , V 1b = V 1 , V 1c = V 1 −v 2 (6) are obtained from the operational amplifiers op 2 , op 3 , and op 4 , respectively, and the analog switch IC 1 is supplied with the voltages. Supplied,
It is switched and selected, and one of them, voltage V 1 ′, is output. From the operational amplifiers op 7 , op 8 , and op 9 , the voltages V 4a = V 4 + v 2 , V 4b = V 4 , V 4c = V 4 −v 1 (7) are obtained, respectively, and supplied to the analog switch IC 2 .
It is switched and selected, and one of them, voltage V 4 ′, is output. The analog switches IC 1 and IC 2 are controlled by a switch control circuit CTL to perform a switching operation,
As shown in FIG. 3, a waveform is obtained in which positive and negative pulses having amplitudes v 1 and v 2 are superimposed on the conventional voltages V 1 and V 4 .

【0014】図4より分かるようにV1a<V0 ,V1c
3 である。つまり、V3 <V1 ′<V0 に設定され
る。従って、 v1 =V1a−V1 <V0 −V1 =V (8) 同様に図4より、 v2 =V1 −V1c<V1 −V3 =V+V2 −V3 =VLCD −3V (9) である。また、V4c>V5 ,V4a<V2 とされる。つま
り、V5 <V4 ′<V2に設定される。従って、 v1 =V4 −V4c<V4 −V5 =V (10) v2 =V4a−V4 <V2 −V4 =V2 −V3 +V=VLCD −3V (11) 図1に示すのは、フレームF1 (F2 )において、1走
査期間T/mに負、正、負、正(正、負、正、負)の4
個のパルスを走査電圧Vi,j に重畳させた場合である。
この例では正、負のパルスの振幅v1 ,v2 に差を付け
ている。
As can be seen from FIG. 4, V 1a <V 0 , V 1c >
It is V 3 . That is set to V 3 <V 1 '<V 0. Therefore, v 1 = V 1a −V 1 <V 0 −V 1 = V (8) Similarly, from FIG. 4, v 2 = V 1 −V 1c <V 1 −V 3 = V + V 2 −V 3 = V LCD It is -3V (9). Further, V 4c > V 5 and V 4a <V 2 are set. That is, V 5 <V 4 ′ <V 2 is set. Therefore, v 1 = V 4 −V 4c <V 4 −V 5 = V (10) v 2 = V 4a −V 4 <V 2 −V 4 = V 2 −V 3 + V = V LCD −3V (11) FIG. 1 shows that in the frame F 1 (F 2 ), four negative, positive, negative, and positive (positive, negative, positive, negative) scans are made in one scanning period T / m.
This is a case where the individual pulses are superimposed on the scanning voltage V i, j .
In this example, positive and negative pulse amplitudes v 1 and v 2 are differentiated.

【0015】図5に示すのは、フレームF1 (F2 )に
おいて、1走査期間T/mに、パルス幅がほゞ1走査期
間の1/2の正(負)のパルスを1個走査電圧VYjに重
畳させた場合である。既に図13に関して述べたよう
に、選択パルスによって透過率Tが最大値Tmax に達し
ても、その後すぐ落ち込みだすが、透過率Tは重畳した
パルスに追従して応答するので、落ち込みの程度を緩和
することができる。図6B,Cには、図6A(図1Bと
同じパルス波形で、振幅をVに選んでいる)に示すよう
にパルスを重畳させた場合の透過率Tの応答波形を、従
来の駆動方法と比較して示している。一般型LCD及び
高速応答LCDとも、この発明のパルスを重畳させて駆
動させた場合の方が従来の駆動方法より透過率の落ち込
みが小さいことが分かる。なお、図6ではフレーム周波
数f=1/T=64Hz,走査電極数m=200本として
いる。
FIG. 5 shows that in frame F 1 (F 2 ), one positive (negative) pulse having a pulse width of approximately ½ of one scanning period is scanned in one scanning period T / m. This is the case where it is superimposed on the voltage V Yj . As already described with reference to FIG. 13, even if the transmittance T reaches the maximum value Tmax due to the selection pulse, it immediately starts to drop, but the transmittance T responds to the superposed pulse, so the degree of the drop is reduced. can do. FIGS. 6B and 6C show response waveforms of the transmittance T when the pulses are superimposed as shown in FIG. 6A (the same pulse waveform as that of FIG. 1B, with the amplitude being selected as V) when compared with the conventional driving method. The comparison is shown. It can be seen that in both the general type LCD and the fast response LCD, the drop of the transmittance is smaller when the pulse of the present invention is driven for superposition than that of the conventional driving method. In FIG. 6, the frame frequency f = 1 / T = 64 Hz and the number of scanning electrodes m = 200.

【0016】パルス幅は1走査期間T/mより小さく、
多くの場合T/mの数分の1乃至10数分の1に選ばれ
る。また、正または負のパルスを信号電圧あるいは走査
電圧のいずれに重畳する場合でも、重畳後のVXiまたは
Yjの電圧波形が図1,図2の最大電圧V0 と最小電圧
5 との範囲を越えなければよい。従って、液晶駆動電
圧発生回路は図4の場合に限らない。
The pulse width is smaller than one scanning period T / m,
In many cases, it is selected to be a fraction of T / m to a fraction of ten. In addition, when the positive or negative pulse is superposed on either the signal voltage or the scanning voltage, the voltage waveform of V Xi or V Yj after superposition is the maximum voltage V 0 and the minimum voltage V 5 of FIGS. It should not exceed the range. Therefore, the liquid crystal drive voltage generation circuit is not limited to the case of FIG.

【0017】[0017]

【発明の効果】この発明によれば、1走査期間T/mよ
り幅の狭い正、負のパルスが、1フレーム期間に少なく
とも1個、画素印加電圧に重畳されるので、画素の光透
過率Tが、それらのパルスに追従して変動し、その結
果、選択パルス間で生じる光透過率の落ち込みの程度が
緩和される。
According to the present invention, at least one positive and negative pulse having a width narrower than one scanning period T / m is superimposed on the pixel applied voltage in one frame period, so that the light transmittance of the pixel is increased. T varies in accordance with those pulses, and as a result, the degree of the drop in the light transmittance that occurs between the selection pulses is reduced.

【0018】従って、従来問題とされていたところの、
液晶の1走査時間が短く、かつ高速応答化されるために
生じた透過率の落ち込みによる画面の輝度の低下及びフ
リッカー現象を緩和することができる。
Therefore, there has been a problem in the past,
It is possible to mitigate a decrease in screen brightness and a flicker phenomenon due to a drop in transmittance caused by a short scan time of liquid crystal and high-speed response.

【図面の簡単な説明】[Brief description of drawings]

【図1】第1行〜第m行のi列の画素を全て点灯させる
場合に、走査電圧VYjの非選択期間に正、負のパルスを
重畳させたこの発明の実施例を示す液晶パネルの要部の
波形図。
FIG. 1 is a liquid crystal panel showing an embodiment of the present invention in which positive and negative pulses are superimposed during a non-selection period of a scanning voltage V Yj when all pixels in the i-th column in the first row to the m-th row are turned on. Waveform diagram of the main part of.

【図2】この発明の他の実施例を示す液晶パネルの要部
の波形図。
FIG. 2 is a waveform diagram of a main part of a liquid crystal panel showing another embodiment of the present invention.

【図3】図2Bの走査電圧VYjの波形の一部を拡大して
示した波形図。
FIG. 3 is an enlarged waveform chart showing a part of the waveform of the scanning voltage V Yj in FIG. 2B.

【図4】この発明で用いる液晶駆動電圧発生回路の一例
を示す回路図。
FIG. 4 is a circuit diagram showing an example of a liquid crystal drive voltage generation circuit used in the present invention.

【図5】この発明の更に他の実施例を示す液晶パネルの
要部の波形図。
FIG. 5 is a waveform diagram of a main part of a liquid crystal panel showing still another embodiment of the present invention.

【図6】画素印加電圧に対する画素の光透過率の応答を
示す波形図。
FIG. 6 is a waveform diagram showing a response of light transmittance of a pixel to a voltage applied to the pixel.

【図7】XY単純マトリックス液晶表示パネルの構成を
示す斜視図。
FIG. 7 is a perspective view showing a configuration of an XY simple matrix liquid crystal display panel.

【図8】図7の第1行〜第6行の第2列の画素をそれぞ
れ点灯、非点灯、点灯、…させる場合の信号電圧VX2
走査電圧VY4及び点灯される画素D2,4 の印加電圧V2,
4 を示す波形図。
8 is a signal voltage V X2 for turning on, off, turning on, and so on the pixels in the second column of the first row to the sixth row of FIG. 7, respectively.
The scan voltage V Y4 and the applied voltage V 2, to the illuminated pixel D 2,4
Waveform diagram showing 4 .

【図9】図7の第1行〜第6行の第2列の画素をそれぞ
れ非点灯、点灯、非点灯、点灯、…させる場合の信号電
圧VX2,走査電圧VY3及び非点灯の画素D2,3 の印加電
圧V2,3 を示す波形図。
9 shows a signal voltage V X2 , a scan voltage V Y3, and a non-lighted pixel when the pixels in the second column of the first row to the sixth row of FIG. 7 are turned off, turned on, turned off, turned on, ... waveform diagram showing applied voltage V 2,3 of D 2,3.

【図10】XY単純マトリックス液晶表示装置の構成を
示すブロック図。
FIG. 10 is a block diagram showing the configuration of an XY simple matrix liquid crystal display device.

【図11】図10の液晶パネル1において、第1行〜第
m行の第i列の画素を全て点灯させる場合の、信号電圧
Xi,走査電圧VYj及び点灯される画素Di,j の印加電
圧Vi,j を示す波形図。
11 is a diagram illustrating a liquid crystal panel 1 of FIG. 10, in which all the pixels in the i-th column in the first row to the m-th row are lit, the signal voltage V Xi , the scanning voltage V Yj, and the lit pixel D i, j. 5 is a waveform diagram showing the applied voltage V i, j of FIG.

【図12】図10の液晶パネル1において、第1行〜第
m行の第i列の画素をそれぞれ点灯、非点灯、点灯、…
させる場合の信号電圧VXi,走査電圧VYj及び点灯され
る画素Di,j の印加電圧Vi,j を示す波形図。
12] In the liquid crystal panel 1 of FIG. 10, the pixels in the i-th column in the first row to the m-th row are lit, non-lit, lit, ...
FIG. 6 is a waveform diagram showing a signal voltage V Xi , a scanning voltage V Yj, and an applied voltage V i, j of a pixel D i, j to be turned on in the case of making it.

【図13】従来の駆動方法で図10の液晶パネルを駆動
した場合の画素Di,1 (Xi ,Y 1 の交差点の画素)の
画素印加電圧に対する画素の光透過率の応答を示す波形
図。
FIG. 13: Driving the liquid crystal panel of FIG. 10 by a conventional driving method.
Pixel D wheni, 1(Xi, Y 1Pixel of intersection)
Waveform showing the response of pixel light transmittance to pixel applied voltage
Fig.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 XYマトリックス液晶表示装置の信号電
極または走査電極の駆動電圧に、1走査期間より短い幅
の正、または負のパルスを1フレーム期間当たり少なく
とも1個重畳させることを特徴とする液晶表示装置の駆
動方法。
1. A liquid crystal comprising at least one positive or negative pulse having a width shorter than one scanning period superposed on a drive voltage of a signal electrode or a scanning electrode of an XY matrix liquid crystal display device. Driving method of display device.
【請求項2】 XYマトリックス液晶表示装置の各走査
電極の駆動電圧に対して、その走査電極の非選択期間に
おいてパルスを重畳することを特徴とする請求項1記載
の液晶表示装置の駆動方法。
2. The method of driving a liquid crystal display device according to claim 1, wherein a pulse is superimposed on a drive voltage of each scan electrode of the XY matrix liquid crystal display device during a non-selection period of the scan electrode.
JP24181291A 1991-09-20 1991-09-20 Method for driving liquid crystal display Pending JPH0651272A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24181291A JPH0651272A (en) 1991-09-20 1991-09-20 Method for driving liquid crystal display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24181291A JPH0651272A (en) 1991-09-20 1991-09-20 Method for driving liquid crystal display

Publications (1)

Publication Number Publication Date
JPH0651272A true JPH0651272A (en) 1994-02-25

Family

ID=17079871

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24181291A Pending JPH0651272A (en) 1991-09-20 1991-09-20 Method for driving liquid crystal display

Country Status (1)

Country Link
JP (1) JPH0651272A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100407281C (en) * 2005-01-31 2008-07-30 友达光电股份有限公司 Grid driving method and circuit of liquid crystal displaying device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100407281C (en) * 2005-01-31 2008-07-30 友达光电股份有限公司 Grid driving method and circuit of liquid crystal displaying device

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