JPH0650850B2 - Data transmission method between different speed time division multiplex transmission lines - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission method between different speed time division multiplex transmission lines used in a loop type network, a bus type network and the like.

2. Description of the Related Art Conventionally, a relay terminal station device used in this type of data transmission method is configured so that line concentrating multiplexing can be performed with respect to an opposing digital transmission line. FIG. 3 shows a conventional multiplexing method. In FIG. 3, reference numeral 1 is a multiplexer, which inputs low-speed frames 2, 3, 4, and 5. 6 is a high-speed frame after multiplexing these frames, and 7 is a highway switch. Next, the operation of the above conventional example will be described. In FIG. 3, the multiplexer sequentially takes in the time slots of the low speed frames 2, 3, 4, 5 and sends them to the high speed frame 6 in the frame order. When receiving a high-speed frame, the flow of transmission is the reverse of transmission.

In this way, even with the conventional multiplexing device, data transmission can be performed by matching different speed frames.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, since the above-mentioned conventional relay terminal equipment is intended for line concentrating multiplexing, a loop type or bus type time division multiplex transmission line and a low speed side terminal in the relay terminal equipment are used. There is a problem that different speed data transmission between the division multiplex transmission lines and arbitrary line exchange cannot be performed.

The present invention solves such conventional problems,
A line having an arbitrary transmission capacity that is an integral multiple of a unit time slot is connected by a trunk transmission line and a transmission line in a relay terminal device,
It is an object of the present invention to provide an excellent data transmission method capable of converting a transmission rate and absorbing a phase difference.

Means for Solving the Problems In order to achieve the above object, the present invention provides a frame header timing matching circuit between a trunk transmission line and a low speed side transmission line to enable different speed transmission between both transmission lines. In addition, a time slot instruction memory and a transmission path memory are further provided, and for a line having a transmission capacity that is an integral multiple of a unit time slot, it is possible to exchange at any time slot position between the main transmission path and the low speed side transmission path. It was done like this.

Therefore, according to the present invention, a holding memory that can access all time slots of a high-speed frame and a low-speed frame between a high-speed frame and a low-speed frame and a transmission line memory that stores all time-slot data of a high-speed frame are mounted. As a result, an arbitrary time slot can be exchanged between the high-speed frame and the low-speed frame, and it can be easily converted to a line having an integral multiple of the unit time slot.

Embodiment FIG. 1 shows the structure of an embodiment of the present invention.

In FIG. 1, reference numeral 21 is a high-speed time division multiplexed bus (hereinafter referred to as TD).
-BUS) and includes a control bus 21a, an address clock 21b, a reception data bus 21c, and a transmission data bus 21c. Reference numeral 22 is a low-speed time division multiplex bus (hereinafter abbreviated as T-BUS), which is composed of a control bus 22a, an address clock 22b, and a transmission / reception data bus 22c. 23 is a reception data RAM, 24 is a reception write controller, 25 is a reception read controller,
26 is a reception slot instruction RAM, 27 is a T-BUS timing generator, 28 is a CPU interface, 29 is a transmission data RAM, 30 is a transmission read controller, 31 is a transmission write controller, 32 is a transmission slot instruction RAM, 33
Is a switching controller, 34, 35, 38 are receivers, 36,
37 is a driver.

Next, the operation of the above embodiment will be described. TD-BUS
The address clock 21b of 21 is received via the receiver 34 and used as the memory address signal of the reception data RAM 23 and the transmission slot instruction RAM 32. The reception write controller 24 receives the reception control timing from the control bus 21a of the TD-BUS 21, and writes all the reception data for one frame of the TD-BUS into the reception data RAM 23. On the other hand, in the reception slot instruction RAM 26, instruction information for transmitting the content of the reception data RAM from the CPU via the CPU interface 28 to an arbitrary time slot of the T-BUS 22 is previously written. The reception slot instruction RAM 26 is addressed by the signal incremented by the transmission clock of the T-BUS 22 in the timing generator 27 of the T-BUS 22, and the reception data RA pointed to by the reception slot instruction RAM 26 in sequence.
The contents of M23 (that is, the time slot information of TD-BUS21) is sent to T-BUS22 via the read driver 37 under the control of the reception read controller 25.

Similarly, from the T-BUS22 data bus 22c to the receiver
Transmit via 38 Write controller 31 TB-BU
Store the data to be sent to S21 in the transmission data RAM 29,
Addressing from the transmission slot instruction RAM 32 causes the transmission data RAM 29 to be transmitted to the transmission data bus of the TB-BUS 21 via the driver 36 under the control of the transmission read controller 30. The switching controller 33, the transmission / reception slot instruction RAMs 24 and 32, and the transmission / reception data RAMs 23 and 29, which are duplicated to maintain the bit sequence of the transmission line when changing the information for exchanging time slots, are switched in synchronization with the frame.

FIG. 3 is an example showing an outline in which the information of the received data frame of TD-BUS 101 is exchanged and transmitted to the data frame of T-BUS 104. Information (data “55”) 105 of the 30th time slot in the TD-BUS 101 is stored in the memory 106 of the 30th address of the reception data RAM 102. On the other hand, if the CPU holds the holding information “0030” in the first memory 107 of the reception slot instruction RAM 103 in advance, the content “55” is read from the memory 30 of the reception data RAM 102 and the address 0 of T-BUS is read. Information “55” at the timing assigned to each time slot
Is sent.

EFFECTS OF THE INVENTION As is apparent from the above embodiment, the present invention is designed to perform data transfer in synchronization between time-division multiplex transmission lines having different speeds, and to arbitrary time slots. It has the advantage of being able to send and receive position information. Further, by combining the time slot instruction memory and the transmission path memory, it is possible to exchange an arbitrary number of arbitrary time slots.

[Brief description of drawings]

FIG. 1 is a block diagram of a device to which a data transmission method between different speed time division multiplex transmission lines in one embodiment of the present invention is applied, FIG. 2 is an explanatory diagram for explaining the operation of the device, and FIG. It is a block diagram for explaining the conventional data transmission method. 21 ... TD-BUS, 22 ... T-BUS, 23 ... Reception data RAM, 24 ... Reception write controller, 25 ... Reception read controller, 26 ... Reception slot instruction RA
M, 27 ... T-BUS timing generator, 28 ... C
PU interface, 29 ... Transmission data RAM, 30 ...
Transmission read controller, 31 ... transmission write controller, 32 ... transmission slot instruction RAM, 33 ... switching controller, 34, 35, 38 ... receiver, 36, 37 ... driver.

Claims (1)

[Claims] 1. A circuit for adjusting transmission / reception timing of both transmission lines and absorbing a phase difference between two time division multiplex transmission lines having different speeds, and a time slot instruction memory and a transmission line memory for both transmission lines are provided. Data transmission between different speed time division multiplex transmission lines by which data transmission / reception can be performed between arbitrary time slots of two transmission lines for a line having a unit time slot and a capacity of an integral multiple thereof by combining with the above circuit. Method.