JPH065082A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To hold a protection region and a nonprotection region in completely the same manner as before a reduandant substitution even after the reduandant substitution. CONSTITUTION:In a semiconductor memory device, a memory space is provided with a protection region and a nonprotection region. The semiconductor memory device is provided with the following: a memory cell array 1 provided with a plurality of memory cells 1; reduandant memory cells 11 used to replace defective memory cells inside the memory cell array 10; and a write-protection setting means 7 which sets whether the reduandant memory cells 11 are protected or not.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, it relates to a redundancy means of a semiconductor memory device in which a part of a memory space is write-protected.

[0002]

2. Description of the Related Art FIG. 4 shows an example of a memory block of a semiconductor memory device in which a part of a memory space is write-protected. FIG. 4 shows a memory cell array 10 belonging to the memory block, a row decoder 2, a column decoder 3, a write circuit 4, a read circuit 5, and a word line 30.
And the bit line pair 47 and the like are schematically shown.
The memory cell array 10 has memory cells 1 arranged in rows and columns.

This memory block has 256 word lines 30 extending from the row decoder 2. The row decoder 2 decodes the row address (RA0-RA7) to select one word line 30 from the 256 word lines 30. Row address (RA0-R
Word line 30 selected when all of A7) are 0
As the 0th word line 30 and the row address (RA0-
Word line 3 selected when all of RA7) are 1
0 is the 255th word line 30.

This semiconductor memory device is provided with write protection means (hereinafter referred to as "protection means"). This protect means has a write protection setting means (hereinafter referred to as “protection setting means”) 6 provided for each word line 30. Each protection setting means 6 is a transistor whose gate is connected to the word line 30. One of the source / drain of this transistor is connected to the pull-up element 101 via the common node 100. The other of the source / drain of the transistor is grounded. As will be described later, by adjusting the threshold value of this transistor, it is possible to set a protected area and a non-protected area for each word line 30.

The write circuit 4 has a terminal for write data which receives write data, a WE terminal which receives a write enable (WE) signal indicating a write command from the outside, and a protect signal which receives a protect signal from the write protect means. A terminal 9 for programming and a program terminal are provided. In normal memory usage, WE
The write circuit 4 writes data in the selected memory cell 1 only when both the signal and the protect signal are at the H level. That is, if the protect signal is at L level, even if the WE signal is at H level,
The writing of data by the writing circuit 4 is not executed.
Further, when writing to the protect area, that is, when performing programming, by setting the program terminal to the H level, it becomes possible to write to the protect area.

The memory block of this semiconductor memory device is
As shown, it is divided into a protected area and a non-protected area. For example, in the memory cell array 10, when protecting the areas corresponding to the word lines 0 to 127, all the protect setting means 6 for the word lines 0 to 127 are protected.
Is set low and the thresholds of the transistors of all the protection setting means 6 for the 128th to 255th word lines are set high. More specifically,
Regarding the word lines from 0 to 127, the transistors of the protect setting means 6 are turned off when the word lines are in the non-selected state (L level), and the transistors of the protect setting means 6 when the word lines are in the selected state (H level). Turns on. Regarding the 128th to 255th word lines, the transistors of the protect setting means 6 are off both when the word lines are in the non-selected state and in the selected state. The setting of which of the protection setting means 6 the threshold value of the transistor is made higher or lower is made by using a mask in the same manner as the method of writing data in the ROM.

Next, how the protection means achieves the protection will be described more specifically. In the illustrated memory block, when any of the word lines 30 from number 0 to 127 is selected, the transistors of the protect setting means 6 for those word lines 30 are turned on, so that the node 100 switches the transistors. It is grounded through and the potential of the node 100 is pulled down to the L level. The potential of the node 100 is transmitted to the protection terminal 9 via the two-stage inverter. Therefore, when the potential of the node 100 becomes L level, the protection terminal 9 also becomes L level, and writing to the word line 30 is blocked. On the other hand, from 128 to 2
When any of the word lines 30 up to the number 55 is selected, the protection setting means 6 is off, so the node 100 is maintained at the H level via the pull-up element 101. Therefore, the protect terminal 9 also becomes H level, and if the WE signal becomes H level, the word line 3
Data is written to 0.

[0008]

Generally, a semiconductor memory device is provided with redundant means for relieving a defective bit. In the memory block of the semiconductor memory device shown in FIG. 4, a problem in the case where one redundant word line 4 and redundant row decoder 8 for relieving a defective bit are provided will be described below.

When there is a defective memory cell in the memory block, the defective word line to which the defective memory cell belongs is replaced with the redundant word line 4. This replacement is achieved by setting the defective row address in the redundant row decoder 8 and deactivating the defective word line in the row decoder 2. The substitution is specifically
It will be performed by laser trimming technology.

FIG. 4 shows the case of having a redundant word line 4 which is not protected. In this case, when a defective bit occurs in the protected area, if the defective row address to which the defective bit belongs is replaced with the redundant word line, the address is not protected. There is a problem that it ends up. This problem will be described with reference to the simplified memory maps shown in FIGS. 5 (a) and 5 (b). If a defective address occurs in the protected area as shown in FIG. 5A, the redundant memory that replaces the defective memory is not write-protected as shown in FIG. 5B. After redundant replacement, the write protect area changes.

In addition, in a memory block having a protected redundant word line 4, when a defective bit occurs in an unprotected area, the redundant word line 4 for the defective row address to which the defective bit belongs.
However, there is a problem in that the address is protected when it is replaced with. As described above, in the semiconductor memory device having the write protect area, when the redundant means is provided, there arises a problem that the write protect area changes after the redundancy repair by the redundant means.

The present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor memory in which the write protect area does not change even after redundant repair of a defective bit by redundant means. To provide a device.

[0013]

A semiconductor memory device according to the present invention is a semiconductor memory device in which a memory space has a write-protected area and a non-write-protected area. The memory cell array has, a redundant memory for replacing a defective memory cell in the memory cell array, and a write protection setting means for setting whether or not the redundant memory is write-protected. To be achieved.

When the defective memory cell is a memory cell in the write protected area, the write protection setting means is set to write protect the redundant memory, and the defective memory cell is written to the defective memory cell. In the case of a memory cell in an unprotected area, it is preferable that the redundant memory is set so as not to be write-protected.

In a preferred embodiment, the redundant memory has a unit capacity, and the defective memory cell is replaced for each unit capacity.

[0016]

EXAMPLES The present invention will be described below with reference to examples.

FIG. 1 shows a configuration example of a memory block included in the semiconductor memory device according to the first embodiment of the present invention. This memory block is similar to the memory block of the semiconductor memory device shown in FIG. 4, and has a memory cell array 10 having a plurality of memory cells 1 arranged in rows and columns.
A row decoder 2 and a column decoder 3 for selecting a desired memory cell 1 from the memory cell array 10, a plurality of word lines 30 and a plurality of bit line pairs 47,
A write circuit 4 for writing data to the selected memory cell 1, a read circuit 5 for reading data from the selected memory cell 1, and a memory cell array 10.
A plurality of redundant memory cells 11 for replacing the defective memory cell therein, a redundant word line 4 for the redundant memory cell 11, and a redundant row decoder 8 for selecting the redundant word line 4 are provided.

Each memory cell 1 has a bit line pair 47.
And word line 30. The bit line pair 47 is connected to the data line 15 via a transistor. The transistor opens and closes according to the column selection signal 46 output from the row decoder 3. Data line 15
Are connected to the write circuit 4 and the read circuit 5.

This semiconductor memory device has a protection means, and has a protected area (protected area) and an unprotected area (non-protected area) in the memory space. This protection means
It has a plurality of protect setting means 6 provided for each word line 30. The protection setting means 6 of this embodiment is a transistor (storage means) whose gate is connected to the word line 30. Source of this transistor /
One of the drains has a common node 10 of the protection means.
It is connected to the pull-up element 101 via 0.
The other of the source / drain of the transistor is grounded. The method of protection is the same as the method described for the semiconductor memory device shown in FIG.

The semiconductor memory device of this embodiment further comprises a redundant memory protect setting means 7 for setting whether or not to protect the redundant memory cell 11. As shown in FIG. 1, the redundant memory protection setting means 7 of the present embodiment has a simple structure including a transistor 7a and a fuse 7b. This transistor 7a is
MOSFET having gate electrode and source / drain
The gate electrode is connected to the redundant word line 4, one of the source / drain is connected to the node 100, and the other is grounded via the fuse 7b. Thus, the redundant memory protect setting means 7 in this embodiment is arranged in parallel with the protect setting means 6 for the other word lines 30.

The redundant memory protect setting means 7 is provided for the memory cell 1 in the area where the defective memory cell is protected.
Is set to protect the redundant memory cell, and if the defective memory cell is the memory cell 1 in the unprotected area, the redundant memory cell 1
It is set so that 1 is not protected. This setting is
This is executed by setting the fuse 7b of the redundant memory write setting means 7 to the short state or the open state.

The redundancy repair carried out in this embodiment will be described in more detail below. First, the row address including the defective memory cell is set in the redundant row decoder 8 by laser trimming, and the word line 30 including the defective memory cell is deactivated in the row decoder 2. Such setting is performed by melting a predetermined fuse provided in the redundant row decoder 8 and the row decoder 2 by laser trimming. When the defective memory cell is the memory cell 1 in the protected area, the redundant memory protect setting means 7 is used during the laser trimming.
Fuse 7b is cut by laser trimming. On the other hand, when the defective memory cell is the memory cell 1 in the unprotected area, the fuse 7b of the redundant memory protect setting means 7 is maintained as it is without being cut.

The redundant memory (redundant row) of this embodiment has a predetermined unit capacity, and defective memory cells are replaced for each unit capacity. The number of redundant memory lines may be plural. In that case, the redundant memory protect setting means 7 is provided for each redundant memory line.

FIG. 2 shows a configuration example of a semiconductor memory device according to the second embodiment of the present invention. This semiconductor memory device includes a memory cell array 10 having a plurality of memory cells 1.
A row decoder 2 and a column decoder 3 for selecting a desired memory cell 1 from the memory cell array 10, a write circuit 4 for writing data to the selected memory cell 1, and data from the selected memory cell 1. A read circuit 5 for reading data, a redundant memory cell 11 for replacing a defective memory cell in the memory cell array 10,
Redundant bit line pair 147 of redundant memory cell 11,
A redundant column decoder 13 for selecting the redundant bit line pair 147.

The semiconductor memory device of this embodiment has the protect setting means 14 for each bit line pair 47, in other words, for each column address. Each protection setting means 14 includes a transistor 14a, a pull-up element 14b,
It has an AND gate 14c and an OR gate. The gate of the transistor 14a receives the WE signal, one of the source / drain is grounded, and the other of the source / drain is connected to the pull-up element 14b and the second input terminal of the OR gate. The first input terminal of the OR gate is connected to the program terminal. The output terminal of the OR gate is connected to the first input terminal of the AND gate 14c.
The second input terminal of the AND gate 14c is connected to the column decoder 3. The memory space of this semiconductor memory device has a protected area and a non-protected area that are divided by column addresses.

The protection for each column address will be described below. When receiving the WE signal, the write circuit 4 of the present embodiment transfers the write data to the data line 15, but when the selected column (bit line pay 47) is in the protect area, the output 50 of the protect setting means 14 is output.
Accordingly, write protection is realized by disconnecting the data line 15 and the bit line pair 47.

A more specific description will be given. In the following, first, the operation when the program terminal in the normal use state is at the L level will be described. For the non-protected area, the transistor 14a of the protect setting means 14
Has a high threshold value. More specifically, the transistor 14a is off regardless of whether the gate of the transistor 14a is at the H level or the L level. Therefore, the second input terminal of the two input terminals (first and second input terminals) of the OR gate, which is connected to the pull-up element 14b, is always H level by the pull-up element 14b.
Hold on to the level. Therefore, if the potential of the second input terminal of the AND gate 14c becomes H level due to the potential of the selected column decode signal line 46, the bit line pair 47 and the data line 15 are surely connected. .

On the other hand, in the protected area, the threshold value of the transistor 14a of the protect setting means 14 is set low. More specifically, when the gate of the transistor 14a is at H level, the transistor 14a is turned on, and when the gate of the transistor 14a is at L level, the transistor 14a is turned off. Therefore, if the WE signal is at L level, the second input terminal of the OR gate is the pull-up element 1
It is held at H level by 46. However, when the WE signal becomes H level, the transistor 14a is turned on, so that the second input terminal of the OR gate is pulled down to L level, and the output 50 of the AND gate 14c becomes L level. Therefore, even if the column (bit line pair 47) in the protected area is selected and the column selection signal 46 becomes H level, if the WE signal becomes H level, the data line 15 and the bit line pair 47 are disconnected. I will let you. The threshold value of the transistor 14a is set by using a mask as in the method of writing data in the ROM.

The present embodiment further includes a memory protection setting means 1 for a redundant column (redundant bit line pair 147).
The memory protect setting means 12 for this redundant bit line pair 147, which has 2
2a, pull-up element 12b, AND gate 12c, O
It has an R gate and a fuse 12d. The gate of the transistor 12a receives the WE signal, one of the source / drain is grounded, and the other is connected to the pull-up element 12b and the second input terminal of the OR gate via the fuse 12d. The first input terminal of the OR gate is connected to the program terminal. The output terminal of the OR gate is connected to the first input terminal of the AND gate 12c.
The second input terminal of the AND gate 12c is the redundant column decoder 1
Connected to 3. The fuse 12d between the pull-up element 12b and the transistor 12a is blown by laser trimming.

At the time of redundancy repair, the column address including the defective bit is set in the redundant column decoder 13 by laser trimming, and the column decode signal including the defective bit is deactivated in the column decoder 3. At this time, at the same time, the fuse 12d is cut or left as it is, depending on whether or not the column address including the defective bit is in the protected area.
More specifically, if the defective address is in the protected area, the fuse 12d is left as it is, and if the defective address is in the non-protected area, the fuse 12d is cut. In this manner, the redundant column address (redundant bit line pair 14
Regarding 7), write protection can also be realized.

When programming the protect area, the program terminal is set to H level and W
Set E to H level. In this case, the first input terminal of the AND gate 12c goes to the H level regardless of the setting of the protect setting means, so that even if WE is at the H level,
The output 50 becomes H level to the protect area, and writing to the protect area can be executed.

The effects of the embodiment of the present invention will be described with reference to the simplified memory maps shown in FIGS. 3 (a), 3 (b) and 3 (c). If a defective address occurs in the protected area as shown in FIG. 3A, the redundant memory that replaces the defective memory is also write-protected as shown in FIG. 3B. On the other hand, if the defective address occurs in the non-protected area, the redundant memory that replaces the defective memory is not write-protected as shown in FIG. 3C.

[0033]

As described above, according to the present invention, it is possible to set whether or not write protection is applied to the redundant memory. Therefore, even after the redundant replacement, the protected area and the non-protected area are exactly the same as those before the redundant replacement. The area can be retained.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 3 is a simplified memory map for schematically showing the effect of the embodiment of the present invention, in which (a) is a memory map before redundant replacement and (b) is redundant by a protected redundant memory. The memory map after the replacement, and (c) is the memory map after the redundant replacement by the unprotected redundant memory.

FIG. 4 is a diagram showing a configuration of a conventional example.

FIG. 5 is a simplified memory map for schematically showing the problems of the conventional example, in which (a) is a memory map before redundant replacement and (b) is redundant replacement by an unprotected redundant memory. It is a memory map after being processed.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 memory cell 2 row decoder 3 column decoder 4 write circuit 5 read circuit 6 protect setting means 7 redundant memory protect setting means 8 redundant row decoder 10 memory cell array 11 redundant memory cell

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 27/10 491 8728-4M

Claims (3)

[Claims] 1. A semiconductor memory device having a memory space having a write protected area and a non-write protected area, the memory cell array having a plurality of memory cells, and a defective memory in the memory cell array. A semiconductor memory device comprising: a redundant memory for replacing a cell; and write protection setting means for setting whether or not the redundant memory is write-protected. 2. The write protection setting means is set to write-protect the redundant memory when the defective memory cell is a memory cell in the write-protected region, and the defective memory cell is 2. The semiconductor memory device according to claim 1, wherein when the memory cell is in a region that is not write-protected, the redundant memory is set so as not to be write-protected. 3. The semiconductor memory device according to claim 1, wherein the redundant memory has a unit capacity, and the defective memory cell is replaced for each unit capacity.