JPH0650774B2 - Solid-state imaging device - Google Patents
Solid-state imaging deviceInfo
- Publication number
- JPH0650774B2 JPH0650774B2 JP59113183A JP11318384A JPH0650774B2 JP H0650774 B2 JPH0650774 B2 JP H0650774B2 JP 59113183 A JP59113183 A JP 59113183A JP 11318384 A JP11318384 A JP 11318384A JP H0650774 B2 JPH0650774 B2 JP H0650774B2
- Authority
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- Japan
- Prior art keywords
- region
- layer
- conductivity type
- solid
- photoelectric conversion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000003384 imaging method Methods 0.000 title claims description 6
- 239000012535 impurity Substances 0.000 claims description 20
- 238000006243 chemical reaction Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 8
- 206010047571 Visual impairment Diseases 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000000779 depleting effect Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 101100115215 Caenorhabditis elegans cul-2 gene Proteins 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14831—Area CCD imagers
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、固体撮像装置に関するものである。TECHNICAL FIELD The present invention relates to a solid-state imaging device.
（従来例の構成とその問題点） インターライン転送方式ＣＣＤは、その低雑音特性か
ら、固体撮像素子の有力な方式として開発が進められて
いる。特に光電変換部にＰＮ接合フォトダイオード（以
下ＰＤと略記する）を用いた素子は高感度であることが
知られている。(Structure of Conventional Example and Problems Thereof) The interline transfer CCD is being developed as an effective method for a solid-state image pickup device because of its low noise characteristic. In particular, it is known that an element using a PN junction photodiode (hereinafter abbreviated as PD) in the photoelectric conversion section has high sensitivity.
第１図は、インターライン転送方式ＣＣＤの全体構成図
を示したものであり、ＰＤ１に蓄積された信号電荷は、
垂直転送ＣＣＤ２及び水平転送ＣＣＤ３を経て、電荷検
知部４で検知出力される。FIG. 1 shows an overall configuration diagram of an interline transfer type CCD, in which the signal charge accumulated in PD1 is
After passing through the vertical transfer CCD 2 and the horizontal transfer CCD 3, it is detected and output by the charge detection unit 4.
以下、第１図のＡ−Ａ′線に沿った断面構造を示す第２
図(a)を用いて説明する。第２図(a)で、ＰＤ５はＮ＋層
で形成され、そこに蓄えられた信号電荷は、転送電極７
に電圧が印加されると、読出しゲートチャンネル８を通
って垂直転送ＣＣＤチャンネル６に転送される。このと
きの電位分布を示したのが第２図(b)である。ここで９
はＰＤ領域、10は読み出しゲートチャンネル領域、11は
垂直転送ＣＣＤチャンネル領域である。Hereinafter, the second section showing the sectional structure taken along the line AA ′ of FIG.
This will be described with reference to FIG. In FIG. 2 (a), the PD 5 is formed of the N + layer, and the signal charge stored therein is transferred to the transfer electrode 7
Is applied to the vertical transfer CCD channel 6 through the read gate channel 8. The potential distribution at this time is shown in FIG. 2 (b). 9 here
Is a PD region, 10 is a read gate channel region, and 11 is a vertical transfer CCD channel region.
しかし、こうした従来例では、ＰＤ５が高濃度のＮ＋層
不純物層で形成され電子の密度が高いために、転送モー
ド時に、信号電荷が完全に垂直ＣＣＤチャンネル６に転
送されず、信号電荷の一部12が取り残されるという、い
わゆる不完全転送を生じる。この取り残し電荷は、ＰＤ
５の静電容量の大きさに比例する。取り残された信号電
荷は次回の読み出し時にまた読み出されるものとなり、
この現象により、再生画像で残像現象を生じるという不
都合が存在していた。However, in such a conventional example, since the PD 5 is formed of a high-concentration N + layer impurity layer and has a high electron density, the signal charges are not completely transferred to the vertical CCD channel 6 in the transfer mode, and one of the signal charges is not transferred. A so-called incomplete transfer occurs, in which part 12 is left behind. This residual charge is PD
It is proportional to the magnitude of the capacitance of 5. The remaining signal charges will be read again at the next read,
Due to this phenomenon, there is an inconvenience that an afterimage phenomenon occurs in a reproduced image.
（発明の目的） 本発明は、上記従来技術の欠点を克服し、残像現象を著
しく低減することができる固体撮像装置も提供すること
を目的とする。(Object of the Invention) It is an object of the present invention to provide a solid-state imaging device capable of overcoming the above-mentioned drawbacks of the prior art and significantly reducing the afterimage phenomenon.
（発明の構成） 上記目的を達成するために、本発明は、光電変換部に同
一導電型の高濃度不純物層N+)と低濃度不純物層(N-)を
共存させる構成を採っている。(Structure of the Invention) In order to achieve the above object, the present invention adopts a structure in which a high-concentration impurity layer N + of the same conductivity type and a low-concentration impurity layer (N − ) of the same conductivity type coexist.
（実施例の説明） 従来例で述べた取り残される電荷量は、信号電荷読み出
し過程の終状態におけるＰＤの静電容量に強く依存し、
この静電容量が大きくなると取り残し量が多くなる。従
って、上記静電容量を小さくすることによって取り残し
量を少なくすることができる。その方法について、本発
明の第１の実施例を示す第３図を用いて説明する。(Explanation of Embodiment) The amount of electric charge left behind described in the conventional example strongly depends on the capacitance of the PD in the final state of the signal charge reading process,
The larger the electrostatic capacity, the larger the amount left behind. Therefore, the residual amount can be reduced by reducing the capacitance. The method will be described with reference to FIG. 3 showing the first embodiment of the present invention.
第３図(a)は、第１の実施例の断面構造を示したもの
で、光電変換部はＰＤ5aで示されており、ＰＤ5aは、13
で示された低濃度不純物層領域（以下Ｎ−層と略記す
る）と、14で示され前記Ｎ−層より高濃度の不純物層領
域（以下Ｎ＋層と略記する）で構成されている。光電変
換部ＰＤ5aを除く箇所は従前と同じである。すなわち、
光電変換部ＰＤ5aに蓄積された信号電荷を転送するため
の転送電極７と、転送された信号電荷を受け入れる、例
えば垂直転送ＣＣＤチャンネル６が用意されている。FIG. 3 (a) shows a sectional structure of the first embodiment, in which the photoelectric conversion portion is indicated by PD5a, and PD5a is 13
And, wherein N is indicated by 14 - low concentration impurity layer region (abbreviated as layer less N) - which in shown is constituted by a layer of a high concentration impurity layer region (hereinafter referred to as N + layer). The parts other than the photoelectric conversion unit PD5a are the same as before. That is,
A transfer electrode 7 for transferring the signal charge accumulated in the photoelectric conversion unit PD5a and a vertical transfer CCD channel 6 for receiving the transferred signal charge are prepared.
第３図(a)は断面図を示しているため、ＰＤ5aはＮ＋層1
4が独立した２つのＮ−層13で挟まれた形で示されてい
るが、実際の構造は、Ｎ−層13は互いに独立したもので
はなく、同一領域である。従って、Ｎ＋層14を真中にし
て左側と右側のＮ−層13の電位は相等しい。この構造に
おける読み出し時の終状態における電位分布を示したも
のが第３図(b)である。Ｎ−層13は、第３図(b)に領域1
6,17で示したように、信号電荷は全て読み出されてお
り、すなわち、空乏化状態に置かれている。シリコンの
場合Ｎ層が空乏化するための不純物濃度は3.13×1012cm
-2以下であることが必要である〔文献J.S.T.HUANG: ON
THE DESIGN OF ION IMPLANTED BURIED CHANNEL CHARGE
COUPLED DEVICES (BCCDs)(Solid-State Electronics,19
77vol 20,pp665-669)〕。Since FIG. 3 (a) shows a cross-sectional view, PD5a is N + layer 1
Although 4 is shown sandwiched between two independent N − layers 13, the actual structure is such that the N − layers 13 are not independent of each other, but in the same region. Therefore, with the N + layer 14 in the middle, the potentials of the left and right N − layers 13 are equal. FIG. 3B shows the potential distribution in the final state at the time of reading in this structure. The N − layer 13 is the region 1 in FIG. 3 (b).
As shown by 6 and 17, all the signal charges have been read out, that is, placed in a depleted state. In the case of silicon, the impurity concentration for depleting the N layer is 3.13 × 10 12 cm
-2 or less [Reference JST HUANG: ON
THE DESIGN OF ION IMPLANTED BURIED CHANNEL CHARGE
COUPLED DEVICES (BCCDs) (Solid-State Electronics, 19
77vol 20, pp665-669)).
Ｎ＋層14は、第３図(b)における領域15で示すように、
信号電荷の一部が残存し、空乏化していない。すなわ
ち、残留電荷が依然として存在するために、残像現象を
完全に抑止することはできない。しかし、空乏化した領
域Ｎ−層13は、転送すべき電荷Ｑがなく、その電位はゲ
ートチャンネル８の電位Ｖの変化に対しても不変である
から、読み出しの転送時には、１／Ｃ＝ｄＶ／ｄＱで表
わされる静電容量Ｃは信号電荷が残存しているＮ＋層14
とＰ基板との接合容量だけである。この場合の静電容量
は、ＰＤ全体がＮ＋層で形成された従前よりも大幅に低
減されるために、信号電荷がこの静電容量によって留め
られる、いわゆる信号電荷の取り残し量は著しく低減さ
れる。残留電荷が生じるか、そうでないかの差異は前に
も述べたようにＰＤの空乏化、すなわちその不純物濃度
に依存する。信号電荷の取り残し量をなくするには、Ｐ
Ｄ5aを低濃度領域で構成すればよい。しかし、不純物濃
度を低くすると、蓄積できる電子数が少なくなるので静
電容量が小さくなり、飽和特性が低下する。すなわち、
ダイナミックレンジが狭くなるので好ましくない。従っ
て、第３図(a)に示したＮ−層13とＮ＋層14の大きさの
関係は、ＰＤにおける信号電荷の取り残し量とダイナミ
ックレンジの兼ね合いで決めることになる。The N + layer 14 is, as shown by the region 15 in FIG. 3 (b),
Part of the signal charge remains and is not depleted. In other words, the residual image phenomenon cannot be completely suppressed because the residual charge still exists. However, the depleted region N − layer 13 has no charge Q to be transferred, and its potential is invariant to the change of the potential V of the gate channel 8. Therefore, 1 / C = dV during the read transfer. The electrostatic capacitance C represented by / dQ is the N + layer 14 in which the signal charge remains.
And the junction capacitance between the P substrate and the P substrate. Since the capacitance in this case is significantly reduced as compared with the conventional PD in which the entire PD is formed of the N + layer, the so-called residual amount of signal charge in which signal charges are retained by this capacitance is significantly reduced. It The difference between the residual charge and the residual charge depends on the depletion of the PD, that is, its impurity concentration, as described above. To eliminate the residual amount of signal charge, P
D5a may be formed in the low concentration region. However, when the impurity concentration is lowered, the number of electrons that can be stored is reduced, so that the capacitance is reduced and the saturation characteristic is deteriorated. That is,
The dynamic range is narrowed, which is not preferable. Therefore, the relationship between the sizes of the N − layer 13 and the N + layer 14 shown in FIG. 3 (a) is determined by the balance between the amount of signal charge left in the PD and the dynamic range.
第１の実施例では、ＰＤ5aにＮ−層13を採用したため
に、ＰＤ5aの静電容量が小さすぎるとダイナミックレン
ジが狭くなるという不都合が生ずる。この場合には、第
４図に示す第２の実施例のように、ＰＤ5bの表面にＰ層
18を形成すればよい。この場合Ｐ層18との接合面がその
静電容量に寄与するため、ダイナミックレンジを増すこ
とができる。そればかりではなく、ＰＮ接合面が表面側
にも形成されるため、短波長感度が向上するというメリ
ットがある。また、第１の実施例では、Ｎ−層13の表面
が空乏化状態のため、暗電流が発生しやすいが、第２の
実施例では表面がＰ層18で覆われているため、暗電流が
発生しにくいという利点がある。なお、Ｎ＋層14の表面
にＰ層18がなくてもかまわない。In the first embodiment, since the N − layer 13 is used for the PD 5a, if the capacitance of the PD 5a is too small, the dynamic range becomes narrow. In this case, as in the second embodiment shown in FIG. 4, a P layer is formed on the surface of PD5b.
18 may be formed. In this case, since the joint surface with the P layer 18 contributes to the electrostatic capacity, the dynamic range can be increased. Not only that, but the PN junction surface is also formed on the front surface side, which has the advantage of improving the short wavelength sensitivity. Further, in the first embodiment, since the surface of the N − layer 13 is depleted, a dark current is likely to occur. However, in the second embodiment, the surface is covered with the P layer 18, so that a dark current is generated. Has the advantage of being less likely to occur. The P layer 18 may not be provided on the surface of the N + layer 14.
次に第３の実施例を、第５図を用いて説明する。固体撮
像素子には、過大光量が入射した場合に、過剰電荷があ
ふれ出すことによって生じるブルーミング現象がある。
この対策として、第５図に示すように、Ｎ基板上にＰウ
ェル19を形成し、その中に、ＰＤ5c、垂直転送ＣＣＤ６
等を形成する方法が用いられる。このとき、ＰＤ5cの下
のＰウェルは、垂直転送ＣＣＤ６の下のＰウェルより浅
く、若しくは低濃度で形成し、Ｐウェル19とＮ基板の間
に逆バイアス電圧20を印加し、ＰＤ5cの下のＰウェルを
空乏化状態とすることによって、ＰＤ5c内の過剰電荷を
Ｎ基板に流し去る。このときＰＤ5cがＮ−層だけで形成
されている場合は、上に述べた過剰電荷の排出を制御性
よく製造することは困難である。これに対し、第５図に
示すようにＮ＋層14を形成することによって、該Ｎ＋層
の下のＰウェル19から過剰電荷を排出する素子を制御性
よく製造することができる。Next, a third embodiment will be described with reference to FIG. The solid-state imaging device has a blooming phenomenon caused by excess charge overflowing when an excessive amount of light is incident.
As a countermeasure against this, as shown in FIG. 5, a P well 19 is formed on the N substrate, in which the PD 5c and the vertical transfer CCD 6 are formed.
Etc. are used. At this time, the P well under the PD 5c is formed shallower or at a lower concentration than the P well under the vertical transfer CCD 6, a reverse bias voltage 20 is applied between the P well 19 and the N substrate, and the P well under the PD 5c is formed. By depleting the P well, excess charges in PD5c are drained to the N substrate. At this time, if PD5c is formed of only the N − layer, it is difficult to control the discharge of the excess charge described above with good controllability. On the other hand, by forming the N + layer 14 as shown in FIG. 5, it is possible to controllably manufacture an element for discharging excess charges from the P well 19 under the N + layer.
上記実施例はいずれもインターライン転送ＣＣＤで示し
たＰＮ接合フォトダイオードを光電変換部として用いる
撮像素子ならば、もちろん有効である。Any of the above embodiments is of course effective as long as it is an image pickup device using a PN junction photodiode shown as an interline transfer CCD as a photoelectric conversion unit.
（発明の効果） 以上のように、本発明は、光電変換部に高濃度不純物層
と低濃度不純物層とを共存させる構造とすることによっ
て、高濃度不純物層により静電容量の大きさを保つこと
で、ダイナミックレンジの低下を抑止し、さらに、低濃
度不純物層で構成することで、信号電荷転送時の取り残
し電荷を排除して残像現象を大幅に改善することができ
るので、その実用的効果は大なるものがある。(Effects of the Invention) As described above, according to the present invention, the structure in which the high-concentration impurity layer and the low-concentration impurity layer are allowed to coexist in the photoelectric conversion portion allows the high-concentration impurity layer to maintain the magnitude of the capacitance. By suppressing the reduction of the dynamic range, and by configuring with a low-concentration impurity layer, it is possible to eliminate the residual charge at the time of signal charge transfer and significantly improve the afterimage phenomenon. Has a great deal.
第１図は、インターライン転送ＣＣＤの構成図、第２図
(a)は、従来例の要部断面構造を示す図、第２図(b)は、
その電位分布図、第３図(a)は、本発明の第１の実施例
の要部断面構造を示す図、第３図(b)は、その電位分布
図、第４図は、本発明の第２の実施例の要部断面構造を
示す図、第５図は、本発明の第３の実施例の要部断面構
造を示す図である。 １…フォトダイオード、２…垂直転送ＣＣＤ、３…水平
転送ＣＣＤ、４…電荷検知部、5a,5b,5c…ＰＤ、６…垂
直転送ＣＣＤチャンネル、７…転送電極、８…読み出し
ゲートチャンネル、13…低濃度不純物層（Ｎ−層）、14
…高濃度不純物層（Ｎ＋層）、19…Ｐウェル。FIG. 1 is a block diagram of an interline transfer CCD, and FIG.
(a) is a diagram showing a cross-sectional structure of a main part of a conventional example, and FIG. 2 (b) is
A potential distribution diagram thereof, FIG. 3 (a) is a diagram showing a sectional structure of an essential part of the first embodiment of the present invention, FIG. 3 (b) is a potential distribution diagram thereof, and FIG. FIG. 5 is a diagram showing a cross-sectional structure of a main part of a second embodiment of the present invention, and FIG. 5 is a diagram showing a cross-sectional structure of a main part of a third embodiment of the present invention. DESCRIPTION OF SYMBOLS 1 ... Photodiode, 2 ... Vertical transfer CCD, 3 ... Horizontal transfer CCD, 4 ... Charge detection part, 5a, 5b, 5c ... PD, 6 ... Vertical transfer CCD channel, 7 ... Transfer electrode, 8 ... Read gate channel, 13 ... Low-concentration impurity layer (N - layer), 14
... High-concentration impurity layer (N + layer), 19 ... P well.
Claims (3)
電型領域の光電変換部と、前記光電変換部に蓄積された
信号電荷を転送する転送電極と、前記転送された信号電
荷を受け入れる領域とを有する固体撮像装置において、
前記光電変換部は、不純物濃度の低い第１の領域と、前
記第１の領域と同一導電型でそれよりも不純物濃度の高
い第２の領域とによって構成されていることを特徴とす
る固体撮像装置。1. A photoelectric conversion part of an opposite conductivity type region formed in one conductivity type impurity region, a transfer electrode for transferring signal charges accumulated in the photoelectric conversion part, and a part for receiving the transferred signal charges. In a solid-state imaging device having a region,
The photoelectric conversion unit is configured by a first region having a low impurity concentration and a second region having the same conductivity type as that of the first region and having a higher impurity concentration than that of the first region. apparatus.
純物領域と同一導電型不純物層が形成されていることを
特徴とする特許請求の範囲第(1)項記載の固体撮像装
置。2. The solid-state image pickup device according to claim 1, wherein an impurity layer having the same conductivity type as the one conductivity type impurity region is formed on the surface of the photoelectric conversion portion.
内に形成されていることを特徴とする特許請求の範囲第
(1)項若しくは第(2)項記載の固体撮像装置。3. An impurity region of one conductivity type is formed in a substrate of opposite conductivity type.
The solid-state imaging device according to item (1) or (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59113183A JPH0650774B2 (en) | 1984-06-04 | 1984-06-04 | Solid-state imaging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59113183A JPH0650774B2 (en) | 1984-06-04 | 1984-06-04 | Solid-state imaging device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60257566A JPS60257566A (en) | 1985-12-19 |
| JPH0650774B2 true JPH0650774B2 (en) | 1994-06-29 |
Family
ID=14605653
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59113183A Expired - Lifetime JPH0650774B2 (en) | 1984-06-04 | 1984-06-04 | Solid-state imaging device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0650774B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6255960A (en) * | 1985-09-05 | 1987-03-11 | Toshiba Corp | Solid state image pick-up device |
| JPS6318665A (en) * | 1986-07-11 | 1988-01-26 | Toshiba Corp | Solid state image sensing device |
| JPH07112054B2 (en) * | 1988-03-08 | 1995-11-29 | 株式会社東芝 | Solid-state imaging device |
| JPH04260369A (en) * | 1991-02-15 | 1992-09-16 | Matsushita Electron Corp | Solid-state image sensing device and manufacture thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57173273A (en) * | 1981-04-17 | 1982-10-25 | Nec Corp | Solid-state image pickup device |
| JPS58142682A (en) * | 1982-02-18 | 1983-08-24 | Nec Corp | Solid-state image pickup element |
| JPS59202662A (en) * | 1983-04-30 | 1984-11-16 | Sharp Corp | Solid-state image pickup device |
-
1984
- 1984-06-04 JP JP59113183A patent/JPH0650774B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57173273A (en) * | 1981-04-17 | 1982-10-25 | Nec Corp | Solid-state image pickup device |
| JPS58142682A (en) * | 1982-02-18 | 1983-08-24 | Nec Corp | Solid-state image pickup element |
| JPS59202662A (en) * | 1983-04-30 | 1984-11-16 | Sharp Corp | Solid-state image pickup device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60257566A (en) | 1985-12-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |