JPH065072A - Control method of refresh operation - Google Patents

Abstract

PURPOSE:To always execute a refresh operation at a definite cycle or lower by a method wherein, even when a bus request for the refresh operation is output, the level of the bus request is changed to a level whose priority degree is high when a definite waiting time or higher is not permitted. CONSTITUTION:When a bus request REFREQ is set effectively and 14musec elapses without being permitted, a time monitoring circuit 11 sets an output 01 effectively. Then, a bus request REFEQL becomes ineffective, and a bus request REFEQH becomes effective. In this case, a bus arbitration circuit 8a permits the bus request REFEQH even when it competes with bus requests CPUREQ, DMAREQ, and sets an acknowledgement signal REFCKH effectively. Thereby, an acknowledgement signal REFACK is output from an OR gate 15, and a refresh operation is executed forcibly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a refresh control method in which bus occupation by a refresh circuit associated with DRAM (Dynamic Random Access Memory) refresh has little effect on bus occupation by another bus master. .

[0002]

2. Description of the Related Art In a computer, a main storage device is indispensable as hardware for storing application programs and data referred to by a processor, as well as calculation results by the processor. DRAM is widely used as one of the elements constituting the main memory device. DRAM is a volatile memory. Therefore, D
When using the RAM, it is necessary to perform refresh in order to prevent the memory contents from disappearing. For this reason, a computer equipped with a DRAM is provided with a refresh circuit for controlling refresh.

FIG. 2 shows a block diagram of a general computer. The computer 1 shown in the figure includes a bus 2 including a system bus, an address bus, a data bus and the like.
The processor (CPU) 3, the direct memory access controller (DMA) 4, the refresh circuit (REF) 5, the main memory (MM) 6, and the input / output device (I
/ O) 7 and the bus arbitration circuit 8 are interconnected.

The CPU 3 executes arithmetic processing by referring to, for example, an application program, and further controls each unit constituting the computer 1 in accordance with the execution of the arithmetic processing. DMA4 is, for example, MM6 and I
The data transfer with the / O7 is performed without the control of the CPU3. REF5 is, for example, 16
The MM6 is partially refreshed within a cycle of μsec, and this is repeated 256 times, and the MM6 is refreshed in a cycle of 4096 μsec.
6 is to be refreshed. MM6
Is a storage device composed of a DRAM. Also, I
/ O7 is composed of, for example, a magnetic storage device. The bus arbitration circuit 8 determines a bus master (any one of the CPU 3, DMA 4, and REF 5) that occupies the bus 2 and uses it, and performs control to give the bus use right.

FIG. 3 shows a conceptual diagram of the bus arbitration circuit 8.
As shown in the figure, the bus arbitration circuit 8 has three input ports Ia to Ic and output ports Oa to O corresponding to the respective inputs.
c is provided. The input ports Ia to Ic are respectively connected to the CPU 3, the DMA 4, and the CPU 3 via the bus 2 shown in FIG.
Bus request CPUREQ, DMAREQ, RE output by REF5
It is a port that receives FREQ. Output ports Oa-Oc
Are the bus requests CPUREQ,
Request confirmation signal CPUAC when DMAREQ and REFREQ are allowed
This port outputs K, DMAACK, and REFACK.

The bus arbitration circuit 8 uses the bus request CPURE
Priority is set for each of Q, DMAREQ, and REFREQ. This priority level is, for example, CPUREQ <DMAREQ <RE
It is set to FREQ. That is, when three bus requests compete with each other, the bus arbitration circuit 8 determines that the bus request REFR
The request confirmation signal REFACK corresponding to the EQ is preferentially output.
If the bus requests CPUREQ and DMAREQ conflict,
The bus arbitration circuit 8 preferentially outputs the request confirmation signal DMAACK. Bus request RE output by REF5 shown in FIG.
The highest level of FREQ is because if the refresh of the MM6 is delayed, the stored contents will be erased. The bus 2 occupied time by each bus master is 1 μsec.
Is limited to. That is, when the request confirmation signal is effectively output and the bus master starts occupying the bus,
The bus request is invalidated after sec and the bus 2 is released.

Now, referring back to FIG. 2 and referring to FIG.
A conventional refresh control method will be described. Figure 4
3 is a time chart of a conventional refresh control method. At the timing T1 shown in the figure, the bus request CP of (a), (b) and (c) input to the bus arbitration circuit 8 is input.
All of UREQ, DMAREQ, and REFREQ are set to invalid (low level). That is, there is no bus master requesting the occupation of the bus 2. At timing T2, the bus arbitration circuit 8 receives the request confirmation signal after the DMA4 sets the bus request DMAREQ of (b) to valid (high level).
Set DMAACK to valid. When the DMA4 recognizes that the request confirmation signal DMAACK of (e) is set to be valid, it starts to occupy the bus 2 and transfers data for 1 μsec from the MM6 to the I / O 7, for example. Note that here, for example, the period from the timing T2 to T5 is set to 1 μsec.

Next, at timing T3, the CPU3
(A) effectively sets the bus request CPUREQ, and at timing T4, REF5 sets (c) the bus request REFREQ to valid. At timing T5, 1 μsec after the request confirmation signal DMAACK in (e) is set valid, the DMA 4 sets the bus request DMAREQ in (b) to invalid and releases the bus 2.

When the bus arbitration circuit 8 recognizes that the DMA 4 has released the bus 2 at the timing T5, (e)
At the same time as disabling the request confirmation signal DMAACK of
The bus requests CPUREQ and REFREQ in (a) and (c) are arbitrated. In this case, the (c) bus request REFREQ having a high priority level is allowed and the (f) request confirmation signal REFA is accepted.
Set CK to valid. When the REF 5 recognizes that the request confirmation signal REFACK of (f) is set to be valid, it starts occupying the bus 2 and refreshes the MM 6.

Next, at timing T6, 1 μsec after the request confirmation signal REFACK of (f) is set valid, REF5 invalidates the bus request REFREQ of (c) and releases the bus 2. .

When the bus arbitration circuit 8 recognizes that the REF 5 has released the bus 2 at the timing T6,
At the same time that the request confirmation signal REFACK in (f) is set to be invalid, the bus request CPUREQ in (a) is permitted and the request confirmation signal CPUACK in (d) is set to be valid. CPU3
When recognizing that the request confirmation signal CPUACK in (d) is set valid, the bus 2 starts to be occupied and the MM 6 is read, for example.

Thereafter, at timing T7, which is 1 μsec after the request confirmation signal CPUACK of (d) is set valid, the CPU 3 releases the bus 2 so that the bus request CPUREQ of (a) is set invalid. Bus arbitration circuit 8
In response to the bus request CPUREQ of (a) being invalidated, the request confirmation signal CPUACK of (d) is invalidated.

REF5 is (c) bus request REFREQ
At a timing T8 when 16 μsec has elapsed after the setting of (1) was enabled, the REF 5 sets the bus request REFREQ of (c) to be valid again for refreshing. At this time, the bus arbitration circuit 8 immediately sets the request confirmation signal REFACK of (f) to valid because the bus 2 is released. REF
5 starts occupying the bus 2, refreshes the MM, sets the bus request REFREQ of (c) to invalid at timing T9 1 μsec after the start of occupancy,
Release bus 2.

[0014]

In the conventional refresh control method described above, since the priority level of the bus request REFREQ output by REF5 is set to the maximum level, the bus request REFREQ conflicts with the bus request REFREQ. Must wait for the next arbitration cycle. Therefore, the bus master, which could not occupy the bus 2 due to the competition, delays the processing while waiting for the bus 2 to be permitted to be occupied. Since the DRAM refresh is always executed periodically as described above, there is a problem in that the adverse effects caused by the increase in traffic cannot be ignored. The present invention has been made by focusing on the above points,
An object of the present invention is to provide a refresh control method capable of reducing a situation in which processing of another bus master is delayed due to execution of refresh.

[0015]

According to a first aspect of the invention, when a refresh circuit for executing a refresh operation of a dynamic random access memory makes a bus request to a system bus for the refresh operation, another A bus request with a lower priority level is output as compared with the bus master, the time is counted from the time when the bus request is output, and the bus request is still output even after the allowable waiting time when the refresh operation is executed. Is not allowed, the present invention relates to a refresh control method, wherein after the waiting time has elapsed, the bus request is switched to a level having a higher priority than that of other bus masters and output.

According to a second aspect of the invention, when the refresh circuit for executing the refresh operation of the dynamic random access memory issues a bus request to the system bus for the refresh operation, the dynamic random access is performed in the first cycle t or less. A partial refresh operation of the memory is executed, and the partial refresh operation is executed N times in a second cycle N times the first cycle t to complete the entire refresh operation of the dynamic random access memory. In the normal state, the bus request having the lowest priority level is output in comparison with other bus masters, the partial refresh operation is repeatedly executed, and the partial refresh operation is performed. If the past average cycle is equal to or longer than the first cycle t, another bus master By comparison, the bus request having the highest priority level is output, the partial refresh operation is completed N times before the second cycle T9 elapses, and then the second cycle T elapses. , A refresh control method characterized by stopping the output of the bus request.

According to a third aspect of the present invention, when the refresh circuit for executing the refresh operation of the dynamic random access memory issues a bus request to the system bus for the refresh operation, the dynamic random access is performed in the first cycle t or less. A partial refresh operation of the memory is executed, and the partial refresh operation is executed N times in a second cycle N times the first cycle t to complete the entire refresh operation of the dynamic random access memory. In this case, a constant switching time S equal to or less than the second cycle T is set, and until the switching time S elapses, the bus request with the lowest priority level is compared with other bus masters. Output, repeat the partial refresh operation, and execute the switching time After the passage of time, the bus request of the highest priority level is output as compared with other bus masters, and the remaining partial refresh operation is completed before the passage of the second period T. And a refresh control method.

[0018]

In the DRAM refresh, the partial refresh is repeated N times to complete the entire refresh.
As long as the refresh is allowed within the allowed refresh cycle, the bus request of the refresh circuit has the lowest priority and does not disturb the processing of other bus masters. On the other hand, even if the bus request for refresh is output, if the bus request is not allowed for a certain waiting time or longer, the level of the bus request is automatically switched to a higher priority one. As a result, the refresh operation of the dynamic memory is always executed within a fixed period. The average cycle of the refresh operations executed up to immediately before is monitored, and when the average cycle is less than or equal to the first cycle t, the priority remains low, and when the average cycle is greater than or equal to the first cycle t, the refresh operation is prioritized. Switch to a higher degree. This makes it possible to secure N partial refresh operations at least during the second period T. When the partial refresh operation is completed N times before the second cycle T elapses, no further refresh operation is necessary, so the second cycle T
The output of the bus request may be stopped until after, and the same operation may be repeated in the next cycle.

A constant switching time S equal to or less than the second period T
During this period, the priority of the bus request for refresh is lowered, and the bus requests of other bus masters are prioritized.
After the switching time S has elapsed, if the priority of the bus request for the refresh operation is maximized, then the second
By the end of the cycle T, the refresh operation is always completed N times. Therefore, it is possible to meet the request to secure the refresh operation N times during the second period T.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention is realized by providing the above-described conventional computer with a priority changing device described below. [First Invention] FIG. 1 shows a hardware block diagram for carrying out the method of the first invention. In the figure, the priority changing device 1
0 and bus arbitration circuit 8a are shown. The bus arbitration circuit 8a corresponds to the priority levels set in four stages. In addition to the input ports Ia to Ic and the output ports Oa to Oc of the bus arbitration circuit 8 described above with reference to FIG.
The difference is that an input port Id and an output port Od are provided. The input ports Ib and Ic are ports that receive bus requests CPUREQ and DMAREQ output from the CPU 3 and the DMA 4, respectively, via the bus 2 shown in FIG. The output ports Ob and Oc are ports for outputting request confirmation signals CPUACK and DMAACK corresponding to the bus requests CPUREQ and DMAREQ permitted by the bus arbitration circuit 8a, respectively.

The input ports Ia and Id are ports for receiving bus requests REFREQL and REFREQH based on the bus request REFREQ output from the REF 5 via the bus 2 shown in FIG. 2, respectively. The output ports Oa and Od have the bus request REFREQ permitted by the bus arbitration circuit 8a.
Request confirmation signal REFACKL, REFACK corresponding to L, REFREQH
This is the port that outputs H. The bus arbitration circuit 8a sets a priority for each of the bus requests CPUREQ, DMAREQ, REFREQL, and REFREQH. The priority level is set to REFREQL <CPUREQ <DMAREQ <REFREQH. That is, for example, three bus requests REFREQL
, CPUREQ, DMAREQ conflict Bus arbitration circuit 8a
Is a request confirmation signal DM corresponding to the bus request DMAREQ.
Set only AACK to valid. Also, the bus request CPUR
When EQ and DMAREQ compete, the bus arbitration circuit 8a sets only the request confirmation signal DMAACK to valid.

The priority changing device 10 includes a time monitoring circuit 11, a NOT gate 12, AND gates 13 and 14.
And an OR gate 15 are provided. Time monitoring circuit 1
The bus request REFREQ is input to one input port I1 and one input of the AND gates 13 and 14. The output port O1 of the time monitoring circuit 11 is connected to the other input of the AND gate 14 and is also connected to the other input of the AND gate 13 via the NOT gate 12. AN
The output of the D gate 13 is input to the input port Ia of the bus arbitration circuit 8a as a bus request REFREQL generated based on the bus request REFREQ. AND gate 1
The output of 4 is input to the input port Id of the bus arbitration circuit 8a as a bus request REFREQH generated based on the bus request REFREQ.

The input of the OR gate 15 is connected to the output ports Oa and Od of the bus arbitration circuit 8a, and the OR gate 1
5, the request confirmation signal REFA based on the request confirmation signals REFACKL, REFACKH output from the output ports Oa, Od.
CK is output. The bus request REFREQ and the request confirmation signal REFACK are transmitted between the bus 2 and the bus arbitration circuit 8a shown in FIG. 2 via the priority changing device 10. The time monitoring circuit 11 normally keeps the output port O1 invalid (low level) and measures a fixed time after the bus request REFREQ is set valid. For example, after 14 μsec has elapsed, the output port O1 is valid (high level). It is composed of a gate circuit and a timer.
This 14 μsec is called a waiting time in the present invention.

That is, when the bus request REFREQ is set to be valid, the bus request REFREQ is held for a maximum of 14 μsec.
L becomes valid and the bus arbitration circuit 8a makes a bus request.
It will arbitrate for REFREQL, CPUREQ, and DMAREQ.
When only the bus request REFREQL is valid, the request confirmation signal REFACKL becomes valid, and the OR gate 15 outputs the request confirmation signal REFACK. Also, bus request RE
When 14 μsec elapses after FREQ is set valid and is not allowed, the time monitoring circuit 11 sets the output port O1 valid. As a result, the bus request REFREQL becomes invalid and the bus request REFREQH becomes valid. In this case, the bus arbitration circuit 8a uses the bus requests CPUREQ, DM
Allow bus request REFREQH even if it conflicts with AREQ,
Set the request confirmation signal REFACKH to valid. This allows
A request confirmation signal REFACK is output from the OR gate 15. Therefore, if the bus request REFREQ is not allowed within 14 μsec, the priority is maximized to 16 μsec.
Operates to force a refresh within.

Here, the refresh control method of the present invention will be described with reference to FIG. FIG. 5 is a time chart of the refresh control method of the present invention. At the timing T11 shown in the figure, (a) (b) (c)
All bus requests CPUREQ, DMAREQ, and REFREQ of are set to invalid (low level). That is, there is no bus master requesting the occupation of the bus 2. Timing T12
In response to the fact that the DMA 4 has set the bus request DMAREQ of (b) to valid (high level), the bus arbitration circuit 8a sets the request confirmation signal DMAACK of (h) to valid. When the DMA 4 recognizes that the request confirmation signal DMAACK of (h) is set to be valid, it starts to occupy the bus 2 and transfers data from the MM 6 to the I / O 7 shown in FIG. 2, for example.

Next, at timing T13, REF5
Sets (c) the bus request REFREQ to valid, and at timing T14, the CPU 3 sets (a) the bus request CPUREQ to valid. Request confirmation signal of (h)
At timing T15, which is 1 μsec after DMAACK is set to be valid, the DMA4 invalidates the bus request DMAREQ in (b) and releases the bus 2. At timing T15, the bus arbitration circuit 8a causes the DMA4
Recognizes that the bus 2 has been released, the request confirmation signal DMAACK in (h) is set to be invalid, and at the same time, the time monitoring circuit 11 outputs based on the bus request CPUREQ and the bus request REFREQ in (a) and (b) ( e) Bus request RE
FREQL arbitration is performed. In this case, high level bus request CPUREQ is allowed and request confirmation signal CPUACK of (g)
To enable. CPU3 is the request confirmation signal of (g)
When recognizing that the CPUACK is set to be valid, the bus 2 is started to be occupied and the data writing to the MM 6, for example, is executed.

Next, at timing T16, 1 μsec after the request confirmation signal CPUACK of (g) is set valid, the CPU 3 invalidates the bus request CPUREQ of (a) and releases the bus 2. . Bus arbitration circuit 8a
Recognizes that the CPU 3 has released the bus 2 at the timing T16, the request confirmation signal CPUACK of (g) is set to be invalid, and at the same time, the bus request REFR of (e) is set.
Allow EQL and set request confirmation signal REFACK in (i) to valid. The priority changing device 10 outputs REFACKL as the request confirmation signal REFACK of (i). REF5 is (i)
When it recognizes that the request confirmation signal REFACK of is set to be valid, the bus 2 starts to be occupied and the MM 6 is refreshed.

Thereafter, a timing T17 at which 1 μsec has elapsed after the request confirmation signal REFACK of (i) is set to be valid
At REF5, the bus request REFREQ of (c) is set to be invalid in order to release the bus 2. The bus arbitration circuit 8a invalidates the request confirmation signal REFACK of (i) in response to the invalidation of the bus request REFREQ of (c).

After REF5 sets the bus request REFREQ of (c) to valid at timing T13, timing T1 immediately before 16 μsec (timing T19 arrives) is reached.
8, when the bus 4 is released, the DMA 4 sets the bus request DMAREQ of (b) to valid (high level), the bus arbitration circuit 8a sets the request confirmation signal DMAACK of (h) to valid. After that, timing T19
At REF5, the bus request REFREQ of (c) is set to valid, and at timing T20, the CPU
3 sets the bus request CPUREQ in (a) to valid.
1 after the request confirmation signal DMAACK in (h) is set to valid
At timing T21 after the elapse of μsec, the DMA4 invalidates the bus request DMAREQ of (b), and the bus 2
Release.

When the bus arbitration circuit 8a recognizes that the DMA4 has released the bus 2 at the timing T21,
At the same time as disabling the request confirmation signal DMAACK in (h), the bus request REFREQL output from the time monitoring circuit 11 is arbitrated based on the bus request CPUREQ in (a) and the bus request REFREQ in (c). Allow high level (a) bus request CPUREQ (g)
The request confirmation signal CPUACK of is set to valid.

Next, a timing T2 before 1 μsec has elapsed after the request confirmation signal CPUACK of (g) is set to be valid.
2, the DMA4 again requests the bus request DM of (b).
Set AREQ to valid. Timing T2 after 1 μsec has elapsed since the request confirmation signal CPUACK in (g) was enabled
3, the CPU 3 uses the bus request CPUREQ of (a)
Is disabled and the bus 2 is released.

When the bus arbitration circuit 8a recognizes that the CPU 3 has released the bus 2 at the timing T23,
At the same time as disabling the request confirmation signal CPUACK of (g), the bus request REFREQL of (e) output from the time monitoring circuit 11 is arbitrated based on the bus requests DMAREQ and REFREQ of (b) and (c). . In this case, the high level (b) bus request DMAREQ is permitted and the request confirmation signal DMAACK (h) is set to be valid.

Thereafter, it is assumed that the processing in which the CPU 3 and the DMA 4 alternately occupy the bus 2 is continued at timings T24 to T31. At timing T32,
The CPU 3 sets the bus request CPUREQ to valid again. On the other hand, at timing T33, the time monitoring circuit 1
When 1 detects that 14 μsec has passed after the bus request REFREQ in (c) was set valid, the output port O
Set 1 to valid (high level). This allows
Instead of the bus request REFREQL of (e), the bus request REFREQH of (f) becomes valid.

At timing T34, which is 1 μsec after the request confirmation signal DMAACK in (h) is set valid, the DMA4 sets the bus request DMAREQ in (b) to invalid and releases the bus 2. The bus arbitration circuit 8a is
When the DMA4 recognizes that the bus 2 is released at the timing T34, the request confirmation signal DMAACK in (h) is set to be invalid, and at the same time, the time monitoring is performed based on the bus request CPUREQ in (a) and the bus request REFREQ in (c). Circuit 1
The bus request REFREQH of (f) output by 1 is arbitrated. In this case, the high level (f) bus request REFREQH is allowed and the request confirmation signal REFACKH shown in FIG.
To enable. Therefore, from the OR gate 15, the request confirmation signal REFA of (i) based on the request confirmation signal REFACKH.
CK will be output.

Next, the timing T3 before 1 μsec has elapsed since the request confirmation signal REFACK of (i) was set valid
5, the DMA4 again sends the bus request DM of (b).
Set AREQ to valid. Timing T3 after 1 μsec has elapsed since the request confirmation signal REFACK in (i) was set valid
6, REF6 is the bus request REFREQ of (c).
Is disabled and the bus 2 is released. At timing T36, the bus arbitration circuit 8a outputs REF6 to the bus 2
Is recognized, the request confirmation signal REFACK of FIG. 1 is recognized.
At the same time that H is set to be invalid, the bus request CPUREQ and the bus request DMAREQ in (a) and (b) are arbitrated.
In this case, the high level (b) bus request DMAREQ
And the request confirmation signal DMAACK of (h) is set to be valid. After that, at timing T37, the CPU 3 occupies the bus 2.

[Second Invention] Next, an embodiment of the second invention will be described. FIG. 6 is a hardware block diagram for implementing the method of the second invention. Here, a priority changing device 20 and a bus arbitration circuit 8a are provided.
The bus arbitration circuit 8a has exactly the same configuration as that already described in FIG. 1, and is for receiving the bus request at the input ports Ia to Id and outputting the request confirmation signal to the output ports Oa to Od. . In this example, the bus request input to the input port Ia shown in the figure has the lowest priority, and the priority is high in the order of the input ports Ib, Ic, and Id. This is also similar to the embodiment shown in FIG.

The priority changing device 20 is provided with time monitoring circuits 21 and 22, a counter 23 and an up / down counter 24. The time monitoring circuit 21 is 4096
It consists of a timer circuit that enables the RESET signal once every μsec. In addition, the time monitoring circuit 22 sets 1 every 16 μsec.
It is composed of a timer circuit which enables the time DOWN signal. In addition, to make a signal valid means to set the level of the signal to a high level. In addition, DRA in this case
M performs a partial refresh operation once in the first cycle t, that is, 16 μsec, and repeats this 256 times to complete the entire refresh operation every second cycle T, that is, 4096 μsec. To do.

The counter 23 resets the counter value when the clear terminal becomes valid and increments the counter value by 1 when the up terminal becomes valid until the counter value becomes N, that is, 256. , REFREQ
This circuit enables the 1 signal. Further, the up-down counter 24 is “0” in the initial state, is reset to “0” when the clear terminal becomes effective, and increments the count by “1” when the up terminal becomes effective, and the down terminal becomes A circuit that decrements the count by "1" when enabled, validates the REFREQ2 signal when the count value is less than "0", and invalidates this signal when the count value is "0" or greater. Composed of circuits.

At the input port Ia of the bus arbitration circuit 8a,
A signal output from the counter 23 of the priority changing device 20
REFREQ1 is input. The signal REFREQ2 is input from the up / down counter 24 of the priority changing device 20 to the input port Id of the bus arbitration circuit 8a. In addition to this, the bus request CPUR output by the CPU or the DMA is input to the input ports Ib and Ic of the bus arbitration circuit 8a, respectively.
EQ and DMAREQ are input. On the other hand, the output ports Oa and Od of the bus arbitration circuit 8a are connected to the input terminals of the OR gate 25, and the output of the OR gate 25 is output from the up terminal of the counter 23 and the up / down counter 24 of the priority changing device 20. It is connected to the up terminal. Further, the request confirmation signals CPUACK and DMAACK are output from the output ports Ob and Oc of the bus arbitration circuit 8a, and the request confirmation signal REFACK is output from the OR gate 25.

Also in this embodiment, the priority changing device 20 inputs a bus request to either the input port Ia or Id of the bus arbitration circuit 8a, as in the first embodiment of the invention described with reference to FIG. The bus arbitration circuit 8a adjusts the bus request from another bus master according to the priority, and then requests the request confirmation signal REFACK from the OR gate 25.
Is output and the refresh operation is permitted. The time monitoring circuit 22 and the up / down counter 24 determine whether the average cycle of the past refresh operation is the first cycle t, that is, 16 μsec or more or less, and the refresh is repeated in the first cycle t or less. If so, the bus request having the lower priority is output to the bus arbitration circuit 8a, and when the average cycle is equal to or longer than the first cycle t, the bus request has the highest priority.

In addition, the time monitoring circuit 21 counts counters when the partial refresh operation has already been completed N times, that is, 256 times in this example, before the second period T, that is, 4096 μsec has elapsed. 23 shows the counter value 255 and invalidates the bus request REFREQ1, but then 4
This is for clearing the counter 23 when 096 μsec has elapsed, and for restarting the counting operation from 0. The counter 23 is cleared and the counter value is "0".
Then, the signal REFREQ1 becomes valid and the partial refresh operation of the random access memory is restarted from the beginning. Therefore, the partial refresh operation is executed only 256 times in the cycle of 4096 μsec.

FIG. 7 shows a refresh control method time chart of the second invention when the circuit of FIG. 6 is actually operated. The circuit of FIG. 6 operates, for example, at the timing shown in this figure. First, at the timing T1 in the initial state,
When the bus request DMAREQ of (b) and the bus request REFREQ1 of (d) become valid, the bus request DMAREQ of (b) has a high priority in this case.
CK becomes effective. As a result, timings T1 to T3
Up to (h), DMAACK becomes valid and the DMA acquires the bus right.

Next, at timing T3, it is assumed that the bus request CPUREQ of (a) becomes valid. In this case, (d)
The bus request REFREQ1 is valid, but since the bus request CPUREQ has a higher priority, the request confirmation signal CPUACK of (g) is valid. As a result, the timing T
The CPU acquires the bus right from 3 to timing T4. At the next timings T4 to T5, only the bus request REFREQ1 in (d) is valid. Therefore, the request confirmation signal REFACK of (i) becomes valid, and this timing T4
During the period from to T5, the refresh circuit acquires the bus right. During the next timings T6 to T7, the refresh circuit similarly acquires the bus right. Therefore, while another bus master is not requesting the bus right, partial refresh operations are sent back one after another. Further, if the timing T1 to the timing T8 in the initial state is set to 16 μsec, the DOWN signal of (f) is valid at the timing T8 until the timing T9. Similarly, timing T
When 16 μsec elapses between 8 and T10, the DOWN signal becomes valid here again from timing T10 to T11.

Next, at the timing T13, the number of times the DOWN signal of (f) becomes valid, that is, the number of times the request confirmation signal REFACK of (i) becomes valid, that is, two times is smaller than three times. Can be seen from the output of the up / down counter 24 shown in FIG. That is, the up-down counter 24 has the REFREQ of (c) at this timing T13.
Enable 2. At this time, (a) bus request CPU
Both REQ and bus request DMAREQ in (b) are valid, but REFREQ2 in (c) has the highest priority, so the request confirmation signal REFACK in (i) is issued at timing T14.
Will be effective. In this way, the refresh circuit occupies the bus from timing T14 to timing T15. Timing T1
After 5, since only the bus request CPUREQ in (a) is valid, the request confirmation signal CPUACK in (g) is valid, and the CPU acquires the bus right from timing T15 to T16.

By the way, it is assumed that the partial refresh operation N times, that is, 256 times has already been completed at the timing T18 in the figure. In this case, the bus request REFREQ1 output by the counter 23 shown in FIG. 6 becomes invalid, and the bus request from the refresh circuit is not output until timing T21 when the cycle of 4096 μsec ends. That is, since the entire refresh operation of the DRAM is completed within 4096 μsec, the refresh operation is suspended until 4096 μsec elapses. After that, timing T
At (21), R of (e) input to the counter 23 shown in FIG.
ESET signal becomes valid. At that time, the counter 23 sets the counter value to “0”, and at timing T21, the bus request REFREQ1 of (d) is validated again. After that, the same operation as the operation starting from the timing T1 is repeated. By the above operation, the refresh circuit allows a bus request once every 16 μsec as an average value, and
A partial refresh is always completed 256 times in μsec.

[Third Invention] Next, an embodiment of the third invention will be described. FIG. 8 shows a hardware block diagram for carrying out the method of the third invention. Here, the priority changing device 30 and the bus arbitration circuit 8a are shown. The configuration of the bus adjusting circuit 8a, its peripheral circuits, input / output signals, etc. are the same as those of the hardware of the first invention already described with reference to FIG.

In the third invention, the configuration of the priority changing device 30 is different from the previous inventions. The priority changing device 30 includes a time monitoring circuit 31, a time monitoring circuit 32,
And a counter 33. Time monitoring circuit 31
Is composed of a circuit which outputs a RESET signal once every second period T for completing the refresh operation of the entire DRAM, that is, every 4096 μsec. Further, the time monitoring circuit 32 uses a constant switching time S equal to or less than the second period T, for example, 3000 μ.
It consists of a circuit that enables the ENABLE signal once every sec. The counter 33 is a circuit for resetting the counter value to “0” in the initial state or when the clear terminal becomes valid, and incrementing the counter value by “1” when the up terminal becomes valid and counting up to 256 times. Is. Then, enable the REFREQ1 signal until the counter value reaches 255, and enable the ENABLE signal, this time the signal REFR
This circuit is used to enable EQ2.

As a result, the counter 33 outputs the bus request REFREQ1 to the input port Ia having the lowest priority of the bus arbitration circuit 8a and outputs the bus request REFREQ2 to the input port Id having the highest priority of the bus arbitration circuit 8a. At the same time, the request confirmation signal REFACK output from the bus arbitration circuit 8a is counted by the counter 33, and if 256 partial refresh operations are completed within 4096 μsec, then the RESET signal of the time monitoring circuit 31 becomes valid. Until the refresh operation is stopped. Also,
30 before completing a partial refresh operation 256 times
When 00 μsec has elapsed, EN output from the time monitoring circuit 32
The ABLE signal becomes valid, and the high-priority bus request REFREQ2 is input from the counter 33 to the bus arbitration circuit 8a. As a result, the remaining partial refresh operation is executed in preference to other bus masters, and 4096 μsec
During this period, the refresh operation is performed 256 times.

Therefore, the switching time S set by the time monitoring circuit 32 is set to 2 after that even if the partial refresh operation could not be executed even once until then.
It is set so that partial refresh operations for 56 times are possible. One partial refresh operation is 1 μse
Since it ends in c, refresh operation can be performed 256 times in about 500 μsec. Therefore, the switching time S of the time monitoring circuit 32 is set to 3000 μsec so as to leave about 1000 μsec with a certain margin.

A specific time chart of the refresh control method of the third invention is shown in FIG. First,
At the timing T1 in the initial state, the bus request REFREQ1 shown in (d) and the DMAREQ shown in (b) are valid. In this case, since the bus request DMAREQ shown in (b) has a high priority, the request confirmation signal DMAACK shown in (h) becomes valid. As a result, the DMA acquires the bus right for 1 μsec from the timing T1 to the timing T3.

Next, at timing T2, the bus request CPUREQ of (a) becomes valid. Therefore, at timing T3, the bus request REFREQ1 in (d) is valid,
Since the bus request CPUREQ in (a) has a higher priority, the request confirmation signal CPUACK in (g) becomes valid. Thus, the CPU acquires the bus right from timing T3 to timing T4. Next, after timing T4, only the bus request REFREQ1 in (d) is valid. Therefore,
The request confirmation signal REFACK of (i) becomes valid, and the refresh circuit acquires the bus right from timing T4 to timing T5. Similarly, the refresh circuit acquires the bus right from timing T6 to timing T7.

It is assumed that 3000 μsec has elapsed between timings T1 and T8. In this case, at timing T8, ENABLE of the time monitoring circuit 32 shown in FIG. 8 becomes effective. That is, FIG.
When the ENABLE of (f) shown in (1) is enabled, the RE shown in (d) of
FREQ1 becomes invalid, and instead REFREQ shown in (c)
2 is valid. Therefore, after that, the bus request of the refresh circuit is treated as the highest priority compared with other bus masters. Therefore, after that, the process is repeated until the timing T15 when the counter value N of the counter becomes 255, and the request confirmation signal REFACK shown in (i) becomes valid, and all refresh operations are completed. When the counter value reaches 256 times at the timing T15 and the last refresh operation is completed at the timing T16, the bus request RE shown in (c)
FREQ2 becomes invalid. After that, REFREQ2 shown in (c)
And the bus request REFREQ1 shown in (d) are both in an invalid state, and the bus request of the refresh circuit is not output until 4096 μsec has elapsed. Then, after timing T17 after 4096 μsec has passed from the initial state, the same operation as described above is executed again.

By the above operation, the bus request of the refresh circuit always has the lowest priority until at least 3000 μsec has passed from the initial state, so that the bus requests of other bus masters are not disturbed and the system performance is improved. To do. If all partial refreshes are not completed after 3000 μsec has elapsed, the refresh operation of the entire DRAM must be refreshed within 4096 μsec because the refresh operation is given the highest priority until it reaches 256 times. Can be completed.

The present invention is not limited to the above embodiments. The circuit of the above embodiment may be replaced with a logic circuit having the same function, a gate circuit, or another circuit block. Further, the priority switching is not necessarily a fixed priority circuit, but may be a circuit configured to rearrange priorities at a predetermined timing. In addition, the first cycle, the second cycle, the switching time, etc.
It can be freely selected and changed according to the characteristics of M.

[0055]

According to the refresh control method described above, in the first invention, first, a bus request of a lower priority level is output for a certain waiting time, and even if this waiting time elapses, the bus request is still output. When the request is not permitted, the bus request is switched to a higher priority level, so that it is possible to execute the bus request once within a fixed time without fail. Further, while the bus request is set to the low priority level, the operation of other bus masters is not hindered, so that the system performance can be improved.

According to the second aspect of the present invention, the past average cycle of the partial refresh operation is monitored, and when this cycle is equal to or longer than the preset first cycle t, the priority of the bus request becomes the highest. Therefore, as the average value, the first period t
The partial refresh operation can be repeated with.
Therefore, it is possible to complete the partial refresh operation N times within at least the second cycle T of t × N.

According to the third aspect of the invention, the bus request for partial refresh is repeatedly output at a low priority until the fixed switching time S, and after the switching time S, the priority is high. Since the bus request is output and the remaining partial refresh operation is performed, the operation of another bus master can be prioritized and system performance can be improved at least until the switching time S elapses. Further, since the priority of the bus request for partial refresh is increased after the switching time S has elapsed, it is possible to complete all necessary partial refresh operations within the second cycle T.

[Brief description of drawings]

FIG. 1 is a hardware block diagram for implementing the method of the first invention.

FIG. 2 is a block diagram of a general computer.

FIG. 3 is a conceptual diagram of a bus arbitration circuit.

FIG. 4 is a time chart of a conventional refresh control method.

FIG. 5 is a time chart of the refresh control method of the present invention.

FIG. 6 is a hardware block diagram for performing the method of the second invention.

FIG. 7 is a time chart of the refresh control method of the second invention.

FIG. 8 is a hardware block diagram for performing the method of the third invention.

FIG. 9 is a time chart of a refresh control method of the third invention.

[Explanation of symbols]

 8a Bus arbitration circuit 10 Priority changing device 11 Time monitoring circuit 12 NOT gates 13 and 14 AND gate 15 OR gate

Claims (3)

[Claims] 1. When a refresh circuit for executing a refresh operation of a dynamic random access memory makes a bus request to a system bus for the refresh operation, it has a lower priority than other bus masters at first. When a bus request of a level is output, time is counted from the time when the bus request is output, and the wait time that is allowable when the refresh operation is executed has elapsed, but the bus request is not accepted, the wait time elapses. Thereafter, the bus request is switched to a level having a higher priority than that of other bus masters and output, and the refresh control method. 2. When a refresh circuit for executing a refresh operation of a dynamic random access memory makes a bus request to a system bus for the refresh operation, a portion of the dynamic random access memory is not longer than a first cycle t. A refresh operation is performed, and the first
When it is assumed that the partial refresh operation is executed N times in a second cycle that is N times the cycle t of FIG. When the bus request of the lowest priority level is output by comparison, the partial refresh operation is repeatedly executed, and the past average cycle of the partial refresh operation is equal to or greater than the first cycle t. Outputs a bus request having the highest priority level as compared with other bus masters, completes N partial refresh operations before the second period T9 elapses, and then outputs the second refresh request. A refresh control method characterized in that the output of the bus request is stopped until a period T has elapsed. 3. A portion of the dynamic random access memory at a first cycle t or less when a refresh circuit for executing a refresh operation of the dynamic random access memory makes a bus request to a system bus for the refresh operation. A refresh operation is performed, and the first
When the partial refresh operation is executed N times in a second cycle that is N times the cycle t, and the entire refresh operation of the dynamic random access memory is finished, A certain switching time S is set, and until the switching time S elapses, the bus request of the lowest priority level is output as compared with other bus masters, and the partial refresh operation is repeatedly executed. Then, after the switching time S has elapsed, the bus request having the highest priority level is output as compared with other bus masters, and the remaining partial refresh operation is performed before the second period T elapses. A refresh control method comprising: