JPH064998A - Synchronizing signal detecting circuit - Google Patents

Abstract

PURPOSE:To successfully detect a synchronous clock independently of existing of a selector mark and to enable improving detecting accuracy even if drop out exists in a synchronizing waveform by providing a synchronization detecting circuit and a PLL circuit. CONSTITUTION:A recorded signal of a disk 1 is supplied to a synchronous signal detecting circuit 8 as encoded read data via an amplifier circuit 7. The synchronous signal detecting circuit 8 obtains a read gate signal based on preamble detected signal from a next stage PLL circuit 9, and supplies this read gate signal to the PLL circuit 9. The PLL circuit 9 detects the read gate signal from the synchronous signal detecting circuit 8, and obtains the preamble detected signal indicating detection of a synchronous signal when synchronous signals of the prescribed numbers are kept after opening of the gate, and supplies this signal to the synchronous signal detecting circuit 8. The PLL circuit 9 takes out the encoded read data by this, and supplies this data taken out to a binary/digital conversion circuit 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing signal detecting circuit suitable for application to a disc reproducing apparatus for reproducing an optical disc such as a write-once.

[0002]

2. Description of the Related Art Conventionally, in a disc reproducing apparatus for reproducing an optical disc such as a write-once, a recording signal recorded on the optical disc is read by an optical head,
After amplifying the read signal, synchronization detection, PLL
Etc., and performs binary / digital conversion, serial / parallel conversion, 1
Processing such as 0-8 conversion is performed, error correction processing is further performed by an ECC (error correction code) processor, and after this error correction processing, predetermined signal processing is performed and output.

There are various types of optical discs on which information can be written. For example, an optical disc (WORM) called a write-once is 5 inches (130 m).
m) WORM (ISO / IEC 9171), and a magneto-optical disk (MO) is 3.5 inches (90 mm) MO (ECMA-154).

In these optical discs, a sector mark indicating the start of the sector is prepared at the head of the sector, and a sync is prepared next to the sector mark. Therefore, the read gate signal for starting the PLL operation can be easily obtained.

[0005]

By the way, the above-mentioned sector mark is a so-called sector header portion, and it is better not to have it in terms of capacity.

Further, CRC (redundancy code check system) and ECC are not added to the sector mark, and if the mark is scratched or dirty, the sector cannot be used.

Further, even if the sector mark can be detected, if there is a dropout in the sync portion immediately after that, there is a possibility that the PLL operation becomes unstable and the sync clock cannot be detected.

In the case of a system having no sector mark, a so-called self-propelled PLL is used, but since the usable PLLIC is limited, the so-called free-running may occur due to variations in the values of external capacitors and resistors. There was the inconvenience that the frequency fluctuated and it was difficult to use.

The present invention has been made to solve such a problem. In a system having a sector mark, even if the sector mark cannot be used, the sync clock is detected and the sector is used. By starting the sector directly with sync, the sector mark becomes unnecessary, so even if the system does not have a sector mark, the sync clock can be detected satisfactorily and even if there is a dropout in the sync waveform. The present invention is intended to propose a synchronization signal detection circuit that can perform so-called retry to improve detection accuracy.

[0010]

The synchronizing signal detecting circuit of the present invention is, for example, as shown in FIGS. 1 to 4, detecting means 8 for detecting the frequency of the synchronizing signal, and detection based on the detection result from this detecting means 8. Continuity detecting means 9 for detecting frequency continuity
And the phase comparison is performed when the continuity detecting means 9 detects the continuity of the detection frequency of the predetermined detection frequency.

The synchronizing signal detecting circuit of the present invention is shown in FIG.
As shown in FIG. 4, it has a detecting means 8 for detecting the frequency of the synchronizing signal, and a continuity detecting means 9 for detecting the continuity of the detected frequency based on the detection result from the detecting means 8. The control operation for phase comparison is stopped when a predetermined number of synchronization signals are not detected after the continuity detecting means 9 detects the continuity of a predetermined detection frequency.

[0012]

According to the configuration of the present invention described above, the phase comparison is performed when the continuity detecting means 9 detects the continuity of the detection frequency of the predetermined detection frequency.

Further, according to the above-described configuration of the present invention, for the phase comparison when the predetermined number of synchronization signals are not detected after the continuity detecting means 9 detects the continuity of the predetermined detection frequency. Stop the control operation of.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the sync signal detecting circuit of the present invention will be described in detail below with reference to FIGS.

First, the case where the synchronizing signal detecting circuit of the present invention is applied to a disk reproducing apparatus will be described with reference to FIG.

In FIG. 2, reference numeral 1 denotes a disk, which is, for example, a 5 inch (130 mm) write once (W).
ORM: ISO / IEC 9171), 12 inches (3
00mm) write-once, 3.5 inch (90mm)
Optical disk (MO: ECMA-154) or an optical disk such as CDR.

Data recording will be described below.
At the time of recording data, for example, 8-bit data is subjected to 8-10 conversion (8 bits to 10 bits), converted into serial digital data, and then RZ (Return).
to Zero) recording or NRZ (Non Ret)
urn to Zero) Recording. That is, the data is recorded on the disc by emitting light in the RZ or NRZ method corresponding to the data "1" and "0".

As for conversion (modulation), in addition to 8-10 conversion, conversion from 8 bits to 16 bits (2, 7)
Conversion (there is a condition that 2 or more and 7 or less 0s always exist between 1 and 1), conversion from 8 bits to 12 bits (1, 7) conversion (always 0 between 1 and 1) Has the condition that 1 or more and 7 or less are included).

Now, the format of the data recorded in this way will be described with reference to FIG.
3B, the address area is composed of an address area and a data area. As shown in FIG. 3B, the address area is a sync called VFO (Variable Frequency Oscillator), an address mark indicating the start of an address, and address data ( Here, "00"), data, address mark, address data (here "01"), data, address mark, address data (here "10"),
Composed of gaps.

The data area is, as shown in FIG. 3C,
A sync called VFO (Variable Frequency Oscillator), a data mark indicating the beginning of data,
Data, data mark, data, ... Data mark, data, buffer.

Disc 1 in this disc reproducing apparatus
When the disc 1 is mounted on the mounting portion of the disc reproducing device (not shown) and the operating portion (not shown) is operated,
The signal processing circuit 16 supplies a control signal to the drive unit 4, the drive unit 4 drives the spindle motor 3, and the disk 1 mounted on the shaft 2 is rotated.

Reference numeral 2 is an optical pickup, which is a signal processing circuit 1.
The drive operation of the drive unit 6 based on the control signal from 6 causes the drive unit 6 to move on the reading surface of the disk 1 to read the recording signal of the disk 1.

The read recording signal of the disc 1 is amplified by the amplifying circuit 7, encoded and converted into binary binary information, and supplied to the synchronizing signal detecting circuit 8 as encoded read data.

As will be described later, the sync signal detection circuit 8 is a circuit for detecting the sync of the encoded read data. The circuit 8 outputs the read gate signal based on the preamble detected signal from the PLL circuit 9 in the next stage. Get
This read gate signal is supplied to the PLL circuit 9.

This PLL circuit 9 detects the read gate signal from the sync signal detection circuit 8 and obtains a preamble detected signal indicating that the sync has been detected when a predetermined number of syncs have continued after the gate was opened. The preamble detected signal is supplied to the sync signal detection circuit 8 as described above.

The PLL circuit 9 extracts the data of the encoded read data, and supplies the extracted data to the binary / digital conversion circuit 11.

The binary / digital conversion circuit 11 converts the binary data extracted by the PLL circuit 9 into serial digital data, and supplies this serial digital data to the serial / parallel conversion circuit 12.

The serial / parallel conversion circuit 12 converts the serial digital data from the binary / digital conversion circuit 11 into parallel digital data, and supplies this parallel digital data to the 10-8 conversion circuit 13.

The 10-8 conversion circuit 13 is for returning to the original because it is 8-10 converted at the time of recording. The original data (original data and ECC (error correction code)) converted to 8 bits by 10-8 conversion is once written in the memory 14 and subjected to error correction processing and the like by the ECC processor.

The data which has been subjected to this error correction processing is supplied to a device using data such as a computer through an output terminal 17 after passing through a signal processing circuit 16.

FIG. 1 is a block diagram showing a main part of the above-mentioned disc reproducing apparatus. FIG. 1 shows an internal constitution of a sync signal detecting circuit 8 and a PLL circuit 9 of the disc reproducing apparatus shown in FIG. .

In FIG. 1, reference numeral 20 is an input terminal to which the encoded read data from the amplifier circuit 7 shown in FIG. 2 is supplied, and the encoded read data (FIG. 4A) from the amplifier circuit 7 is supplied via this input terminal 20. Is supplied to the input terminal A of the monostable multivibrator 21.

This monostable multivibrator 2
1 (hereinafter referred to as mono-multi) is retriggerable, and the time constant determined by the capacitor 22 and the resistor 23 is set to be slightly longer than the cycle T of the sync clock of the encoded read data.

Therefore, the signal output from the output terminal Q of the mono-multi 21 continuously becomes a high level "1" signal (see FIG. 4B). This signal is supplied to the enable terminal EN and the load terminal LD of the counter 24, respectively.

A dip switch 25 is connected to the input terminals D1 to D4 of the counter 24 so that the counter 24 is in a count enable state, that is, signals supplied from the monomulti 21 to the enable terminal EN and the load terminal LD are at high level. When it becomes “1”, the value set by the DIP switch 25 is the input terminals D1 to D of the counter 24.
4 and thereafter, the counter 24 starts counting the clock signal supplied from the input terminal 26 from the loaded value.

When the counter 24 counts up to a certain count value (when a certain time elapses), it outputs a carry signal. This carry signal is supplied to the clock input terminal CK of the D-type flip-flop circuit 27.

The flip-flop circuit 27 uses the carry signal from the counter 24 as a clock and pulls up the data input terminal D to the high level "1". Therefore, when the carry signal is supplied, the data output terminal is output. Outputs a read gate signal (see FIG. 4C).

This read gate signal is supplied to the read gate input terminal RG of the PLL circuit 9. The PLL circuit 9 starts its operation when the read gate signal is supplied (when the gate of the read gate signal is opened, that is, at the high level “1”).

The PLL circuit 9 internally counts the number of sync pulses after the operation is started, and when it reaches a predetermined count value (when a predetermined number of sync pulses continue).
Obtain the preamble detected signal (see FIG. 4D),
The AND circuit 33 outputs this preamble detected signal.
Supply to.

On the other hand, to the load signal input terminal LD and the count enable terminal EN of the counter 30, the read gate signal from the flip-flop circuit 27 is supplied as the load signal and the count enable signal, and at the same time, the clock signal input terminal CK. Is supplied with the clock signal from the input terminal 32.

A dip switch 31 is connected to the input terminals D1 to D4 of the counter 30, and the counter 30 is in the count enable state, that is, signals supplied from the flip-flop circuit 27 to the enable terminal EN and the load terminal LD, respectively. When the high level becomes "1", the value set by the DIP switch 31 is loaded into each of the input terminals D1 to D4 of the counter 30, and thereafter the counter 30 is supplied from the loaded value through the input terminal 32. Start counting clock signals.

When the counter 30 reaches a predetermined count value, it outputs a carry signal like the counter 24 described above. This carry signal is supplied to the NAND circuit 33, is ANDed with the preamble detected signal from the PLL circuit 9, and is then inverted. The signal output from the NAND circuit 33 is the flip-flop circuit 27.
Is supplied to the clear terminal CLR to reset the flip-flop circuit 27.

As shown in FIG. 4, in the NAND circuit 33, the preamble detected signal (see FIG. 4D) from the PLL circuit 9 and the read gate signal reach a high level "1" and reach a predetermined count value. The carry signal of the counter 30 that is output is logically ANDed and inverted and supplied to the clear terminal CLR of the flip-flop circuit 27.
When the preamble detected signal is at the high level "0" when the count signal reaches the predetermined count value and the carry signal is output, the NAND circuit 33 outputs the high level "1".
Clear signal is output, and the flip-flop circuit 27
Is not cleared, and the read gate signal remains at the high level "1" in the flip-flop circuit 27.

As described above, the synchronizing signal detecting circuit shown in FIG. 1 (including the synchronizing signal detecting circuit 8 and the PLL circuit 9)
Indicates that the read gate signal is temporarily turned on because the sync pulse is continuous within the period set by the DIP switch 25, and the read gate is confirmed by the return of the preamble detected signal within the period set by the DIP switch 31. is there.

Next, the operation when the ideal encoded read data cannot be obtained due to scratches or stains will be described.

For example, when a pseudo signal is generated in the encoded lid data due to noise or the like, the mono-multi 21 operates, so that the output of the mono-multi 21 becomes a high level "1".

At the same time, the counter 24 starts counting. However, in general, in the case of noise,
Since the ones having time intervals longer than the regular sync length T are also mixed, the continuous operation of the re-trigger of the mono-multi 21 is interrupted. The output becomes low level "0", and the initial value is loaded again. Therefore, the carry signal is not output from the counter 24, as a result, the flip-flop circuit 27 is not set, and the read gate signal is not output from the flip-flop circuit 27.

On the other hand, even when the leading portion of the sync clock has a signal loss due to scratches, dirt, etc., the circuit operation is the same as that described above, and the read gate signal is at the high level "1" until the sync clock is normally reproduced. "It doesn't work.

When the preamble detected signal is not generated after the head portion of the sync clock is normally reproduced, that is, even though the read gate signal becomes high level "1", the PLL circuit 9 thereafter. When the sync clock does not come out normally by the set number (when there is a scratch or dirt slightly behind the beginning of the sync clock), the output of the NAND circuit 33 outputs the output of the flip-flop circuit 27 as described above. Since it is cleared, the read gate signal becomes inactive "0".

However, if the sync clock continues normally thereafter, the circuit automatically starts repeating the circuit operation from the beginning. That is, since the retry operation is performed, the read gate signal is determined to be active "1" at the stage when the necessary repetition of the sync clock is detected.

Clocks (input terminals 26 and 3) used for the counters 24 and 30 of the sync signal detection circuit shown in FIG.
The clocks respectively supplied to 2) are clocks with high precision generated by an oscillator or the like (not shown) so as to improve the overall operation precision of the circuit. The clock signals may be the same, but the lengths of time required for the counters 24 and 30 are generally quite different and the counter 30 is longer in time. May be obtained by dividing the clock supplied to the counter 24.

The counters 24 and 30 may have a multi-stage structure or may be up-down counters. Also,
For example, the read gate signal may be generated from the sync clock without using the counter 30 and the clear signal generation circuit including the NAND circuit.

As described above, in this example, the read gate signal is temporarily turned on because the sync pulse is continuous within the period set by the dip switch 25, and the preamble detected signal is generated within the period set by the dip switch 31. Since the read gate is determined by returning it, in a system with a sector mark, even if the sector mark cannot be used, the sync clock can be detected and that sector can be used. By starting with the direct sync, the sector mark becomes unnecessary, so that the sync clock can be detected well even in a system without a sector mark, and even if there is a dropout in the sync waveform, so-called retry is performed to perform detection accuracy. Can be increased.

The above embodiment is an example of the present invention.
It goes without saying that various other configurations can be adopted without departing from the scope of the present invention.

[0055]

According to the present invention described above, the phase comparison is performed when the continuity of the detection frequency of the predetermined detection frequency is detected by the continuity detecting means. Therefore, in a system having a sector mark. Can detect the sync clock and use the sector even if the sector mark is disabled. By starting the sector directly with sync, the sector mark becomes unnecessary and there is no sector mark. Even the system can satisfactorily detect the sync clock, and even if there is dropout in the sync waveform, so-called retry can be performed to improve the detection accuracy.

Further, according to the present invention described above, the control operation for phase comparison is performed when the predetermined number of synchronization signals are not detected after the continuity detecting means detects the continuity of the predetermined detection frequency. So I decided to stop
In a system with a sector mark, even if the sector mark cannot be used, the sync clock can be detected and the sector can be used, and the sector mark is not required by directly starting the sector with the sync. As a result, the sync clock can be satisfactorily detected even in a system having no sector mark, and even if the sync waveform has a dropout, so-called retry can be performed to improve the detection accuracy.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a sync signal detection circuit of the present invention.

FIG. 2 is a block diagram showing an example of a disc reproducing apparatus to which the sync signal detecting circuit of the present invention is applied.

FIG. 3 is an explanatory diagram for explaining an embodiment of a synchronization signal detection circuit of the present invention.

FIG. 4 is a timing chart provided for explaining one embodiment of the synchronization signal detection circuit of the present invention.

[Explanation of symbols]

 8 Sync signal detection circuit 9 PLL circuit

Claims (3)

[Claims] 1. A detection means for detecting the frequency of a synchronizing signal, and a continuity detection means for detecting the continuity of the detected frequency based on the detection result from this detection means. The synchronous signal detection circuit is characterized in that the phase comparison is performed when the continuity of the detection frequency of is detected. 2. A retriggered monostable oscillator,
2. The sync signal detecting circuit according to claim 1, further comprising the continuity detecting means for detecting continuity when a sync signal having a frequency equal to or higher than a predetermined frequency arrives. 3. A detection means for detecting the frequency of the synchronization signal, and a continuity detection means for detecting the continuity of the detection frequency based on the detection result from the detection means. A synchronization signal detection circuit, wherein a control operation for phase comparison is stopped when a predetermined number of synchronization signals are not detected after detecting continuity of a predetermined detection frequency by.