JPH0648794B2 - Diversity receiver - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an diversity receiver that receives radio waves with a plurality of antennas and connects the antennas having the highest reception levels to a receiver.

[Prior art]

Conventionally, there is a diversity receiver disclosed in Japanese Patent Laid-Open No. 58-12439. This is for receiving television sequence broadcasting, and is configured as follows. Three
The signals respectively received by the antennas of the book are input to the television receiver in a time division manner after the vertical synchronizing signal by the high frequency switch. From this receiver, the signal level corresponding to each antenna is detected by the level detection circuit, each detection level signal is sampled and held by the sample and hold circuit, and the level comparison circuit compares the hold voltage of each sample and hold circuit. The state in which the antenna corresponding to the large hold voltage is connected to the receiver is held until the next comparison.

[Problems to be solved by the invention]

However, in such a diversity receiver, since the signals from the respective antennas are supplied to the receiver in a time division manner, the same number of sample hold circuits and comparison circuits as the antennas are required, which makes the circuit configuration complicated. There was a problem.

[Means for solving problems]

A first invention for solving the above problems is to provide three or more antennas, one receiver, and one of the antennas, which is interposed between the receiver and the antennas. Antenna switching means for switching the antennas connected to each other, means for generating an antenna switching timing signal each time a predetermined time elapses, and digits corresponding to the three or more antennas, and one of the digits corresponds. The other digit corresponds to the connection instruction state for instructing the connection of the antenna to the receiver.The digit becomes the non-connection instruction state for instructing the non-connection of the antenna to the receiver, and the digit in the connection instruction state is the antenna switching. First antenna switching signal generating means for generating a first antenna switching signal that moves by one digit each time a timing signal is generated, and a level detecting means for detecting the reception level of the receiver. A level holding means for holding the output of the level detecting means when the antenna switching timing signal is not generated, and an output when the output of the level detecting means is larger than the output of the level holding means when the antenna switching timing signal is generated. And a second antenna switching signal holding means for holding the first antenna switching occurring at that time as a second antenna switching signal in response to the output of the comparing means. Means for supplying the first antenna switching signal to the antenna switching means when the switching timing signal is generated, and supplying a second antenna switching signal to the antenna switching means when the antenna switching timing signal is not generated. .

A second aspect of the present invention is an antenna for interposing between three or more antennas, one receiver, and the receiver and each antenna, and switching the antenna connected to the receiver among the antennas. A switching means, a means for generating an antenna switching timing signal every time a predetermined time elapses, and a connection of an antenna having digits corresponding to each of the three or more antennas, one of which corresponds to the receiver. Is connected to the receiver and the other digit is a non-connection state that indicates the connected state of the antenna to the receiver, and the digit in the non-connection state is adjacent to each other when the antenna switching timing signal is generated. When the antenna switching signal that moves to the digit is generated and the digit that is in the connection instructing state when the direction inversion signal is generated is returned by one in the direction opposite to the movement direction so far, the digit that is in the connection instructing state after that The antenna switching signal generating means for moving to the above, the level detecting means for detecting the reception level of the reception, the level holding means for holding the output of the level detecting means when the antenna switching timing signal is not generated, the antenna switching Comparing means for generating the direction inversion signal each time the output of the level detecting means becomes smaller than the output of the level holding means when the timing signal is generated.

[Operation] According to the first aspect of the invention, when the antenna switching timing signal is not generated, the antenna corresponding to the digit in the connection instruction state of the second antenna switching signal is connected to the receiver, and the antenna is connected. The reception level at is held in the level holding means. Then, when the antenna switching timing signal is generated, the antenna corresponding to the digit of the connection instruction state in the first antenna switching signal is connected to the receiver, and the reception level at that antenna is compared with the reception level of the level holding means. It If this reception level is higher than the reception level held in the level holding means, then the first antenna switching signal becomes the second antenna switching signal as the second antenna switching signal.
Held by the antenna switching signal holding means. Further, when the reception level is lower than the reception level held in the holding means, the second antenna switching signal held at that time is held as it is. Then, until the next antenna switching signal is generated, the second antenna switching signal held in the second antenna switching signal holding means is supplied to the antenna switching means, and the level holding means is supplied to the level holding means as described above. The reception level at that time is retained. Therefore, what is held in the second antenna switching signal holding means is an antenna switching signal for connecting the antenna, which always has the maximum reception level, to the receiver.

According to the second invention, when the antenna switching timing signal is not generated, the antenna corresponding to the digit in the connection instruction state in the antenna switching signal is connected to the receiver,
The reception level at the antenna is held by the level holding means. When the antenna switching timing signal is generated, the digit in the antenna switching signal that is in the connection instruction state moves by one, the antenna corresponding to the moved digit is connected to the receiver, and the reception level at the antenna changes to the level. It is compared with the reception level of the holding means. If this reception level is higher than the reception level held in the level holding means, that state is maintained and the reception level at the antenna at that time is held in the level holding means until the next antenna switching timing signal is generated. To be done. Similarly, each time a switching timing signal is generated, if the reception level at the newly connected antenna is higher than the reception level at the antenna connected when the previous antenna switching timing signal was generated, that reception level Switch to a larger antenna. When the output of the level detecting means becomes smaller than the output of the level holding means during the switching in this way, that is, the reception level of the antenna connected at the previous antenna switching timing is higher than that of the antenna connected this time. When it becomes larger than the reception level, the direction inversion signal from the comparison means is generated, and the antenna switching signal generation means returns the digit in the connection instruction state to the previous digit and connects the antenna having the large reception level to the receiver. At this time, the level holding means holds the reception level at that time. Then, when the antenna switching timing signal is generated next time,
The antenna switching signal generating means generates the antenna switching signal by reversing the moving direction so that the reception antenna of the second time before is connected to the receiver. If the reception level at this time is smaller than the reception level held in the level holding means, the previous reception antenna is switched in the same manner as described above.

〔Example〕

The first embodiment has four antennas 2, 4, 6, 8 as shown in FIG. These antennas 2, 4, 6,
Reference numerals 8 have different directivities, and are attached to an automobile on which the television receiver 10 is mounted.

An antenna switching unit 12 connects one of the antennas 2, 4, 6, 8 selected by the switching signal to the input terminal of the television receiver 10. In the switching signal, each bit has four digits corresponding to the antennas 2, 4, 6, and 8, for example, 4 digits.
It consists of bits, and only one bit of each bit is "1".
The signal synthesizing unit 16 in the control unit 14 supplies the antenna switching unit 12 so that the antenna corresponding to the bit "1" is connected to the television receiver 10. That is, the bit that is "1" is the connection instruction state, and the bit that is "0" is the non-connection instruction state.

Reference numeral 17 denotes an audio signal level detection unit that detects the level of the audio signal extracted from the television receiver 10. The level detection signal of the audio signal level detection unit 17 is the signal switching unit 18
It is supplied to one input of the comparison unit 20 or the level holding unit 22 via. The output of the level holding unit 22 is supplied to the other input of the comparison unit 20. The signal switching section 18 is interposed between the audio signal level detecting section 16 and one input of the comparing section 20 and between the analog switch 24 and the audio signal level detecting section 17 and the level holding section 22. The analog switch 26 and the analog switch 24 are closed when the gate signal supplied from the timing control circuit 28 in the control unit 14 becomes “1”, and the analog switch 26 outputs the gate signal to the inverter 30. It is configured to be closed when the inverted inverting gate signal becomes "1".

As shown in FIG. 2, the timing control circuit 28 responds to the falling edge of the vertical synchronizing signal (see FIG. 9 (a)) extracted from the television receiver 10 to set the output to "1" for a predetermined time. The output signal of the circuit 32 (see FIG. 9 (b)) is generated as a gate signal.

The comparison unit 20 sets the output to "1" when the level detection signal of the audio level detection unit 17 supplied via the analog switch 24 is larger than the output of the level holding unit 22. The output of the comparison unit 20 is supplied to the control unit 14.

The control unit 14 also has a serial-parallel shift register 32. The series-parallel shift register 32 is composed of digits corresponding to the antennas 2, 4, 6, and 8, that is, 4 bits,
It functions as a parallel register when the serial / parallel switching signal is supplied from the reset and initialization circuit 34, and functions as a serial shift register when the serial / parallel switching signal is not supplied. Further, the input side IN and the output side OUT of the series-parallel shift register 32 are directly connected, and when functioning as a serial shift register, they operate as a ring counter. The shift signal to the serial-parallel shift register 32 is supplied from the reset and initialization circuit 34 via the OR gate 36 at the beginning of power supply, and thereafter supplied from the timing control circuit 28 via the OR gate 36. The timing control circuit 28 basically generates a shift signal by using the one-shot circuit 39 which outputs "1" for a predetermined time in response to the fall of the output of the one-shot circuit 31 (see FIG. 9 (c)). ).
Therefore, when the serial-parallel shift register 32 functions as a serial shift register, the series-parallel shift register 32 shifts each time the vertical synchronizing signal falls.

Each bit output of the serial-parallel shift register 32 is connected to each of the NAND gates 38a to 38d which form the comparison antenna setting gate unit 38.
Is supplied to one input. Also each NAND gate 38
Gate signals are supplied to the other inputs of a to 38d, respectively.

The comparison antenna setting gate unit 38 is a NAND gate 38.
Because it is composed of a to 38d, when the gate signal is "1", it outputs the inverted output of the serial-parallel shift register 32, and when the gate signal is "0", the output of serial-parallel shift "1111" is output regardless of.

Each bit output of the serial / parallel shift register 32 is also supplied to the parallel shift register 40 composed of 4 bits. As the shift signal to the parallel shift register 40, a signal obtained by waveform-shaping the output signal of the comparison unit 20 by the waveform shaping unit 42 is used. Therefore, the parallel shift register 40 is
When the comparison unit 20 sets the output signal to "1", each output of the serial-parallel shift register 32 at that time is taken in, and when the comparison unit 20 sets the output signal to "0", each bit output at that time is maintained. To do.

Each bit output of the parallel shift register 40 is supplied to one input of each of the NAND gates 44a to 44d forming the reception antenna setting gate unit 44. Also each NAND gate 44a
Inverted gate signals are supplied to the other inputs of the to 44d. Since the receiving antenna setting gate unit 44 is also composed of the NAND gates 44a to 44d, when the inversion gate signal is "1", an inverted bit output of the parallel shift register 40 is output, and the inversion gate signal is "0"
At this time, "1111" is output regardless of each bit output of the parallel shift register 40.

The outputs of the NAND gates 38a to 38d are supplied to one input of each of the NAND gates 16a to 16d forming the signal combining unit 16. The output of each NAND gate 44a to 44d is
It is supplied to the other input of each NAND gate 16a to 16d. Therefore, the signal synthesizing unit 16 outputs each output of the serial-parallel shift register 32 when the gate signal is "1", and when the inverted gate signal is "1", that is, when the gate signal is "0", the parallel signals are output in parallel. Each output of the shift register 40 is output.

The diversity receiver configured as above operates as follows. Now, when the power is turned on, the series-parallel shift register 32 and the parallel shift register 40 are reset by the reset signal from the reset and initialization circuit 34 shown in FIG. Then, as shown in FIG. 8B, the serial-parallel shift register 32 operates as a parallel shift register by the serial-parallel signal generated from the reset / initialization circuit 34 following the reset signal, and the reset / initialization circuit 34 is operated. As shown in FIG. 8 (c), the serial-parallel shift register 32 is operated by the shift signal generated during the serial-parallel signal generation.
However, the initial setting value “1” from the reset and initial setting circuit 34
000 ”is captured. The captured “1000” is input to one input of each of the NAND gates 38a to 38d of the comparison antenna setting gate unit 38. Since the serial / parallel switching signal is not supplied to the serial / parallel shift register 32 thereafter, the serial / parallel shift register 32 functions as a serial shift register.

In this state, the gate signal is "0" and is supplied to the other input of each of the NAND gates 38a to 38d. Therefore, as shown in FIG.
The output of through 38d is "1111", and the NAND gate 44a
Since "0000" is supplied from the parallel shift register 40 to one of the inputs through 44d and the inverted gate signal of "1" is supplied to the other input as shown in FIG. 9 (c), The output of the NAND gates 44a to 44d is "1111".
Becomes Since the outputs of the NAND gates 44a to 44d of "1111" and the outputs of the NAND gates 38a to 38d of "1111" are supplied to the NAND gates 16a to 16d, the outputs of the NAND gates 16a to 16d are shown in FIG. 9 (i). Is "0000", and both antennas are TV receivers.
Not connected to 10.

In this state, the timing control circuit 28 responds to the fall of the vertical synchronizing signal to set the gate signal to "1" as shown in FIG. 9 (b) and the inverted gate signal as shown in FIG. 9 (c). Is set to "0". At this time, as shown in FIG. 9 (f), the outputs of the NAND gates 38a to 38d become "0111" which is the output "1000" of the serial-parallel shift register 32 inverted, while the NAND gates 44a to 44d output the inverted gate signals. Since it is “0”, as shown in FIG.
1 ". Therefore, the outputs of the NAND gates 16a to 16d are, as shown in FIG.
The output is "1000", and the antenna 2 is connected to the television receiver 10 via the antenna switching unit 12.

The audio signal level of the television receiver 10 to which the antenna 2 is connected is detected by the audio signal level detection unit 17, and "1" is displayed.
Is supplied to the comparison section 20 through the closed analog switch 24 as shown in FIG. 9 (j). The comparison unit 20 compares this with the output of the level holding unit 22, but since the level holding unit 22 initially holds nothing, the output of the comparison unit 20 is as shown in FIG. 9 (l). "1"
Becomes This output “1” is supplied to the parallel shift register 40 via the waveform shaping section 42, and the parallel shift register 40
Takes in each bit output "1000" of the serial-parallel shift register 32 as shown in FIG. 9 (g).

Eventually, the gate signal falls to "0", and in response to this, the timing control circuit 28 generates a shift signal as shown in FIG. 9 (d). As a result, the serial-parallel shift register 32 shifts in series, and as shown in FIG.
100 ". At this time, since the gate signal is "0" and the inverted gate signal is "1", the outputs of the NAND gates 38a to 38d are "1111" and the NAND gates 44a to 44d.
"d" is the inverted output of the parallel shift register 40.
1 ". Therefore, the outputs of the NAND gates 16a to 16d output the output "1000" of the parallel shift register 40, and the antenna 2 is kept connected to the television receiver 10.

On the other hand, the gate signal is "0" and the inverted gate signal is "1".
As shown in FIGS. 9 (j) and 9 (k), the analog switch 24 is opened and the analog switch 26 is released.
Closes. As a result, the level detection output of the audio level detection unit 10 that detects the audio level of the television receiver 10 to which the antenna 2 is connected is supplied to the level holding unit 22 and held therein.

Next, when the vertical synchronizing signal falls, the gate signal becomes "1", and the inverted gate signal becomes "0", the signal synthesizing unit 16 outputs "010" of the serial-parallel shift register 32 in the same manner as described above.
"0" is output and the antenna 4 is connected to the television receiver 10. The audio level detection unit 17 detects the audio level of the television receiver 10 to which the antenna 4 is connected. If this level detection signal is higher than the voice level when the antenna 2 held in the level holding unit 22 is connected, the parallel shift register 40 is the same as the above-mentioned one.
Take in 32 outputs "0100". Therefore, when the inverted gate signal becomes "1", the output of the signal synthesizing unit 16 becomes "0100", and the antenna 4 is kept connected to the television receiver 10. Further, if the level detection signal is lower than the sound level held in the level holding unit 22, the comparison unit 20
Output is maintained at "0", parallel shift register is "1000"
Maintain the state of. Therefore, when the inverted gate signal becomes "1", the output of the signal combining unit 16 becomes "1000", and the antennas connected to the television receiver 10 are the antennas 4 to 2
Is switched to.

Thereafter, the same operation is performed. For example, four antennas 2, 4,
Assuming that the reception level of the antenna 4 is the highest among the signals 6 and 8, when the antenna 2 is switched to the antenna 4 as described above, the connection state of the antenna 4 is maintained, and then the vertical synchronization signal falls, The antenna is switched to the antenna 6 at once, but returns to the antenna 4 again. Next, when the vertical synchronizing signal falls, the antenna is switched to the same 8 but returns to the antenna 4 again. When the antenna 8 is connected to the receiver 10 at the falling edge of the vertical synchronizing signal, the antenna 2 is connected to the television receiver 10 at the next falling edge of the vertical synchronizing signal.

In this way, the optimum antenna is selected while switching from antenna 2 to antenna 4. The car moves during this time, but since there is time within a few pulses of the vertical sync pulse, its distance is negligible, so the reception level does not fluctuate and has little effect on choosing the optimal antenna.

Reference numeral 46 denotes a coincidence detection circuit, which outputs a signal "1" when the outputs of the parallel shift register 40 and the serial-parallel shift register 32 coincide with each other.
And gate 48 of the. The coincidence of the outputs of both shift registers 32, 40 means that the antenna currently selected as the optimum and this antenna and the antenna with which the next vertical synchronization signal falls are compared. ing. In such a case, it is a waste of time to make a comparison. Therefore, the serial / parallel shift register 32 is controlled by the clock signal of the timing control circuit.
When the outputs of both shift registers 32 and 40 coincide with each other as a result of shifting, the shift signal is supplied one more time in succession to shift another serial-parallel shift register 32. For this reason, the output of the coincidence detection circuit 46 is supplied to the AND gate 48 as shown in FIG. 2. The AND gate 48 inverts the output of the one-shot circuit 39 by the inverter 50 and outputs it by the delay circuit 52. What is delayed by the amount is supplied. The output of the AND gate 48 is delayed by the delay circuit 54 and then supplied to the OR gate 56 to which the output of the one-shot circuit 39 is also supplied.

When the output of the one-shot circuit 39 becomes "1" and the output of the serial-parallel shift register 32 shifts, and the outputs of both registers 32 and 40 match, the output of the one-shot circuit 39 becomes synchronized with that of "1". Then, the output of the coincidence detection circuit 46 becomes "1" (see FIG. 3 (e)) and is supplied to the AND gate 48. The AND gate 48 is also supplied with the output of the one-shot circuit 39 inverted and delayed (see FIG. 3 (d)). Therefore, the AND gate generates two pulses (Fig. 3).
(See (f)). The first one of these pulses occurs while the output of the one-shot circuit 38 is "1", while the latter one occurs after the output of the one-shot circuit 39 becomes "0". OR gate with further delay of these pulses
Or gate 56 because it is supplied to 56 (see FIG. 3 (g)).
Causes the output of the one-shot circuit 39 to change from "1" to "0" and then to "1" again with some delay (see FIG. 3 (h)), and further shifts the serial-parallel shift register 32.

An error detection circuit 58 supplies an H level output to the reset and initialization circuit 34 when two or more "1"'s are included in the outputs of the serial-parallel shift register 32, and both registers 32 are supplied. , 40 to return to the initial state. This is to prevent that if there is more than one "1" in each output of the serial-parallel shift register 32 for some reason, two or more antennas will be connected to the receiver 10 at the same time. is there.

A second embodiment is shown in FIGS. 4 to 6. In this embodiment, the number of antennas is three, that is, the antennas 2, 4, and 6, and the same parts as those in the first embodiment are designated by the same reference numerals and their description is omitted. It should be noted that, contrary to the first embodiment, the comparison unit 20 generates the output "1" when the level detection output of the audio signal level detection unit 17 is smaller than the holding output of the level holding unit 22.

In addition to the comparison unit 20, the control unit 58 of this embodiment has a timing control circuit 60, a parallel shift register 62, a decoder 64 and a T-type flip-flop 66.

The timing control circuit 60 includes a gate signal supplied to the analog switch 24 and the inverter 30, and a parallel shift register.
And a shift signal to be supplied to 62. As shown in FIG. 5, the timing control circuit 60 controls the vertical sync signal (see FIG. 6 (a)).
Output) "1" for a predetermined time t1 in response to the falling edge of
(See FIG. 6 (b)) has a one-shot circuit 68,
This output is used as a gate signal. Besides this,
In response to the falling edge of the vertical synchronizing signal, a predetermined time t2 (t2>
The output is set to "1" only for t1) (see FIG. 6 (c)) and the one-shot circuit 70 and the inverter 72 for inverting the output thereof.
And when the output of the comparison unit 20 rises from "0" to "1" (6th
(See FIG. 3D), and in response to this, the predetermined time t3 (t3> t
2) A one-shot circuit 74 that outputs only "1", an AND gate 76 to which the output of the one-shot circuit 74 (see FIG. 6 (e)) and the output of the inverter 72 are input, and the AND gate 76 and the one-shot It has an OR gate 78 to which the output of the circuit 68 is input. The output of this OR gate 78 is used as a shift signal. Therefore, when the output of the comparison unit 20 is "0", the shift signal only becomes "1" in synchronization with the gate signal as shown in the first half of FIG.
When the output of is "1", as shown in the latter half of Fig. 6, it becomes "1" in synchronization with the gate signal and then becomes "1" again (Fig. 6).
(See (f)).

When the shift signal from the timing control circuit 60 becomes "1", the parallel shift register 62 takes in the outputs D' ₁ , D' ₂ , D' ₃ of the decoder 64 at that time. Then, each output of the parallel shift register 62 is supplied to the antenna switching unit 12 and is also supplied to the inputs D ₁ , D ₂ and D ₃ of the decoder 64.

The Q output of the T-type flip-flop 66 is supplied to the decoder 64 as D _{0 in} addition to D ₁ , D ₂ and D ₃ . The T-type flip-flop 66 inverts the Q output every time the output of the comparison section 20 becomes "1".

The decoder 64 has 12 NAND gates as shown in FIG.
69a to 69l, four AND gates 71a to 71d, one inverter 73, one OR gate 75 and one NOR gate
75, and the values shown in the table below are D ₀ , D ₁ , D ₂ ,
When D ₃ is taken, the values shown in the table below are taken as D ′ ₁ , D ′ ₂ and D ′ ₃ .

It should be noted that X represents either "1" or "0". D' ₁ is for antenna 2 and D' ₂ is for antenna 4
, D' ₃ is a digit corresponding to each antenna 6,
The antenna 2 is connected to the receiver 10 when the D ′ ₁ is “1”, the antenna 4 is connected to the D ′ ₂ when the D ′ ₂ is “1”, and the antenna 6 is connected to the receiver 10 when the D ′ ₃ is “1”. The switching unit 12 operates.

There is always only one "1" in D' ₁ , D' ₂ and D' ₃ .

Next, the operation of this embodiment will be described. Now the parallel shift register 62 has been reset and the T-type flip-flop 66 has been reset.
Q output of is 0. The output of the parallel shift register 62 is “000”, and none of the antennas 2, 4, and 6 is connected to the television receiver 10. Since the output of the shift register 62 is "000", the decoder 64
The D _{1 to} D ₃ inputs are also “000” and the outputs D ′ _{1 to} D ′ ₃ are “001” (see Table (a)).

In this state, when the vertical synchronizing signal falls, the shift signal and the gate signal become "1" (see FIGS. 6 (b) and 6 (f)). As the shift signal becomes "1", the shift register 62 takes in the output "001" of the decoder 64. As a result, the antenna 6 is connected to the receiver 10. Also, since the gate signal becomes "1", the analog switch 24
An audio level detection signal is detected from the audio signal level detection unit 17 to the comparison unit 20 via the and is compared with the output of the level holding unit 22, but since the level holding unit 22 does not hold anything,
The output of the comparison unit 20 is “0”. Therefore, the timing control circuit 60 does not generate a shift signal, the Q output of the T-type flip-flop 66 is also "0", and the state in which the antenna 6 is connected to the receiver 10 is maintained. Eventually, the gate signal is "0"
Then, the inverted gate signal becomes "L", the analog switch 24 is opened and the analog switch 26 is closed, and the level detection signal of the audio level detection section 17 is held in the level holding section 22. At this time, since the D _{0 to} D ₃ inputs of the decoder 64 are "0001", the D' _{1 to} D' ₃ outputs are "100" (see Table (d)).

When the next vertical synchronizing signal falls, the gate signal and the shift signal become "1" again, the shift register 62 takes in the D' _{1 to} D' ₃ outputs (100) of the decoder 64, and the antenna 2
Is connected to the receiver, and the audio level detection signal from the audio level detection unit 17 in the state where the antenna 2 is connected to the comparison unit 20 is supplied. If this is larger than the output of the level holding unit 22 holding the audio level detection signal in the state where the antenna 6 is connected, the output of the comparing unit 20 is “0”, and the state where the antenna 2 is connected to the receiver 10. Is maintained. Similarly, if the reception level at the new antenna connected to the vertical synchronization signal falls in the same manner, the connection state of the new antenna is maintained until the next vertical synchronization signal falls. That is, the antenna sequentially changes to the antennas 2, 4, and 6 each time the vertical synchronizing signal falls.

On the other hand, when the vertical synchronizing signal falls while the antenna 4 is connected to the receiver 10, the shift signal and the gate signal become "1", and the output of the parallel shift register 62 becomes "0".
01 ”, and the antenna 6 is connected to the receiver 10. At this time, the D _{0 to} D ₃ inputs of the decoder 64 are “0001”.
And the D' _{1 to} D' ₃ outputs are "100". In this state, if the reception level with the antenna 6 connected is lower than the reception level with the antenna 4 connected,
The comparison unit 20 generates the output "1". As a result, the Q output of the T-type flip-flop 66 becomes "1", and the decoder 64
Inputs D _{0 to} D ₃ of "1001" and D' _{1 to} D '
_{The three} outputs are respectively “010” (see table (g)). Since the output of the comparison unit 20 is "1", the timing control circuit 6
0 again generates the shift signal (see FIG. 6 (f)), the D' _{1 to} D' ₃ outputs "010" of the decoder 64 are taken into the shift register 62, and the antenna connected to the receiver 10 becomes , Is returned from the antenna 6 to the antenna 4. The Q output of the T-type flip-flop 66 is maintained at "1" until the next comparison unit 20 generates the output "1". At each fall, the antennas are switched in the order of antennas 4, 2, 6, ie in the reverse order.

Thus, also in the second embodiment, when the antenna is switched, if the switched antenna, for example, the antenna 4 has a higher reception level than the previous antenna, for example, the antenna 2, the switched state is maintained. If the reception level of the previous antenna 2 is higher, switching to the previous antenna 2 is immediately performed. Then, next, the antenna 6 before the antenna 2 is switched to,
If the reception level of the antenna 2 is higher, the antenna 2 is immediately switched to the antenna 2, and then the antenna 4 is switched. If the reception level of the antenna 2 is higher, the antenna 2 is switched to. In this way, the optimum antenna, in this case antenna 2, is selected. In the decoder 64, when D _{0 to} D ₃ inputs are other than (a) to (g) in the table, the D ′ _{1 to} D ′ ₃ outputs are set to “000” to prevent malfunction. This is because.

In the above both embodiments, the case of receiving the television broadcast has been described. Therefore, the gate signal and the shift signal are generated by using the vertical synchronizing signal. However, when receiving the FM broadcast or the like, a proper frequency is separately provided. Using the clock signal generator of
The clock signal may be used to generate a gate signal or a shift signal. Further, although the audio signal level is detected in both of the above embodiments, the video signal level may be detected.

〔effect〕

As described above, according to the present invention, since three or more antennas are sequentially switched to search for the antenna with the maximum level, the probability that the reception level of the receiver will be the null level is low, and good reception is achieved. can do. For example,
If the probability of a null level for one antenna is 10%, the probability of a null level is 2% for two antennas, and the probability of a null level is 0.1% for three antennas, and three or more antennas. With, the probability of a null level is greatly reduced, and good reception is possible.

Further, since the antennas are switched every time a predetermined time elapses, the best reception state can be obtained. That is,
It is possible to switch the antennas when the reception level drops below a certain level, but this will not switch the antennas unless the reception level drops. It may not be possible to find such an antenna, although it may be possible to further increase the reception level by connecting an antenna other than the one that is present. However, according to the present invention, since the antenna is switched every time a predetermined time elapses, it is possible to receive at the best reception level.

Furthermore, even though the signals from three or more antennas are compared, the circuit that holds the reception level and the comparison circuit are
Since it is sufficient to provide only one of each, the circuit configuration becomes very simple.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of a diversity receiver according to the present invention, FIG. 2 is a block diagram of a timing control circuit used in the first embodiment, and FIG. 3 is a block diagram of the third embodiment. Timing chart, FIG. 4 is a block diagram of the second embodiment, FIG. 5 is a block diagram of a timing control circuit used in the second embodiment, and FIG. 6 is a timing chart of the second embodiment. FIG. 7 is a block diagram of the decoder used in the second embodiment, FIG. 8 is a timing chart in the power-on state of the first embodiment, and FIG. 9 is a timing in the operating state of the first embodiment. It is a chart. 2, 4, 6, 8 ... Antenna, 10 ... Television receiver (receiver), 12 ... Antenna switching section, 14, 58 ... Control section, 17
...... Voice level detection unit, 20 comparison unit, 22 …… Level holding unit.

Claims (2)

[Claims] 1. Three or more antennas and one receiver,
An antenna switching means interposed between the receiver and each of the antennas for switching one of the antennas connected to the receiver, and means for generating an antenna switching timing signal at every elapse of a predetermined time; If there is a digit corresponding to three or more antennas, and one of the digits is a connection instruction state for instructing connection of the corresponding antenna to the receiver, an antenna corresponding to another digit is not connected to the receiver. A first antenna switching signal generating means for generating a first antenna switching signal, which is in a non-connection instructing state for instructing connection, and the digit in the connection instructing state moves one digit in sequence whenever the antenna switching timing signal is generated. A level detecting means for detecting a reception level of the receiver, and an output of the level detecting means when the antenna switching timing signal is not generated. Level holding means, comparing means for producing an output when the output of the level detecting means is larger than the output of the level retaining means at the time of generation of the antenna switching timing signal, and the output means of the comparing means for producing the output. Second antenna switching signal holding means for holding the first antenna switching signal generated at this time as a second antenna switching signal, and supplying the first antenna switching signal to the antenna switching means when the antenna switching timing signal is generated. Second when the antenna switching timing signal is not generated
And a means for supplying an antenna switching signal to the antenna switching means. 2. Three or more antennas and one receiver,
An antenna switching means interposed between the receiver and each of the antennas for switching one of the antennas connected to the receiver, and means for generating an antenna switching timing signal at every elapse of a predetermined time; A connection instruction state in which a digit corresponding to three or more antennas is provided, and one of the digits corresponds to an instruction to connect the antenna to the receiver, and an antenna corresponding to another digit to the receiver is received. It becomes the non-connection state that indicates the connection state, and the digit that becomes the non-connection state moves to the adjacent digit every time the above antenna switching timing signal is generated. An antenna switching signal generating means for returning the digit by one in the opposite direction to the previous moving direction and moving the digit in the connection instructing state in the opposite direction, and a receiver for the receiver. Level detecting means for detecting the level, level holding means for holding the output of the level detecting means when the antenna switching timing signal is not generated, and output of the level detecting means for holding the level when the antenna switching timing signal is generated A diversity receiving device, comprising: a comparing means for generating the direction inversion signal each time the output becomes smaller than the output of the means.